A memory prefetch control method, device, storage medium and program product

Abstract

The application discloses a memory prefetch control method and device, a storage medium and a program product, and relates to the technical field of computers. A heterogeneous logical model covering multiple access modes is constructed, a prefetch strategy candidate set is generated based on standard logical models corresponding to different access modes, the expression limitation of a single model for complex multi-modal access characteristics is broken, and the access rules in different scenarios can be comprehensively covered; through prefetch cost calculation, sorting and screening, targeted evaluation of the strategy is realized, bandwidth load aggravation and resource waste caused by redundant prefetching are avoided, and optimization of the target prefetch strategy in terms of low delay and high bandwidth utilization is ensured. The application solves the problems in the related art that a fixed logical model is difficult to adapt to dynamic and diverse memory access behaviors and resource utilization is low, and achieves the technical effects that the fixed logic does not need to be relied on, the access mode change can be dynamically adapted through flexible combination of the heterogeneous model and strategy screening, and the application is especially suitable for terminal devices with limited resources.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a memory prefetch control method, device, storage medium, and program product. Background Art

[0002] In emerging application areas such as high-performance computing, edge intelligence, and real-time data processing, the rapid expansion of complex computing tasks and data-intensive applications has placed higher demands on low-latency, high-bandwidth memory access capabilities. Especially in resource-constrained end devices such as edge nodes and embedded platforms, memory access bottlenecks have become a key factor restricting overall computing performance and energy efficiency.

[0003] In related technologies, memory prefetch mechanisms based on fixed logic models are often used, such as sequential prediction, historical statistical analysis, or simple state machine logic. These methods usually assume that memory access presents a certain stable pattern and use a single rule to speculate on future access addresses. However, in reality, the memory access behavior of programs is significantly dynamic and diverse, and may exhibit multimodal characteristics such as burst access, short-cycle repetition, high concurrency conflicts, or hotspot locality. Fixed logic strategies often find it difficult to accurately capture these complex access characteristics, which can easily lead to a decrease in prefetch hit rate and an increase in redundant prefetches, thereby increasing the system bandwidth load, wasting storage resources, and even causing access conflicts, which in turn reduces system performance.

[0004] To address this issue, some methods have introduced analysis mechanisms based on feature models such as timing diagrams and access probability statistics, or employed prediction models based on historical trajectory fitting to improve prefetching adaptability. However, most of these methods still rely on a single model structure, lacking the ability to comprehensively represent heterogeneous access characteristics. Furthermore, they fail to implement targeted cost assessment and ranking optimization during policy selection, making it difficult to switch policies in a timely manner when access patterns suddenly change.

[0005] Therefore, how to build a prefetching strategy that can cover multiple access modes, achieve rapid adaptation and high-precision prefetching of current access behavior, and thus take into account system performance, delay control and resource utilization efficiency is a technical problem that technical personnel in this field urgently need to solve. Summary of the Invention

[0006] The present application provides a memory prefetch control method, device, storage medium and program product to at least solve the problems in related technologies that fixed logic models are difficult to adapt to dynamic and diverse memory access behaviors and resource utilization is inefficient. It achieves the technical effect of dynamically adapting to access mode changes through flexible combination and policy screening of heterogeneous models without relying on fixed logic, which is particularly suitable for resource-constrained terminal devices.

[0007] The application provides a memory prefetch control method, comprising: constructing a heterogeneous logic model based on a plurality of standard logic models, wherein the plurality of standard logic models correspond to different access modes respectively; inputting a current memory access sequence into the heterogeneous logic model to generate a prefetch strategy candidate set, wherein the prefetch strategy candidate set comprises a plurality of prefetch strategies; calculating a corresponding prefetch cost for each prefetch strategy in the prefetch strategy candidate set, and sorting and screening the prefetch costs to determine a target prefetch strategy; and performing a corresponding memory prefetch operation from a target address set based on the target prefetch strategy.

[0008] The application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of any of the memory prefetch control methods.

[0009] The application also provides a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the steps of any of the memory prefetch control methods.

[0010] The application also provides a computer program product, comprising a computer program, and the computer program is executed by a processor to implement the steps of any of the memory prefetch control methods.

[0011] According to the application, the heterogeneous logic model covering a plurality of access modes is constructed, the prefetch strategy candidate set is generated based on the standard logic models corresponding to different access modes, the expression limitation of a single model to complex multi-modal access characteristics is broken, and the access rules in different scenarios can be comprehensively covered; through the calculation, sorting and screening of the prefetch cost, the targeted evaluation of the strategy is realized, the bandwidth load aggravation and resource waste caused by redundant prefetch are avoided, and the optimization of the target prefetch strategy in terms of low delay and high bandwidth utilization is ensured. The application solves the problems in the related art that the fixed logic model is difficult to adapt to dynamic and diverse memory behaviors and resource utilization is low, and achieves the technical effect that the access mode change can be dynamically adapted through the flexible combination and strategy screening of the heterogeneous model without relying on the fixed logic, and the application is especially suitable for terminal devices with limited resources. BRIEF DESCRIPTION OF DRAWINGS

[0012] In order to more clearly illustrate the embodiments of the application, the drawings needed in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0013] Figure 1 A flowchart of a memory prefetch control method provided by an embodiment of the application.

[0014] Figure 2 A schematic diagram of a memory prefetch control device is provided for an embodiment of the present application.

[0015] Figure 3 A schematic diagram of an electronic device is provided for an embodiment of the present application.

[0016] Figure 4 A schematic diagram of a computer readable storage medium is provided for an embodiment of the present application. DETAILED DESCRIPTION

[0017] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, any other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0018] It should be noted that, in the description of the present application, the terms "comprise", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such a process, method, article or device. The terms "first", "second" and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0019] In order for those skilled in the art to better understand the technical solutions of the present application, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0020] As Figure 1 The embodiments of the present application provide a memory prefetch control method. The method is described in detail in combination with the execution flow of the memory prefetch control method. The method comprises:

[0021] S11: constructing a heterogeneous logic model based on a plurality of standard logic models, the plurality of standard logic models respectively corresponding to different access modes.

[0022] Specifically, by integrating a plurality of standard logic models, a heterogeneous logic model framework capable of coping with a plurality of memory access modes is constructed. The main purpose of this step is that when facing a memory access environment with highly dynamic access behavior and variable patterns, instead of relying on a single model to make prefetch decisions, a plurality of types of standard logic models are used to cooperatively perceive access behavior and evaluate access rules from different modeling perspectives, thereby providing a more accurate and robust logic basis for subsequent prefetch strategy generation.

[0023] The standard logic model can be a structured modeling manner designed for different access behavior characteristics, for example: some models are better at identifying time-dependent access sequences, such as sequential access or repeated pattern access (typical such as AIG (And-Inverter Graph), XMG (XOR-Inverter Graph), and other logic models); and some models are more biased towards capturing statistical characteristics or context correlations, such as access heat, jump distance distribution, and other statistical logic models. These standard logic models respectively extract predictability information from different dimensions of access sequences and are integrated into a heterogeneous logic model through a unified interface. The heterogeneous logic model does not simply stack each standard model, but enables or adapts through certain combination mechanisms or selection mechanisms (for example, based on the weight switching or model fusion mechanism of access characteristics), thereby achieving the generalization modeling capability of access patterns at the model structure level.

[0024] It should be understood that this step is not to construct a new model for each memory access sequence, but to prepare multiple model templates with fixed structure but different logic orientation in advance, and to activate and combine these models on demand at runtime to cope with different types of access situations. This structural heterogeneity + logic coordination modeling method has better pattern adaptability and generalization ability of prefetch strategy generation compared to the single model prediction method of related technologies.

[0025] S12: input the current memory access sequence into the heterogeneous logic model to generate a prefetch strategy candidate set, the prefetch strategy candidate set including a plurality of prefetch strategies.

[0026] Specifically, the constructed heterogeneous logic model is used to jointly model and analyze the current input memory access sequence, thereby generating a set of prefetch strategy candidates for the current access behavior. The prefetch strategy candidate set represents a variety of possible prefetch paths or operation methods, providing strategy space support for subsequent cost evaluation and decision screening. Since memory access behavior is highly dynamic and uncertain, it is not appropriate to directly output a unique prefetch result, but a candidate set needs to be constructed to integrate the analysis perspectives of each logic model, thereby improving the coverage and robustness of the strategy.

[0027] Specifically, the heterogeneous logic model receives a current memory access sequence (e.g., the last several memory accesses), and then calls multiple standard logic models in parallel or alternately to perform reasoning. Each model proposes one or several possible prefetch suggestions based on its modeling method and preferred features (e.g., temporal dependency, statistical distribution, context pattern, etc.). For example, one model may suggest prefetching address X based on the jump distance rule, while another model may suggest prefetching addresses Y and Z based on the access frequency trend. After processing by a preset fusion strategy, the suggestions form a candidate set of prefetch strategies at the current time.

[0028] In addition, to enhance the flexibility and accuracy of prediction, the prefetch strategies in the candidate set can include not only specific prefetch address targets, but also strategy-level parameters such as prefetch depth, coverage, trigger condition, instruction granularity, etc. By converting the model output into a strategy representation and collecting the set, this step essentially completes an abstract conversion from pattern recognition to strategy proposal, which not only preserves the information dimension of model reasoning, but also leaves optimization space for the next step of strategy cost evaluation and screening. This candidate strategy set generation method has high scalability and can be flexibly adapted to different computing platforms and application scenarios.

[0029] It should be understood that the AIG structure corresponds to a timing diagram model that maps a sequence of continuous memory access addresses to a timing dependency graph, or in other words, maps the memory access sequence to a directed acyclic graph (DAG), capturing the sequential rules in program execution. Each node represents a memory address (e.g., addresses A, B, and C). The edges represent the access order between the addresses (e.g., A→B→C). The timing relationship is described by AND-OR operations. For example, if the access to address B must follow the access to address A, the logical expression is . Assuming the access sequence is A→B→C→B→D, the timing diagram contains the paths A→B→C and (B→D), and the rule can be derived by the AIG structure: if B is accessed, then prefetch C and D.

[0030] The statistical model of the XMG structure is based on the access frequency and locality features to construct statistically driven logic rules. The implementation is XOR-Majority (XOR-Majority) operation, for example, if at least two of addresses X, Y, and Z are frequently accessed, then prefetch the next address. High-frequency access addresses are given higher weights. Assuming that addresses X and Y are accessed 10 times in a short period of time, and address Z is accessed 2 times, the statistical model generates the rule: if X and Y are accessed simultaneously, then prefetch their adjacent addresses.

[0031] If the isomorphic logical model includes the above two structures (AIG and XMG) of the standard logic model, the memory access sequence is mapped to the AIG and XMG structures at the same time. The same data can derive complementary rules under different logical perspectives. For example: AIG focuses on timing dependency: after accessing A, B needs to be accessed; XMG focuses on statistical combination: A and C often appear at the same time, and D needs to be prefetched.

[0032] The core steps of the strategy generation algorithm include: key path extraction, identification of high-frequency paths (such as loop access sequences), generation of deep prefetching strategies (prefetching future 3-5 addresses); locality analysis, dividing regions according to access frequency (such as hot cache lines), generating coverage prefetching strategies (prefetching adjacent 64B data blocks). Finally, a candidate set of prefetching strategies is obtained , There are n prefetching strategies, E is the set of all prefetching strategies, and each prefetching strategy contains parameters such as prefetching depth and coverage range. This process is implemented through a hybrid structure selection framework to ensure that the candidate strategies can capture both timing rules and statistical characteristics.

[0033] The logical function expression corresponding to the isomorphic logical model is: . In the formula, is the corresponding logical function value, is the logical kernel function, which is AND-OR in AIG and XOR-Majority in XMG. is the weight parameter corresponding to the i-th step, reflecting the influence of historical access on current prediction (for example indicates the most critical recent access), and the weight parameter is usually a fixed value or manually adjusted. i is the index, used to traverse the sequence from 1 to k. k is the maximum number of historical accesses considered by the logical kernel function, and in the expression, k defines the range of summation, i.e. considering the historical access data back to k steps from the current time step t. represents the memory access address at time step t, represents the memory access address at time step t-i, i.e. the memory access address at i steps before the current time step t.

[0034] In addition, the weight matrix corresponding to the weight parameter can also be optimized through ridge regression to avoid overfitting. For example, if a strategy performs well in the training set but poorly in the test set, the regularization term will suppress its weight.

[0035] For example, in an actual case, an alternating memory access address sequence and , the letters A, B, C, D, E in each sequence represent the corresponding memory access addresses, and AIG modeling and XMG modeling are performed on them respectively to generate prefetch strategies, and a candidate set is given. Specifically, AIG modeling obtains two paths, path 1 is A→B→C→D, and path 2 is A→B→E. The strategy generated based on this is "when accessing B, prefetch C and E at the same time"; the statistical results of XMG modeling show that B appears 4 times, A appears 2 times, and C, D, and E appear 1 time each. The generated strategy is "if B is accessed, prefetch its adjacent address (C or E)". The candidate set includes: prefetch depth = 2 (B→C→D); coverage = 2 cache lines (prefetch 64B before and after B). Among them, it is necessary to understand that the memory access address sequence The correct approach is to construct the path as "A→B→C→D" or "A→B→C and B→D". The specific implementation is determined according to the current actual scenario.

[0036] S13: For each prefetch strategy in the prefetch strategy candidate set, calculate the corresponding prefetch cost, sort and filter the prefetch costs, and determine the target prefetch strategy.

[0037] Specifically, within the set of candidate prefetch strategies, the target prefetch strategy that best suits the current memory access scenario is identified. Since candidate strategies are often diverse and their effectiveness can vary significantly under different system states, static selection based solely on model scores or historical performance often fails to guarantee global optimality. To this end, this step introduces a dynamic evaluation mechanism using prefetch cost as a metric to comprehensively rank and screen strategies from multiple perspectives.

[0038] The composition of the prefetch cost is typically based on a trade-off between multiple factors, such as the memory access latency (or resource overhead) caused by executing a particular strategy and the prefetch hit rate benefit achieved by the strategy. The latency cost represents the extent to which the strategy's execution consumes system resources such as memory bandwidth and access paths, while the hit rate benefit reflects the strategy's effectiveness—that is, whether the prefetched data can actually be used in subsequent accesses. Based on this, these two dimensions are combined into a cost metric using a certain weighting method, and all candidate strategies are normalized and ranked to determine the strategy with the optimal performance-to-cost ratio.

[0039] This step not only evaluates policies based on static rules but also incorporates dynamic system feedback, such as current memory load, cache hit rate, and bandwidth bottlenecks, to adjust the weights of each evaluation dimension, thereby demonstrating environmental adaptability. Furthermore, this step offers a degree of robustness. When the cost values ​​of some policies deviate significantly due to system anomalies or sample drift, the evaluation mechanism can proactively identify and eliminate these anomalous policies, preventing misguided prefetching behavior. Finally, through a sorting and screening mechanism.

[0040] S14: Perform the corresponding memory prefetch operation from the target address set based on the target prefetch strategy.

[0041] This step applies the selected target prefetch strategy to the memory system, triggering the corresponding prefetch behavior to load data that may be accessed in advance from the target address set, thereby optimizing the processor's access efficiency to the memory. The target address set is usually a sequence of addresses or an address pattern derived from the prefetch strategy, and its composition can be determined based on the pattern matching results of the current access sequence, the access density distribution, or the access offset trend, among other multi-dimensional features. The prefetch operation does not directly affect the current processing flow, but rather loads data into the cache or other buffer area in advance without blocking the main thread.

[0042] During execution, the dynamic scheduling of prefetch depth (e.g., prefetching N-step addresses) and prefetch granularity (e.g., by cache line or page) is combined with real-time running states such as current memory bandwidth, cache occupancy, and access concurrency to determine whether to execute, delay execution, or partially execute the target prefetch strategy immediately. This process emphasizes the balance between latency sensitivity and hit probability to ensure that the prefetch behavior itself does not interfere with the bandwidth or contaminate the cache of the main thread, thereby steadily improving the overall throughput efficiency and response capability of the system.

[0043] In addition, the prefetch operation performed in this step also lays the foundation for subsequent feedback learning mechanisms. It can monitor whether the prefetched data is actually hit in subsequent access and record the hit situation as historical samples, thereby forming a lightweight strategy verification loop. This feedback is not only used for strategy optimization, but also for improving the recognition accuracy of access patterns, making the entire prefetch system more adaptable and evolutionary.

[0044] In an exemplary embodiment, for each prefetch strategy in the prefetch strategy candidate set, the corresponding prefetch cost is calculated, including: for each prefetch strategy in the prefetch strategy candidate set, the corresponding delay cost and hit rate gain are calculated; the delay cost represents the duration of the memory bus occupied by the execution of the prefetch strategy, and the hit rate gain represents the proportion of the prefetched data that is actually accessed; based on the delay cost and the hit rate gain, the corresponding prefetch cost is calculated.

[0045] In this embodiment, the calculation of the prefetch cost for each prefetch strategy candidate aims to find the optimal strategy from multiple potential strategies for actual memory prefetching operations. This process first relies on two core performance metrics, namely delay cost and hit rate gain. Delay cost describes the system burden caused by the execution of the prefetch strategy, mainly embodied in how much memory bus bandwidth the strategy occupies, how much data transfer it triggers, and the possible blocking or interference of these transfer processes on current or future requests. The evaluation of this delay cost is usually based on the amount of data prefetched, the triggering frequency, the memory level of the target address (such as main memory or remote NUMA (Non-Uniform Memory Access) node), and the bandwidth utilization and concurrent access of the current system, among other dimensions.

[0046] The corresponding hit rate gain is used to evaluate the effectiveness of the prefetch strategy, i.e., the probability or proportion of the data prefetched by the strategy being hit in subsequent actual access. This indicator reflects the contribution of prefetch behavior to the overall hit rate improvement, thus indirectly representing the improvement ability of the strategy for system access delay. Hit rate gain can be predicted based on historical access data, or modeled in combination with access pattern classification (such as sequential access, random access, cyclic access, etc.) and address locality features. In some implementations, short-term sliding windows or long-period statistical mechanisms are also introduced to smooth the hit results, in order to improve the stability and prediction accuracy of the indicator.

[0047] Once the delay cost and hit rate gain are quantified as specific values, they are input into a predefined cost function to calculate the final prefetch cost indicator. This cost function is usually a weighted combination model, which can be linear combination or use a nonlinear mapping structure, depending on the system target. The purpose of weighting is to provide adaptability for system preferences in different operating states: for example, in high bandwidth occupation situations, more attention may be paid to delay cost, thereby reducing prefetch interference; while in low hit rate stages, it may be more inclined to relax the constraints on delay and prioritize hit gain. The construction of such a cost function and dynamic weight adjustment mechanism enables the system to achieve flexible balance between multiple performance indicators and realize adaptive optimization.

[0048] Finally, the prefetch cost serves as a unified indicator to evaluate the pros and cons of each candidate strategy, and is used for sorting and screening operations to ensure that the target prefetch strategy selected by the system is both effective and does not cause excessive interference to the system load. Through the above evaluation and comparison mechanism, not only is the quantitative decision of the prefetch strategy realized, but also a foundation is laid for subsequent strategy feedback learning and dynamic adjustment.

[0049] On the basis of the above-mentioned embodiments: in an exemplary embodiment, based on the delay cost and the hit rate gain, the corresponding prefetch cost is calculated, comprising: for each prefetch strategy, obtaining a first weight corresponding to the delay cost and a second weight corresponding to the hit rate gain; based on the delay cost, the first weight, the hit rate gain and the second weight, the corresponding prefetch cost is calculated.

[0050] In this embodiment, the evaluation of the prefetch cost not only depends on the basic delay cost and the hit rate gain itself, but also further introduces a weight parameter to adapt and adjust the system requirements under different running scenarios. This weight-based cost modeling method embodies a strategy of balanced optimization under multiple indicators. Specifically, for each candidate prefetch strategy, the corresponding delay cost and hit rate gain are obtained respectively, and two independent weight factors, i.e. the first weight of the delay cost and the second weight of the hit rate gain, are introduced to reflect the degree of attention of the current system to different performance targets (such as delay minimization or hit rate maximization).

[0051] The first weight is used to measure the sensitivity of the current system to the delay cost. When the bandwidth pressure is large or the prefetch behavior may compete for resources with the main thread, the first weight is dynamically increased to increase the influence of delay on the overall evaluation in the cost calculation. Conversely, when the bandwidth resource is relatively abundant, the first weight is appropriately reduced to relax the constraint on the delay overhead, allowing more potentially valuable prefetch strategies to be selected. Similarly, the second weight reflects the degree of attention of the system to the hit rate gain. If the current cache hit rate is low, the second weight is increased so that strategies with high hit rate perform better in cost calculation to achieve the goal of quickly improving cache utilization efficiency.

[0052] Once the delay cost, the hit rate gain and their corresponding weights are obtained, the prefetch cost is calculated based on a weighted combination formula. The delay is a negative indicator (the higher the worse), and the hit rate is a positive indicator (the higher the better). This difference combination allows the cost value to reflect the overall advantages and disadvantages of the strategy in multiple performance indicators on a unified scale. It is worth noting that this structure allows the system to directly numerically sort multiple strategies, making the subsequent screening operation efficient, clear and easy to automate.

[0053] Through the above design, the evaluation system of the entire prefetch strategy realizes high flexibility and dynamic adaptability. The introduction of the weight not only avoids the limitation of hard coding a fixed objective function, but also provides adjustable control parameters for subsequent feedback optimization and online learning. In actual deployment, these weights can be adjusted in real time according to the runtime statistical information, thereby supporting the effectiveness and resource sensitivity of the strategy decision under different loads, application types or access patterns.

[0054] In an exemplary embodiment, further comprising: monitoring bandwidth utilization and cache hit rate of the memory in real time; adjusting the first weight according to the bandwidth utilization; adjusting the second weight according to the cache hit rate.

[0055] In this embodiment, in order to improve the adaptability and real-time performance of the prefetch control strategy, a dynamic monitoring mechanism of runtime performance indicators is introduced, which specifically includes real-time sampling and analysis of memory bandwidth utilization and cache hit rate. Bandwidth utilization reflects the occupancy degree of the current memory bus, which is an important indicator for measuring whether there is memory congestion in the system; the cache hit rate reveals the hit effect of the prefetch strategy on the actual access data, which is a key parameter for evaluating the prefetch benefit. By continuously monitoring these two indicators, the system can dynamically perceive the resource pressure and prefetch effect in the running state, thereby providing a basis for adjusting the prefetch strategy.

[0056] After obtaining these indicators, the weight parameters used to calculate the prefetch cost are adjusted according to the actual situation. When a high bandwidth utilization is detected, it indicates that the current system resources are tight, and the prefetch operation may compete with normal access; at this time, the weight of the delay cost in the cost function is increased, that is, the value of the first weight is increased, so that the strategy with high delay cost gets a lower score in the sorting and is not easily selected. In this way, potential bandwidth conflicts can be suppressed, and interference of prefetch on the main thread can be avoided. Conversely, if the bandwidth utilization is low, it indicates that the system has sufficient idle resources, and the first weight can be reduced to tolerate a certain degree of prefetch overhead in exchange for potential cache benefits.

[0057] Similarly, when a low cache hit rate is detected, it indicates that the hit efficiency of the current prefetch strategy is not ideal, and there is a problem of prefetch invalidation. At this time, the weight of the hit rate gain is increased, that is, the second weight is increased, to encourage strategies with higher hit rates to obtain higher comprehensive scores in the sorting, which helps to select strategies that can improve the cache hit rate. Conversely, if the cache hit rate is already at a high level, the second weight can be reduced to avoid excessive dependence on the hit rate and give more space to other optimization targets such as delay control.

[0058] Through the above mechanism, the strategy cost function dynamically responds to the runtime state, so that the strategy evaluation is no longer based on static rules, but combines the current system load and performance requirements for real-time trade-off. This feedback adjustment mechanism enhances the adaptive ability of the prefetch system and can maintain optimal prefetch effect and system stability in various running scenarios.

[0059] It should be understood that the delay cost (Cdelay) ) reflects the memory bus occupation time caused by the execution of a certain prefetch strategy, which is the core indicator of measuring the bandwidth resource consumption of prefetch operation. Its physical meaning is that in a prefetch process, the system needs to schedule multiple addresses of data into the cache, which occupies the limited memory transmission channel, thereby introducing potential delay. The calculation method is: = the number of prefetch addresses x single address transmission time + control overhead. If strategy e needs to prefetch 3 addresses, each address takes 2 cycles, and the control overhead is 1 cycle, then = 3 x 2 + 1 = 7, is the delay cost corresponding to the prefetch strategy e.

[0060] Hit rate gain describes the effectiveness of the prefetch strategy, that is, the proportion of the prefetch data actually hit by subsequent access, which reflects the accuracy of the strategy. The higher the index, the less invalid prefetch, and the greater the performance benefit brought by prefetch. The calculation method is = the number of hit addresses / the number of prefetch addresses. If strategy e prefetches 5 addresses, of which 3 are used by subsequent access, then = 3 / 5 = 0.6, is the hit rate gain corresponding to the prefetch strategy e.

[0061] After the calculation of the above two indicators, the system will integrate them into a weighted total cost function to form the final evaluation indicator of the candidate strategy. The cost function formula is: ; is the total cost corresponding to the prefetch strategy e, is the first weight, representing the trade-off parameter of the system's sensitivity to bandwidth resources, is the second weight, used to regulate the system's preference for prefetch hit effect; if the system detects bandwidth tension, it can appropriately increase a to suppress strategies with high bandwidth consumption; if the hit rate is low, it can increase g to prefer high hit strategies.

[0062] Comprehensive example: assume that strategy 1 is: , ; strategy 2 is: , ; strategy 1 has lower cost and is preferentially selected as the target strategy for final execution.

[0063] When evaluating the cost of candidate combinations, input the pre-selected strategy candidate set generated in the above steps . Traverse all pre-selected strategies: for the i-th prefetch strategy , calculate its and . Then optimize the regularization weight, and the formula is , in which is the candidate strategy feature matrix (each row corresponds to the strategy delay, hit rate, etc.), is the transpose matrix of , is the regularization term (to prevent overfitting, to suppress the strategy that performs well on the training set but poorly on the test set), L represents the strategy target correlation matrix, which connects the strategy features and the decision target, and M represents the regularization strategy feature matrix, is the inverse matrix of M. Finally, through sorting selection, the minimum cost strategy is selected in ascending order of total cost . , so as to complete the evaluation and optimization of the pre-selected strategy.

[0064] In actual cases, the candidate strategies include two kinds: is the prefetch depth = 2 (delay = 6 cycles, hit rate = 70%), is to cover adjacent cache lines (delay = 10 cycles, hit rate = 90%), and the parameter setting is when the bandwidth is tight . By calculating the total cost, , , the result is to select , because it is more optimal when the bandwidth is tight.

[0065] Through the above cost function mechanism, not only the performance of the candidate strategy is comprehensively evaluated, but also the weight parameters can be dynamically adjusted according to the system resource status in the running state, so that the prefetch control can not only consider the bandwidth efficiency, but also ensure the access hit rate, so as to realize efficient and intelligent adaptive prefetch management.

[0066] In an exemplary embodiment, the first weight is adjusted according to the bandwidth utilization, including: when the bandwidth utilization is greater than a first preset threshold, the first weight is adjusted to increase the influence of the delay cost; the second weight is adjusted according to the cache hit rate, including: when the cache hit rate is less than a second preset threshold, the second weight is adjusted to increase the influence of the hit rate gain.

[0067] In this embodiment, by monitoring the usage status of the memory bandwidth in real time, the influence weight of the delay cost in the prefetch cost is dynamically adjusted. When it is detected that the current bandwidth utilization exceeds a preset first threshold (for example, 80%), it indicates that the bus resource tends to be tight, at this time the strategy should pay more attention to the occupation of the bus resource. Therefore, the first weight corresponding to the delay cost is automatically increased, so as to strengthen the preference for the low-bandwidth-occupying strategy in the cost evaluation, and avoid the strategy with high delay and high prefetch amount to further aggravate the bus load.

[0068] Meanwhile, the cache hit rate is continuously tracked to evaluate the effectiveness of the prefetching strategy in actual operation. When the cache hit rate continuously falls below a second preset threshold (e.g., 60%), it indicates that the current prefetching strategy is not effective enough, and there are many invalid prefetching operations. To guide the system to preferentially select a strategy with better hit effect, the second weight of the hit rate gain is appropriately increased, so that the influence of the hit rate factor in the cost function is enhanced in future strategy evaluation, thereby improving the accuracy and resource use efficiency of the overall prefetching of the system.

[0069] For example, the initial state is: , When the bandwidth utilization is monitored to reach 90%, it is adjusted to , At this time, the system is more inclined to the low-delay strategy.

[0070] Directly inverting the matrix may cause numerical instability (e.g., matrix singularity), and adding a regularization term increases a small perturbation to the diagonal elements of the matrix to ensure invertibility. It is equivalent to applying a "conservative constraint" to the weight of the strategy to avoid overfitting of a certain strategy in the training set.

[0071] In the related art, 1000000 units are required to store a 1000x1000 matrix; through Cholesky decomposition, it is compressed into a single-dimensional array by utilizing symmetry, and only 500500 units are required, the memory occupancy is reduced by half, and the calculation speed is increased by 7 times. For example, if the prefetching strategy one is fast but has a low hit rate, and the prefetching strategy two is slightly slower but has a high hit rate, the system will dynamically select according to the current memory bandwidth state. This process uses ridge regression to optimize the weight matrix and prevents overfitting through regularization to ensure the robustness of the strategy selection.

[0072] In an exemplary embodiment, after calculating the corresponding delay cost and hit rate gain for each prefetching strategy in the candidate set of prefetching strategies, the memory prefetching control method further comprises: detecting the delay cost and hit rate gain of each prefetching strategy; marking the prefetching strategy corresponding to the delay cost exceeding the first standard range or the hit rate gain exceeding the second standard range as an abnormal prefetching strategy; and eliminating the abnormal prefetching strategy from the candidate set of prefetching strategies.

[0073] In this embodiment, to further improve the robustness and execution stability of the memory prefetching strategy, after calculating the delay cost and hit rate gain of the candidate prefetching strategy, a round of abnormal value detection mechanism is performed. Specifically, based on historical statistical data, a first standard range of the delay cost (e.g., mean , a second standard range of hit rate gain. If the delay cost of a strategy is significantly higher than the normal interval (i.e. exceeds the upper limit of the first standard range), it indicates that it may cause abnormal occupation of system bandwidth resources; if the hit rate gain is significantly lower than the normal interval (i.e. lower than the lower limit of the second standard range), it indicates that the strategy may have a large number of invalid prefetches. Such strategies are uniformly marked as abnormal prefetch strategies, and are excluded from the candidate set in the current round of evaluation to avoid entering the final ranking and selection process.

[0074] In addition, an adaptive fallback mechanism is also introduced to prevent continuous strategy failure in extreme or mutant access patterns. This mechanism counts the number of candidate strategies after screening in consecutive rounds, and if no prefetch strategy passes the cost calculation and abnormal exclusion process in three consecutive rounds (i.e. no effective strategy), a conservative prefetch strategy is temporarily enabled, such as forcibly reducing the prefetch depth to 1 and only prefetching the minimum access interval. This conservative strategy can ensure the minimum level of prefetch response while avoiding resource waste and load surge, providing a buffer window for subsequent re-adaptation of logical model parameters and strategy generation.

[0075] In an exemplary embodiment, the memory prefetch control method further comprises: for each prefetch data corresponding to a prefetch strategy, constructing a loss function according to the predicted hit probability and the actual hit probability; performing truncated backpropagation on the memory access sequence based on the loss function, and retaining the backpropagation gradient information of a preset truncation window; the preset truncation window includes a preset step number; optimizing the model parameters of the heterogeneous logical model according to the backpropagation gradient information and a preset learning rate, the model parameters including input sensitivity parameters and historical decay parameters, the input sensitivity parameters representing the influence weight of new memory access sequences on the prefetch strategy, and the historical decay parameters representing the influence weight of historical memory access sequences in the update of the prefetch strategy.

[0076] In this embodiment, for the dynamic adaptability optimization problem of memory prefetch strategies, a model parameter training method based on truncated backpropagation is proposed to reduce training resource consumption and improve update response efficiency. This method first measures the difference between the predicted hit probability and the actual hit probability as the optimization target by constructing a loss function. The loss function is defined as wherein, represents the actual hit probability of the kth memory prefetch strategy, and N represents the number of prefetches. The cross-entropy loss measures the difference between the predicted hit probability and the actual hit probability If the predicted hit probability is 80% (p = 0.8), the actual hit probability is (p = 0.8), and the actual hit probability is (p = 0.8). ​), the loss is -ln0.8≈0.223. On this basis, instead of using the traditional long sequence full gradient back propagation method, a truncated back propagation strategy is adopted, and gradient calculation and parameter update are only performed within a preset truncated window (such as the last 10 steps of memory access). The truncated window is limited in steps, avoiding excessive memory storage requirements due to the accumulation of historical states.

[0077] From a physical point of view, the back propagation process of traditional neural networks or logical models needs to retain all the intermediate calculation results (such as activation values and gradients) of all time steps, so that the memory occupation increases linearly with the number of time steps, making it difficult to deploy in resource-limited hardware environments. Through the truncation strategy, only the latest period of access behavior is focused on, and the contribution of early historical gradients is ignored, thereby significantly reducing the state storage amount. For example, if a training sequence is as long as 1000 steps, and 1MB of intermediate state needs to be stored at each step, the cost of complete retention is 1GB of memory overhead; if only the gradient information of the last 10 steps is retained, the storage overhead is only 10MB, reducing by more than 90%.

[0078] In addition, to solve the problem of loss of long-term dependence information caused by truncated gradients, this embodiment introduces a dual strategy of dynamic adjustment and mixed training. During operation, if it is detected that there is obvious periodicity in the memory access sequence (such as a period of about 100 steps), the truncated window length is dynamically expanded (such as from 10 steps to 20 steps) to temporarily retain more historical states for parameter update, thereby capturing periodic behavior characteristics.

[0079] In addition, a periodic full gradient training mechanism is also integrated, that is, a complete back propagation training is performed every certain number of steps (such as 100 steps) to calculate the gradient information of all historical steps to correct the deviation that may be caused by short-term truncated training. This mixed training method takes into account resource efficiency and model accuracy, making the prefetching strategy have stronger adaptability and stability when dealing with complex access patterns that coexist with short-term bursts and long-term regularities.

[0080] The parameter update formula is: , . is an input sensitivity parameter, representing the control of the influence of new input on the current state (such as the sensitivity of the prefetching decision); is a historical decay parameter, representing the decay rate of the historical state (such as the forgetting rate of the old access pattern), j, f, x, n in the parameter update formula represent new input, activation function, current state and index respectively. T represents the size of the truncated window, that is, only the gradient information of the last T steps is retained for parameter update. The truncation is realized by: only calculating the gradient of the last time step (t-T+1); discarding earlier time steps (such as t-T+2). and . intermediate state of the model parameters The gradient computation at the current time T only depends on and without the need to save data to .

[0081] Further, to speed up the matrix operation involved in the gradient computation process, the embodiment introduces numerical optimization techniques such as Cholesky decomposition for accelerated updating of high-dimensional weight matrices. Such methods reduce the computational complexity of the original matrix inversion or linear equation solution from high to low order, while having good parallelism and cache friendliness on various hardware platforms. While ensuring the accuracy of model parameter (such as input sensitivity parameter, historical decay parameter) updating, the computational load and resource consumption are effectively controlled, making the prefetch control scheme practical for deployment on resource-constrained platforms such as edge processors and embedded chips.

[0082] For example, to train a prefetch model, the input is the last 5 memory addresses, and the output is the prefetch suggestion.

[0083] Forward propagation: input sequence , generate candidate strategies (such as prefetch C and D) through AIG and XMG models, and calculate hit probability (predicted hit 3 / 4 address).

[0084] Loss calculation: actual hit addresses are C and ; loss L = -ln0.75 ≈ 0.287.

[0085] Backpropagation (truncated): only the gradients of the last two steps (accessing B and D) are retained; update parameters p and q: where is the preset learning rate, p new is the updated input sensitivity parameter, is the updated historical decay parameter, for example ; matrix acceleration: use Cholesky decomposition to update the weight matrix, and the memory occupancy is reduced from 4MB to 1MB. Using 1-D Cholesky decomposition to speed up matrix operations, the originally required 1000x1000 matrix is compressed into a single-dimensional array, reducing memory occupancy to one quarter. This optimization enables the model to be deployed on resource-constrained edge devices while ensuring accuracy.

[0086] In an exemplary embodiment, further comprising: calculating a difference degree between the current memory access sequence and the previous memory access sequence; judging whether the current access pattern has changed compared with the previous access pattern based on the difference degree; if the change occurs, triggering a logic switching mechanism of the heterogeneous logic model to switch to a logic model corresponding to the current access pattern.

[0087] In this embodiment, in view of the fact that the memory access pattern may change over time, a dynamic monitoring and logic switching mechanism is introduced to improve the response capability of the prefetch strategy to the change of the access pattern. The core of the mechanism is to judge whether the access pattern has changed significantly by calculating the difference degree between the current access sequence and the historical access sequence in real time, so as to trigger the logic switching of the heterogeneous logic model and select the prefetch strategy generation path that matches the current pattern better.

[0088] In order to measure the difference between the access patterns, the access sequence difference degree is selected as the key monitoring index. Specifically, the current access sequence and the access sequence of the previous time window can be represented as Scurr and Sprev respectively, and the difference degree between them can be represented as D(Scurr, Sprev) by calculating the Euclidean distance or Hamming distance. For example, when the running state is switched from sequential traversal to random jump, the distance value between the two access sequences will increase significantly. For example, the difference degree , The difference degree is , which represents the memory access sequence at the current time t (such as the last 100 addresses); , which represents the memory access sequence at the previous time t-1; , which represents the Euclidean distance (or Hamming distance) of the sequence.

[0089] A preset threshold is set to determine whether the access pattern has changed. When the difference degree , it is considered that the current access pattern has deviated significantly from the original pattern, so as to trigger the reconstruction of the prefetch strategy. The physical meaning is that the change of the access behavior will cause the failure of the original strategy based on a certain type of pattern (such as sequential access), so the prefetch path must be dynamically adjusted to maintain high hit rate and low delay.

[0090] Once the logic switching mechanism is triggered, the optimal logic model will be selected again according to the current access characteristics (such as switching from the time sequence dependent model to the statistical feature model), to ensure that the subsequent generated prefetch strategy is highly adapted to the current access behavior. This dynamic reconstruction mechanism significantly enhances the robustness and self-adaptive ability of the system in the process of multi-task and multi-stage running.

[0091] For example, the memory access sequence at the previous time t-1 is: (sequential access); the memory access sequence at the current time t is: (random jump); calculate difference . Set a preset threshold (e.g. ), when , it is determined that the access pattern has changed significantly, and the difference exceeds the threshold, indicating that the original prefetch strategy may fail, and the logical reconstruction needs to be triggered.

[0092] In an exemplary embodiment, a logical switching mechanism of a heterogeneous logic model is triggered to switch to a logical model corresponding to the current access pattern, including: based on the characteristics of the current access pattern, selecting a target standard logic model adapted to the current access pattern from a plurality of standard logic models contained in the heterogeneous logic model; disabling the strategy generation function of other standard logic models in the heterogeneous logic model that are not adapted to the current access pattern; and regenerating a prefetch strategy candidate set based on the target standard logic model.

[0093] In this embodiment, when it is monitored that the current access pattern has changed significantly from the existing pattern, the logical switching mechanism of the heterogeneous logic model will be triggered to ensure that the prefetch strategy generation logic always matches the access characteristics. The first step of this logical switching mechanism is to identify the characteristics of the current access pattern, such as whether it has sequential, periodic, local or random characteristics, etc. The pattern discrimination is completed by statistical indicators such as address spacing distribution, repetition frequency or similarity of historical patterns of the access sequence.

[0094] For example, disable the old model, pause the strategy generation of the current logical representation (such as the timing graph AIG); activate the new model, select the adapted logical representation according to the characteristics of the current pattern; strong sequentiality, use timing graph (AIG); strong randomness, switch to statistical model (XMG); generate new strategy, regenerate the pre-selected strategy candidate set according to the steps of the above embodiment. For example, the initial pattern is sequential access, and the strategy "prefetch the next 2 addresses" is generated using AIG; monitor , switch to XMG, and generate the strategy "prefetch adjacent cache lines of high-frequency addresses".

[0095] It should be understood that the selection of the adapted target standard logical model here to regenerate the set of prefetch strategy candidates does not conflict with the step S12 of "inputting the current memory access sequence into the heterogeneous logical model to generate a set of prefetch strategy candidates". Specifically, in S12, during the initial stage or periodic evaluation, the heterogeneous logical model is used to simultaneously consider timing dependencies and statistical characteristics to generate a set of prefetch strategy candidates with different prefetch depths and coverages. This is done to ensure that no matter how the actual access pattern changes, there are sufficient strategies to choose from. The reason for selecting the target standard logical model in this embodiment is that during operation, when changes in the access pattern are detected and the prefetch strategy needs to be adjusted, a logical representation that best suits the current access pattern is selected for strategy generation. This selection is based on the principle of optimal matching of efficiency and effect, that is, finding the optimal solution under given conditions. Although multiple standard logical models (such as AIG and XMG models) are used simultaneously in step S12 to generate a set of prefetch strategy candidates, at any given point in time (especially after a change in the access pattern), the system will only activate one model that best suits the current scenario to make real-time decisions. This is because different access patterns may be more suitable for different prediction models, and enabling two models at the same time may result in waste of resources or increased decision complexity. Therefore, although S12 adopts multi-model joint modeling to generate a rich and diverse set of prefetch strategy candidates, this embodiment emphasizes selecting the most appropriate single model based on the current access pattern at a specific moment to achieve efficient prefetch decisions. There is no conflict between the two, but rather a complementary relationship. The former provides a broad basis for selection, while the latter ensures accuracy and efficiency in practical applications.

[0096] In an exemplary embodiment, based on the characteristics of the current access pattern, a target standard logical model adapted to the current access pattern is selected from multiple standard logical models included in the heterogeneous logical model, including: if the current access pattern is a sequential access pattern, then a standard logical model corresponding to a timing-dependent access pattern is selected as the target standard logical model; if the current access pattern is a random access pattern, then a standard logical model corresponding to a statistical feature-based access pattern is selected as the target standard logical model.

[0097] This selection process relies on extracting behavioral features of the access sequence, such as determining whether the access address has a linear growth trend, whether the access interval is stable, and whether there are repetitive patterns or random jumps. Specifically, if the current memory access pattern exhibits obvious sequential access characteristics, such as memory addresses increasing in fixed increments (such as A, A+1, A+2,...), the system prioritizes the standard logical model of timing-dependent access patterns as the target model. This model excels at leveraging the relationship between temporal continuity and address progression, and by modeling the offset patterns in the access sequence, it performs highly accurate predictive prefetching.

[0098] In contrast, if the current memory access behavior exhibits a random access pattern, i.e., there is no obvious linear or periodic regularity between the access addresses, the system will preferentially select a standard logic model of the statistical feature type as the target model. This type of model focuses more on learning the probability distribution, frequently accessed address set or feature pattern in the historical data to adapt to irregular and jump-like access behavior, thereby maintaining the stability of the prefetch hit rate in a complex access environment. The selected target standard logic model will become the dominant module in the current heterogeneous model and be used to generate a new set of prefetch strategy candidates.

[0099] At the same time, to avoid the interference of the inadapted models, the strategy generation function of the other standard logic models in the heterogeneous logic model is temporarily disabled, and only the inference path of the target logic model is retained. This process not only simplifies the computational burden and improves processing efficiency, but also effectively avoids strategy conflicts between different models. The set of prefetch strategy candidates regenerated by the target standard logic model will better reflect the memory access prediction needs under the current access pattern, significantly improving the effectiveness and accuracy of prefetching.

[0100] In an exemplary embodiment, after selecting the target standard logic model that adapts to the current access pattern from the multiple standard logic models included in the heterogeneous logic model based on the characteristics of the current access pattern, the memory prefetch control method further comprises: dynamically adjusting the model parameters of the heterogeneous logic model based on the characteristics of the current access pattern to adapt to the current access pattern; the model parameters include input sensitivity parameters and historical decay parameters.

[0101] In this embodiment, to further improve the adaptability of the heterogeneous logic model under different memory access patterns, after the selection of the target standard logic model is completed, the key model parameters of the heterogeneous logic model will also be dynamically adjusted based on the behavior characteristics of the current access pattern. This adjustment operation aims to make the model more sensitive to local changes in the access sequence while retaining reasonable historical information to achieve more accurate strategy output.

[0102] The model parameters include but are not limited to input sensitivity parameters and historical decay parameters. Among them, the input sensitivity parameter is used to represent the influence weight of the current input sequence on the output of the prefetch strategy, and the larger the value, the more the model values the changes in the current access behavior; it is suitable for scenarios with frequent access changes, such as burst or irregular access patterns. The historical decay parameter is used to control the retention degree of the model to the past access information, and the smaller the value, the faster the historical information decays, and the model is more biased towards short-term memory; it is suitable for situations with weak sequentiality or unstable access characteristics.

[0103] Through the dynamic adjustment mechanism, the heterogeneous logic model can not only switch the logic structure to match the global characteristics of the access mode, but also realize soft adaptation according to the details of the access behavior at the model parameter level.

[0104] In an exemplary embodiment, based on the characteristics of the current access mode, the model parameters of the heterogeneous logic model are dynamically adjusted, including: if the current access mode presents periodic characteristics, the historical decay parameter is increased by a preset step; and if the current access mode presents burst characteristics, the input sensitivity parameter is increased by a preset step.

[0105] In this embodiment, not only the overall change of the access mode is dealt with by switching the logic model structure, but also a parameter level fine-tuning mechanism based on the characteristics of the access mode is introduced to realize fine-grained response to local behavior differences. When it is identified that the current memory access mode has certain periodic characteristics (for example, the access address has a stable cycle structure, the time interval is regular, etc.), it can be inferred that the historical behavior has strong predictive significance for future access, and therefore the historical decay parameter is gradually increased by a preset step to prolong the memory window of the model for past access records, thereby enhancing the capture ability of periodic behavior.

[0106] On the contrary, when it is detected that the current access mode has obvious burst characteristics (for example, the address access jumps sharply, and a new data area is accessed in a concentrated manner), the reference value of the historical mode to the current behavior is reduced at this time. In order to improve the response speed of the model to the new input sequence, the input sensitivity parameter is increased by a preset step, so that the model pays more attention to the latest access mode change and weakens the influence of past data. This parameter dynamic adjustment strategy based on the characteristics of the access mode enables the heterogeneous logic model to not only remember valuable periodic information, but also quickly learn new burst behavior, and balances stability and flexibility, thereby improving the overall prefetching effect and adaptability.

[0107] For example, the linear function adjustment formula is: The dynamic adjustment rule is: periodic access: increase q (historical decay parameter) (such as from 0.6 to 0.8) to enhance the memory of the historical state; and burst access: increase p (input sensitivity parameter) (such as from 0.5 to 0.7) to improve the response speed to new inputs. For example, when it is detected that the access presents periodicity (such as repeating A→B→C every 100 steps), q is automatically increased to 0.8 to strengthen the capture of the cycle mode; and if a large number of random accesses burst, p is increased to 0.7 to quickly learn new address relationships.

[0108] In a specific embodiment, the video stream processing program is initially set to sequentially read frame data (mode 1), and is then switched to randomly jump frames and clip (mode 2).

[0109] Pattern 1 (Sequential Access): Using AIG model, strategy is "prefetch next 3 frames"; parameters: .

[0110] Monitor pattern switch: Calculate , determine as random access; trigger logic reconstruction, switch to XMG model.

[0111] Pattern 2 (Random Access): Generate statistical strategy "prefetch adjacent 2 frames with highest frequency among last 10 frames"; dynamically adjust parameters: (decrease history dependence, increase immediate response).

[0112] Result: prefetch hit rate increases from 70% in pattern 1 to 85% in pattern 2.

[0113] Abnormality detection: if strategy hit rate is below 40% for 5 consecutive times, or delay cost exceeds 2 times of historical average, determine as abnormal prefetch strategy. Fall back to conservative strategy, enable prefetch depth = 1 (only prefetch next address), reduce resource occupation; incremental learning, collect data during abnormal period, update model parameters after offline training; alarm mechanism, notify system administrator to check hardware or software abnormality. For example, sudden memory bus conflict leads to dramatic increase of prefetch delay, system switches to conservative strategy while recording conflict period data for later analysis.

[0114] Through modular DFR model, dynamically adjust non-linear function parameters. For example, if current access presents periodicity, system increases feedback coefficient q to capture cyclic regularity; if access is highly bursty, increase input scaling factor p to accelerate response. This dynamic adaptation ensures that the prefetch strategy always fits the actual scenario. Such dual adaptive mechanism significantly improves the robustness and effectiveness of memory prefetch strategy in diversified program scenarios.

[0115] Through the above description of the embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be realized by means of software and the necessary general hardware platform, of course, it can also be realized by hardware, but in many cases the former is a better embodiment.

[0116] As Figure 2Embodiments of the present application also provide a memory prefetch control device, comprising: a heterogeneous modeling module 21 configured to construct a heterogeneous logic model based on a plurality of standard logic models, each of the standard logic models corresponding to a different memory access pattern; a policy generation module 22 configured to input a current memory access sequence into the heterogeneous logic model to generate a prefetch policy candidate set comprising a plurality of prefetch policies; a cost evaluation module 23 configured to calculate a corresponding prefetch cost for each of the prefetch policies in the prefetch policy candidate set, and sort and filter the prefetch costs to determine a target prefetch policy; and a prefetch execution module 24 configured to perform a corresponding memory prefetch operation from a target address set based on the target prefetch policy.

[0117] In an exemplary embodiment, the cost evaluation module 23 comprises: a cost decomposition submodule configured to calculate a delay cost and a hit rate gain for each of the prefetch policies in the prefetch policy candidate set; the delay cost represents a time length of occupying a memory bus when the prefetch policy is executed, and the hit rate gain represents a proportion of the prefetch data corresponding to the prefetch policy that is actually accessed; and a weighted cost calculation submodule configured to calculate a corresponding prefetch cost based on the delay cost and the hit rate gain.

[0118] In an exemplary embodiment, the weighted cost calculation submodule is specifically configured to, for each of the prefetch policies, obtain a first weight corresponding to the delay cost and a second weight corresponding to the hit rate gain; and calculate a corresponding prefetch cost based on the delay cost, the first weight, the hit rate gain, and the second weight.

[0119] In an exemplary embodiment, the device further comprises a dynamic weight adjustment module configured to monitor a bandwidth utilization rate and a cache hit rate of the memory in real time; and adjust the first weight according to the bandwidth utilization rate and adjust the second weight according to the cache hit rate.

[0120] In an exemplary embodiment, the dynamic weight adjustment module is specifically configured to monitor a bandwidth utilization rate and a cache hit rate of the memory in real time; and when the bandwidth utilization rate is greater than a first preset threshold, adjust the first weight to increase an influence of the delay cost; and adjust the second weight according to the cache hit rate, including: when the cache hit rate is less than a second preset threshold, adjust the second weight to increase an influence of the hit rate gain.

[0121] In an exemplary embodiment, the device further comprises an abnormal policy elimination module configured to detect a delay cost and a hit rate gain of each of the prefetch policies; mark a prefetch policy corresponding to the delay cost exceeding a first standard range or the hit rate gain exceeding a second standard range as an abnormal prefetch policy; and eliminate the abnormal prefetch policy from the prefetch policy candidate set.

[0122] In an example embodiment, the adaptive training module further comprises: a loss function construction submodule configured to construct a loss function according to the predicted hit probability and the actual hit probability; a truncated back propagation submodule configured to perform back propagation within a preset truncated window; and a parameter updating submodule configured to update the model parameters of the heterogeneous logic model according to the back gradient and the learning rate, wherein the model parameters include the input sensitivity parameter and the history decay parameter.

[0123] In an example embodiment, the memory access pattern detection module is further configured to: calculate a difference degree between a current memory access sequence and a previous memory access sequence; determine whether a change occurs in the current access pattern compared with the previous access pattern based on the difference degree; and the logic switching module is further configured to trigger a logic switching mechanism of the heterogeneous logic model to switch to a logic model corresponding to the current access pattern if the change occurs.

[0124] In an example embodiment, the logic switching module comprises: a model selection submodule configured to select a target standard logic model adapted to the current access pattern from a plurality of standard logic models included in the heterogeneous logic model based on a feature of the current access pattern; a model start-stop submodule configured to disable a policy generation function of other standard logic models in the heterogeneous logic model that are not adapted to the current access pattern; and the model start-stop submodule is further configured to regenerate the prefetch policy candidate set based on the target standard logic model.

[0125] In an example embodiment, the parameter adaptive adjustment module is configured to dynamically adjust the model parameters of the heterogeneous logic model based on a feature of the current access pattern to adapt to the current access pattern, wherein the model parameters include the input sensitivity parameter and the history decay parameter.

[0126] In an example embodiment, if the current memory access pattern presents a periodic feature, the history decay parameter is increased by a preset step; and if the current memory access pattern presents a burst feature, the input sensitivity parameter is increased by a preset step.

[0127] For other introductions of the memory prefetch control device, please refer to the above embodiments, which will not be repeated here.

[0128] As Figure 3 Embodiments of the present application further provide an electronic device comprising a memory 101 and a processor 102, wherein the memory 101 stores a computer program, and the processor 102 is configured to run the computer program to perform the steps in any of the above memory prefetch control method embodiments.

[0129] As Figure 4The embodiments of the present application further provide a computer readable storage medium 201, which stores a computer program 202. The computer program 202 is configured to execute the steps in any of the memory prefetching control method embodiments when running.

[0130] In an example embodiment, the computer readable storage medium 201 can include, but is not limited to, a U disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store the computer program 202.

[0131] The embodiments of the present application further provide a computer program product, which includes a computer program. The computer program is executed by a processor to implement the steps in any of the memory prefetching control method embodiments.

[0132] The embodiments of the present application further provide another computer program product, which includes a non-volatile computer readable storage medium. The non-volatile computer readable storage medium stores a computer program. The computer program is executed by a processor to implement the steps in any of the memory prefetching control method embodiments.

[0133] The skilled in the art can further realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be realized in electronic hardware, computer software or a combination of both. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of the examples have been described in general terms in the above description. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. The skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0134] The above provides a memory prefetching control method, device, storage medium and program product. The principles and implementation modes of the present application are described by applying specific examples. The above example is only used to help understand the method and its core idea. It should be pointed out that for those skilled in the art, without departing from the principles of the present application, some improvements and modifications can be made to the present application. These improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A memory prefetch control method, characterized in that: include: Building a heterogeneous logical model based on multiple standard logical models, where the multiple standard logical models correspond to different access modes; Inputting the current memory access sequence into the heterogeneous logic model to generate a prefetch strategy candidate set, wherein the prefetch strategy candidate set includes multiple prefetch strategies; For each of the prefetch strategies in the prefetch strategy candidate set, calculating a corresponding delay cost and a hit rate gain; the delay cost represents the length of time the memory bus is occupied by executing the prefetch strategy, and the hit rate gain represents the proportion of prefetched data corresponding to the prefetch strategy that is actually accessed; For each of the prefetch strategies, obtaining a first weight corresponding to the delay cost and a second weight corresponding to the hit rate gain; Calculating a corresponding prefetch cost based on the delay cost, the first weight, the hit rate gain, and the second weight; Sorting and screening the prefetching costs to determine a target prefetching strategy; Based on the target prefetch strategy, a corresponding memory prefetch operation is performed from the target address set.

2. The memory prefetch control method according to claim 1, wherein: Also includes: Real-time monitoring of memory bandwidth utilization and cache hit rate; adjusting the first weight according to the bandwidth utilization; The second weight is adjusted according to the cache hit rate.

3. The memory prefetch control method according to claim 2, wherein: Adjusting the first weight according to the bandwidth utilization includes: When the bandwidth utilization is greater than a first preset threshold, adjusting the first weight to increase the impact of the delay cost; Adjusting the second weight according to the cache hit rate includes: When the cache hit rate is less than a second preset threshold, the second weight is adjusted to increase the influence of the hit rate gain.

4. The memory prefetch control method according to claim 1, wherein: After calculating the corresponding delay cost and hit rate gain for each of the prefetch strategies in the prefetch strategy candidate set, the memory prefetch control method further includes: Detecting the delay cost and hit rate gain of each prefetch strategy; Marking the prefetch strategy corresponding to the delay cost exceeding the first standard range or the hit rate gain exceeding the second standard range as an abnormal prefetch strategy; The abnormal prefetch strategy is eliminated from the prefetch strategy candidate set.

5. The memory prefetch control method according to claim 1, wherein: The memory prefetch control method further includes: For the prefetched data corresponding to each prefetch strategy, a loss function is constructed based on the predicted hit probability and the actual hit probability; Performing truncated back propagation on the memory access sequence based on the loss function, retaining reverse gradient information of a preset truncation window; the preset truncation window includes a preset number of steps; Based on the reverse gradient information and the preset learning rate, the model parameters of the heterogeneous logic model are optimized, where the model parameters include an input sensitivity parameter and a history decay parameter. The input sensitivity parameter represents the influence weight of the new memory access sequence on the prefetch strategy, and the history decay parameter represents the influence weight of the historical memory access sequence in the prefetch strategy update.

6. The memory prefetch control method according to claim 1, wherein: Also includes: Calculate the difference between the current memory access sequence and the previous memory access sequence; Determining whether the current access mode has changed compared to the previous access mode based on the difference; If a change occurs, the logic switching mechanism of the heterogeneous logical model is triggered to switch to the logical model corresponding to the current access mode.

7. The memory prefetch control method according to claim 6, wherein: Triggering a logic switching mechanism of the heterogeneous logical model to switch to a logical model corresponding to the current access mode includes: Based on the characteristics of the current access pattern, selecting a target standard logical model adapted to the current access pattern from a plurality of standard logical models included in the heterogeneous logical model; Deactivate a policy generation function of other standard logical models in the heterogeneous logical model that are not compatible with the current access mode; The prefetch strategy candidate set is regenerated based on the target standard logical model.

8. The memory prefetch control method according to claim 7, wherein: Selecting a target standard logical model adapted to the current access pattern from a plurality of standard logical models included in the heterogeneous logical model based on the characteristics of the current access pattern includes: If the current access mode is a sequential access mode, selecting a standard logic model corresponding to a timing-dependent access mode as a target standard logic model; If the current access mode is a random access mode, a standard logical model corresponding to the statistical characteristic access mode is selected as the target standard logical model.

9. The memory prefetch control method according to claim 7, wherein: After selecting a target standard logical model adapted to the current access pattern from a plurality of standard logical models included in the heterogeneous logical model based on the characteristics of the current access pattern, the memory prefetch control method further includes: Based on the characteristics of the current access mode, model parameters of the heterogeneous logic model are dynamically adjusted to adapt to the current access mode; the model parameters include input sensitivity parameters and historical attenuation parameters.

10. The memory prefetch control method according to claim 9, wherein: Dynamically adjusting model parameters of the heterogeneous logical model based on characteristics of the current access pattern includes: If the current access pattern exhibits periodic characteristics, increasing the historical attenuation parameter by a preset step; If the current access mode exhibits a sudden characteristic, the input sensitivity parameter is increased by a preset step.

11. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the steps of the memory prefetch control method according to any one of claims 1 to 10 when executing the computer program.

12. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the memory prefetch control method according to any one of claims 1 to 10.

13. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the memory prefetch control method according to any one of claims 1 to 10 are implemented.

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