A method for reducing logic simplification of FPGA synthesis tool operation units, storage medium and electronic equipment
By identifying and merging the input signals of the reduction and operation units, the logic is simplified and the reduction and type is reduced or type, which solves the problem of excessive logic resources in traditional tools and optimizes the area and performance of FPGA synthesis.
Patent Information
- Application Number
- CN202511045146.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-29
- Publication Date
- 2025-09-30
- Estimated Expiration
- 2045-07-29
AI Technical Summary
Traditional FPGA synthesis tools fail to effectively consider the logical relationships of reduced computing units, resulting in a large amount of logic resources after synthesis, affecting the area and performance of FPGA design.
Traverse the circuit netlist, identify and merge the input signals of the reduction and operation units, convert the reduction and type into the reduction or type through logic simplification, reduce the number of logic resources, and optimize the area of FPGA synthesis.
This reduces logic resources and improves the routing rate and timing performance of FPGA designs.
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Figure CN120542332B_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of FPGA synthesis tools, and in particular relates to a method for reducing the logic simplification of operation units of an FPGA synthesis tool, a storage medium and an electronic device. Background Art
[0002] Logic synthesis is a crucial step in the FPGA EDA software design process. It converts user-entered behavioral-level or register-transfer-level (RTL) Verilog / VHDL circuit files into a netlist consisting of basic FPGA logic elements, such as lookup tables (LUTs) and flip-flops (FFs). FPGA logic synthesis consists of two phases: synthesis and mapping. Synthesis converts the behavioral-level or RTL circuit file into a logic netlist consisting of gates; mapping maps the gate-based logic netlist into a netlist consisting of basic FPGA logic elements.
[0003] Area optimization (i.e., reducing resource usage) is one of the core goals of logic synthesis, directly impacting the routing success rate and timing performance of FPGA software designs. Reduced operation units, including reduce_and units, reduce_or units, and reduce_not units, are the fundamental logic units in FPGA synthesis netlists. The synthesized netlists of complex FPGA application circuits typically contain a large number of reduced operation units. However, traditional synthesis tools do not consider the logical relationships between these reduced operation units when simplifying them, resulting in a large number of logic resources after synthesis. Therefore, it is necessary to optimize existing synthesis tools to effectively simplify the logic of reduced operation units, thereby reducing the number of logic resources after synthesis and optimizing the area of FPGA synthesis. Summary of the Invention
[0004] The present invention provides a method for simplifying the logic of reduced operation units of an FPGA synthesis tool, which can effectively simplify the logic of the reduced operation units, reduce the number of logic resources after synthesis, and optimize the area of FPGA synthesis.
[0005] Other purposes and advantages of the present invention can be further understood from the technical features disclosed in the present invention.
[0006] In order to achieve one or part or all of the above purposes or other purposes, a technical solution of the present invention provides a method for simplifying the logic of an FPGA synthesis tool reduction operation unit, traversing each logic unit in a circuit netlist, obtaining a mapping set of logic unit output signals to logic units, a reduction and operation unit set, and a NOT gate unit input and output mapping set; traversing each reduction and operation unit c in the reduction and operation unit set, determining the input A-end signal sig_a of each reduction and operation unit c, searching the logic unit d from which the signal sig_a comes from the mapping set of the logic unit output signals to the logic units, and determining whether the type of the logic unit d is If it is a reduction or operation unit, the judgment result is no, then continue with the processing of the next reduction and operation unit c; if the judgment result is yes, then perform a logical simplification operation on the current reduction and operation unit c, including finding the reduction or operation unit a of each signal source of sig_a from the mapping set of the logic unit output signal to the logic unit, obtaining each input signal set S0 of the reduction or operation unit a, and inserting the input signal set S0 into the signal set S; finding the best combination of the two input signal sets S0 that can be merged from the signal set S, and merging the same signals for the best combination of the input signal sets S0 that can be merged.
[0007] If the merging is successful, continue to search for the next set of best merged signals to merge the same signals; otherwise find the common signal set of signals in all subsets from the set S, and convert the reduction and operation unit c from the reduction and type to the reduction or type.
[0008] Find the two best input signal sets S0 that can be merged from the signal set S, including traversing any 2-bit signal combination (ai, aj) of the signal sig_a; finding the input signal sets Si and Sj corresponding to the signals ai and aj respectively; calculating the simplification gain of the signal combination (ai, aj) based on the number of signals in the signal sets Si and Sj; calculating the simplification gain of the current signal combination (a1, a2), and when the calculated simplification gain of the current signal combination is greater than the current maximum gain, the input signal sets S1 and S2 corresponding to the current signal combination (a1, a2) are the best combinations for the current logical simplification; the current maximum gain refers to the maximum value of the simplification gain of the signal combination (ai, aj).
[0009] According to the number of signals in the signal sets Si and Sj, calculating the simplification gain of the signal combination (ai, aj) includes setting the initialization simplification gain of the signal combination (ai, aj) to 0; obtaining the common signal set of the input signals in the sets Si and Sj, and the remaining signal sets Si' and Sj' in the sets Si and Sj excluding the common signal set; if the set Si' is empty, the simplification gain of the signal combination (ai, aj) is twice the sum of the number of signals in the common signal set and the number of signals in the set Sj'; if the number of signals in the set Si' is 1 and the number of signals in the set Sj' is 1 , then determine from the NOT gate unit input-output mapping set whether the signals of set Si' and set Sj' are negated signals, and if the judgment result is yes, the simplification gain of the signal combination (ai, aj) is twice the number of signals in the common signal set plus 2; if the judgment result is no, if the number of signals in set Si' is 1 and the number of signals in set Sj' is greater than 1, then determine whether set Sj' contains the negated signal of the signal in set Si', and if the judgment result is yes, the simplification gain of the signal combination (ai, aj) is twice the number of signals in the common signal set plus 1.
[0010] If the number of signals in set Si' is greater than the number of signals in set Sj', then sets Si' and Sj' are swapped.
[0011] When the simplified gain of the current signal combination (a1, a2) is greater than the current maximum gain, the current maximum gain is the simplified gain of the signal (a1, a2).
[0012] Merge the same signals for the best combination of the mergeable input signal set S0, including finding the common signal set of the input signal sets S1 and S2 corresponding to the current signal combination (a1, a2) and the remaining signal sets S1' and S2' of the signal sets S1 and S2 excluding the common signal set; if the set S1' is empty, clear the set S2', delete the a2-th input signal in sig_a, and return true; if the number of signals in the set S1' is 1 and the number of signals in the set S2' is 1, determine the signal sets S1' and S2' from the NOT gate unit input-output mapping set. Check whether the signal is a negated signal. If the result is yes, set S1 = public signal set, clear set S2, delete the a2th input signal in sig_a, and return true; if the result is no, return false; if the number of signals in set S1' is 1 and the number of signals in set S2' is greater than 1, determine whether set S2' contains the negated signal of the signal in set S1', otherwise return false; if set S2' contains the negated signal of the signal in set S1', delete the negated signal of the signal in set S1' from set S2, otherwise return false.
[0013] Find the common signal set of the signals in all subsets from the set S, and convert the reduction and operation unit c from the reduction and type to the reduction or type, including finding the common items of the signals in all subsets from the set S. If the common items of the signals in the subset are empty, then exit this process; if the common items of the signals in the subset are not empty, then remove the common items of the signals in the subset from the set S; and create a new signal new_a, insert the common items of the signals in the subset into the signal new_a; update each input of sig_a according to the signal in each subset in the set S. The input signal of the reduction or operation unit a of the signal source; a new reduction and operation unit new_and is created, and the output signal of the reduction or operation unit a of each input signal source of sig_a is inserted into the input signal of new_and, and the output signal of new_and is inserted into the signal new_a; a new reduction or operation unit new_or is created, and the signal new_a is used as the input signal of the reduction or operation unit new_or; a connection is added to the current netlist from the output signal of the reduction and operation unit c to the output signal of the reduction or operation unit new_or.
[0014] Another technical solution of the present invention provides a storage medium, wherein the storage medium stores program code, and the program code is called by a processor to execute the method for reducing the logic simplification of an FPGA synthesis tool operation unit as described above.
[0015] Another technical solution of the present invention provides an electronic device, comprising one or more processors; a memory; and one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute a method for reducing logic simplification of an FPGA synthesis tool operation unit as described above.
[0016] Compared with the prior art, the beneficial effects of the present invention mainly include: the method of simplification of logic of reduced operation units in the FPGA synthesis tool of the present invention can quickly and effectively simplify the logic of the reduced operation units in the circuit netlist, simplifying the roadbed of the reduced operation units, helping to reduce the number of resources after synthesis, reducing the area of FPGA synthesis, and improving the routing rate and timing performance of FPGA software design.
[0017] In order to make the above and other objects, features and advantages of the present invention more clearly understood, preferred embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0019] Figure 1 The present invention provides a flow chart of a method for reducing logic simplification of an FPGA synthesis tool.
[0020] Figure 2 Schematic diagram of a flow chart of a method for finding an optimal combination of input signals according to the present invention.
[0021] Figure 3 FIG. 4 is a flow chart of a method for merging identical input signals according to the present invention.
[0022] Figure 4 It is a flowchart of converting a reduced and type logical unit into a reduced or type logical unit according to the present invention. DETAILED DESCRIPTION
[0023] The foregoing and other technical aspects, features, and functions of the present invention are clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. Directional terms such as up, down, left, right, front, and back, used in the following embodiments, are intended solely to refer to the directions in the accompanying drawings. Therefore, the directional terms used are for illustrative purposes only and are not intended to limit the present invention.
[0024] Example 1
[0025] Embodiment 1 provides a method for reducing and simplifying the logic of an FPGA synthesis tool reduction operation unit, traversing each logic unit in a circuit netlist, obtaining a mapping set of logic unit output signals to logic units, a reduction and operation unit set, and a NOT gate unit input and output mapping set; traversing each reduction and operation unit c in the reduction and operation unit set, determining the input A-end signal sig_a of each reduction and operation unit c, searching the mapping set of the logic unit output signals to the logic units for the logic unit d from which the signal sig_a originates, and determining whether the type of the logic unit d is a reduction or operation unit, and determining the result. If the answer is no, continue processing the next reduction and operation unit c; if the judgment result is yes, perform a logical simplification operation on the current reduction and operation unit c, including finding the reduction or operation unit a of each signal source of sig_a from the mapping set of the logic unit output signal to the logic unit, obtaining each input signal set S0 of the reduction or operation unit a, and inserting the input signal set S0 into the signal set S; finding the best combination of the two input signal sets S0 that can be merged from the signal set S, and merging the same signals for the best combination of the input signal sets S0 that can be merged.
[0026] If the merging of identical signals succeeds, continue searching for the next set of optimal merged signals in set S to merge identical signals; if the merging of identical signals fails, find the common signal set of signals in all subsets within set S, and convert the reduction and operation unit c from reduction and type to reduction or type.
[0027] The following is a detailed explanation of a method for reducing logic simplification of an FPGA synthesis tool for operation units according to the first embodiment of the present invention with reference to the accompanying drawings.
[0028] like Figure 1 As shown, a method for reducing logic simplification of an FPGA synthesis tool of the present invention comprises the following steps:
[0029] Step S1: traverse each logic cell in the circuit netlist to obtain the mapping set out2cell from output signals to logic cells, the reduction and operation unit set ands, and the mapping set not2y from input signals to output signals of NOT gate units.
[0030] Step S2: traverse each reduction and operation unit c in the set ands and execute steps S3-S8.
[0031] Step S3: Determine whether reduction and operation unit c meets the requirements for logical simplification of reduction and operation units. Obtain signal sig_a at input A of reduction and operation unit c. Find the logic unit d from the set out2cell that represents each bit of signal sig_a. Determine whether logic unit d is a reduction or operation unit. If not, it does not meet the requirements for logical simplification of reduction and operation units. The logic simplification process for reduction and operation unit c is terminated, and processing for the next reduction and operation unit c in ands is started.
[0032] Step S4: If the type of logic unit d is a reduction or operation unit type, find the reduction or operation unit a of each bit signal source of signal sig_a from the set out2cell, obtain the set S0 of each bit input signal of the reduction or operation unit a, and insert the signal set S0 into the set S.
[0033] Step S5: Find the best combination (S1, S2) of the input signal set S0 that can be merged from the set S, where S1 and S2 represent two subsets in the set S, respectively representing the reduction of the two-bit input signal sources (a1, a2) in the signal sig_a or the input signal set of the logic unit a.
[0034] Step S6: For the signals in sets S1 and S2, merge the same signals.
[0035] Step S7: If the signals of sets S1 and S2 are successfully merged, go to step S5 and continue to search for the next best merged signal in set S to merge the same signals; otherwise, go to step S8.
[0036] Step S8: Find the common items of the signals in all subsets from the set S, and convert the reduction and operation unit c from the reduction and type to the reduction or type.
[0037] Step 5 of Example 1 is to find two optimal input signal sets S0 that can be merged from the signal set S, including traversing any 2-bit signal combination (ai, aj) of the signal sig_a; finding the input signal sets Si and Sj corresponding to the signals ai and aj respectively; calculating the simplification gain of the signal combination (ai, aj) based on the number of signals in the signal sets Si and Sj; calculating the simplification gain of the current signal combination (a1, a2), and when the calculated simplification gain of the current signal combination is greater than the current maximum gain, the input signal sets S1 and S2 corresponding to the current signal combination (a1, a2) are the optimal combinations for the current logical simplification, and the current maximum gain refers to the maximum value of the simplification gain of the signal combination (ai, aj).
[0038] See also Figure 2 , which includes the following specific steps:
[0039] Step S5-1: Traverse any 2-bit signal combination (ai, aj) in the sig_a signal and execute steps S5-2 to S5-11.
[0040] Step S5-2: Set the initialization simplified gain score of the combination (ai, aj) to 0.
[0041] Step S5-3: Find the input signal sets Si, Sj corresponding to the signals ai, aj respectively.
[0042] Step S5 - 4 : Obtain the common signal set Sa of the input signals in the set Si and the set Sj, and the remaining signal sets Si′ and Sj′ in the sets Si and Sj.
[0043] Step S5-5: If the number of signals in Si' is greater than the number of signals in Sj', then swap sets Si' and Sj'.
[0044] Step S5-6: If the set Si' is empty, the simplification gain score of the combination (ai, aj) = (the number of signals in the common signal set Sa + the number of signals in the set Sj') × 2, and go to step S5-11 to calculate the simplification gain of the current combination (a1, a2); otherwise, go to step S5-7.
[0045] Step S5-7: If the number of signals in Si'=1 and the number of signals in Sj'=1, determine from the set not2y whether the signals in Si' and Sj' are negated signals. If the judgment result is yes, execute step S5-8; otherwise, execute step S5-9.
[0046] Step S5-8: The simplification gain score of the signal combination (ai, aj) = (the number of signals in the public signal set Sa) × 2 + 2, and then proceed to step S5-11 to calculate the simplification gain of the current combination (a1, a2).
[0047] Step S5-9: If the number of signals in Si'=1 and the number of signals in Sj'>1, execute step 5-10; otherwise, execute step 5-11 to calculate the simplified gain of the current combination (a1, a2).
[0048] Step S5-10: Determine whether Sj' contains the inverted signal of the signal in Si'. If so, the simplified gain score of the combination (ai, aj) = (the number of signals in the common signal set Sa) × 2 + 1.
[0049] Step S5-11: If the simplification gain score calculated for the current combination (a1, a2) is greater than the current maximum gain max, then the current maximum gain max=score, and the combination (a1, a2) is the optimal combination for the current logic simplification.
[0050] In the first embodiment, step 6 is to merge the same input signals of the set S1 and the set S2. Figure 3 , specifically including the following steps:
[0051] S6-1: Find the common signal set Sa of the input signals in the sets S1 and S2, and the remaining signal sets S1' and S2' in the sets S1 and S2 after removing the common signal set Sa.
[0052] S6-2: If the set S1' is empty, clear the set S2, delete the input signal at the a2th bit in sig_a, and return true; otherwise, execute step S6-3.
[0053] S6-3: If the number of signals in set S1'=1 and the number of signals in set S2'=1, execute step S6-4; otherwise, execute step S6-5.
[0054] S6-4: Determine from the set not2y whether the signals in the sets S1' and S2' are inverted signals. If so, set S1 = the common signal set Sa, clear set S2, and delete the input signal at the a2th bit in sig_a, and return true (indicating that the signal merge is successful); otherwise, return false (indicating that the signal merge fails).
[0055] S6-5: If the number of signals in set S1' = 1 and the number of signals in set S2' > 1, execute step S6-6; otherwise return false.
[0056] S6-6: Determine whether the inverted signal of the signal in S1' exists in S2'. If so, delete the inverted signal of the signal in S1' from the set S2; otherwise, return false.
[0057] In the first embodiment, step S8 is to find the common items of the signals in all subsets from the set S, and the reduction and logic unit c is converted from the reduction and type to the reduction or type, see Figure 4 , specifically including the following steps:
[0058] S8-1: Find the common item Sa1 of the signals in all subsets from S.
[0059] S8-2: If the set of public items Sa1 is empty, exit the processing of this process; otherwise, execute step S8-3.
[0060] S8-3: Remove the common signal in the common item Sa1 from all sub-sets in the set S.
[0061] S8-4: Create a new signal new_a and insert all signals in the public item Sa1 into new_a.
[0062] S8-5: Update the input signal of the reduction or operation unit a of each bit input signal source of sig_a according to the signal in each subset of the set S.
[0063] S8-6: Create a new reduction and operation unit new_and, and insert the output signal of the reduction or operation unit a of each input signal source of sig_a into the input signal of the unit new_and.
[0064] S8-7: Insert the output signal of the unit new_and into the signal new_a.
[0065] S8-8: Create a new reduction OR operation unit new_or, and use the signal new_a as the input signal of the unit new_or.
[0066] S8-9: Add a connection from the output signal of the reduction and operation unit c to the output signal of the unit new_or in the current netlist.
[0067] Example 2
[0068] The second embodiment provides a storage medium in which program code is stored. The stored program code is called by a processor to execute the steps of the method for reducing logic simplification of an FPGA synthesis tool and an arithmetic unit described in the first embodiment.
[0069] Example 3
[0070] Embodiment 3 provides an electronic device, which includes one or more processors; a memory; and one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute the steps of the method for reducing the logic simplification of an FPGA synthesis tool operating unit described in embodiment 1.
[0071] The above describes in detail the method, storage medium, and electronic device for reducing logic simplification of arithmetic units in an FPGA synthesis tool provided by the present invention. This article uses specific examples to illustrate the structure and operating principles of the present invention. The description of the above embodiments is intended only to facilitate understanding of the method and core concept of the present invention. It should be noted that those skilled in the art may make various improvements and modifications to the present invention without departing from the principles of the present invention, and such improvements and modifications also fall within the scope of protection of the claims of the present invention.
Claims
1. A method for reducing logic simplification of an arithmetic unit using an FPGA synthesis tool, characterized in that: Traverse each logic unit in the circuit netlist to obtain a mapping set of logic unit output signals to logic units, a reduction and operation unit set, and a NOT gate unit input and output mapping set; Traversing each reduction and operation unit c in the reduction and operation unit set, determining the input A-end signal sig_a of each reduction and operation unit c, searching the mapping set of logic unit output signals to logic units for the logic unit d that is the source of the signal sig_a, and determining whether the type of the logic unit d is a reduction or operation unit. If the determination result is no, continuing the processing to the next reduction and operation unit c; If the judgment result is yes, a logic simplification operation is performed on the current reduction and operation unit c, including finding the reduction or operation unit a corresponding to each signal source of sig_a from the mapping set of logic unit output signals to logic units, obtaining each input signal set S0 of the reduction or operation unit a, and inserting the input signal set S0 into the signal set S; Finding an optimal combination of two input signal sets S0 that can be merged from the signal set S, including traversing any 2-bit signal combination (ai, aj) of the signal sig_a; finding input signal sets Si and Sj corresponding to the signals ai and aj, respectively; calculating a simplification gain of the signal combination (ai, aj) based on the number of signals in the signal sets Si and Sj; calculating a simplification gain of the current signal combination (a1, a2), and when the calculated simplification gain of the current signal combination is greater than a current maximum gain, the input signal sets S1 and S2 corresponding to the current signal combination (a1, a2) are the optimal combination for current logical simplification; the current maximum gain refers to the maximum value of the simplification gain of the signal combination (ai, aj); And the same signals are merged for the best combination of the mergeable input signal set S0.
2. The method for reducing logic simplification of an FPGA synthesis tool according to claim 1, wherein: If the merger is successful, continue to search for the next set of best merged signals in the set S to merge the same signals; Otherwise, a common signal set of signals in all subsets is found from the set S, and the reduction and operation unit c is converted from a reduction and operation type to a reduction or operation type.
3. The method for reducing logic simplification of an FPGA synthesis tool according to claim 1, wherein: Calculating the simplified gain of the signal combination (ai, aj) according to the number of signals in the signal sets Si and Sj includes setting the initial simplified gain of the signal combination (ai, aj) to 0; Obtain the common signal set of the input signals in the sets Si and Sj, and the remaining signal sets Si' and Sj' excluding the common signal set in the sets Si and Sj; If the set Si' is empty, the simplification gain of the signal combination (ai, aj) is twice the sum of the number of signals in the common signal set and the number of signals in the set Sj'; If the number of signals in set Si' is 1 and the number of signals in set Sj' is 1, then determine from the NOT gate unit input-output mapping set whether the signals in set Si' and set Sj' are negated signals, and if the judgment result is yes, the simplification gain of the signal combination (ai, aj) is twice the number of signals in the common signal set plus 2; If the judgment result is no, if the number of signals in set Si' is 1 and the number of signals in set Sj' is greater than 1, then determine whether set Sj' contains the inverted signal of the signal in set Si'. If the judgment result is yes, then the simplified gain of the signal combination (ai, aj) is twice the number of signals in the common signal set plus 1.
4. The method for reducing logic simplification of an FPGA synthesis tool according to claim 3, wherein: If the number of signals in set Si' is greater than the number of signals in set Sj', then sets Si' and Sj' are swapped.
5. The method for reducing logic simplification of an FPGA synthesis tool according to claim 1, wherein: When the simplified gain of the current signal combination (a1, a2) is greater than the current maximum gain, the current maximum gain is the simplified gain of the signal (a1, a2).
6. The method for reducing logic simplification of an FPGA synthesis tool according to claim 1, wherein: Merging the same signals for the best combination of the mergeable input signal set S0, including finding the common signal set of the input signal sets S1 and S2 corresponding to the current signal combination (a1, a2) and the remaining signal sets S1' and S2' of the signal sets S1 and S2 excluding the common signal set; If the set S1' is empty, clear the set S2', delete the a2th input signal in sig_a, and return true; If the number of signals in set S1' is 1 and the number of signals in set S2' is 1, then determine from the NOT gate unit input-output mapping set whether the signals in set S1' and set S2' are negated signals. If the judgment result is yes, set S1 = common signal set, clear set S2, delete the a2th input signal of sig_a, and return true; if the judgment result is no, return false; If the number of signals in set S1' is 1 and the number of signals in set S2' is greater than 1, then determine whether there is a negated signal of the signal in set S1' in set S2', otherwise return false; If the negated signal of the signal in set S1' exists in set S2', the negated signal of the signal in set S1' is deleted from set S2; otherwise, false is returned.
7. The method for reducing logic simplification of an FPGA synthesis tool according to claim 2, wherein: Finding a common signal set of signals in all subsets from the set S, and converting the reduction and operation unit c from a reduction and type to a reduction or type, including finding a common item of signals in all subsets from the set S, and exiting the process if the common item of signals in the subsets is empty; If the common item of the signals in the subset is not empty, removing the common item of the signals in the subset from the set S; A new signal new_a is created, and the common items of the signals in the subset are inserted into the signal new_a; Update the input signal of the reduction or operation unit a of each bit input signal source of sig_a according to the signal in each subset of the set S; Create a new reduction and operation unit new_and, insert the output signal of the reduction or operation unit a of each input signal source of sig_a into the input signal of new_and, and insert the output signal of new_and into the signal new_a; Create a new reduction or operation unit new_or, and use the signal new_a as the input signal of the reduction or operation unit new_or; A connection is added in the current netlist from the output signal of the reduction and operation unit c to the output signal of the reduction or operation unit new_or.
8. A storage medium, characterized in that: The storage medium stores program code, and the program code is called by a processor to execute the method for reducing logic simplification of an FPGA synthesis tool operation unit according to any one of claims 1 to 7.
9. An electronic device, characterized in that: including one or more processors; Memory; One or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute the method for reducing logic simplification of an FPGA synthesis tool operation unit as described in any one of claims 1 to 7.