Design method and system of delay-free proportional resonator

Abstract

This invention provides a design method and system for a delay-free proportional resonator. The method includes: step S101, establishing an association formula; step S102, constructing a tuning formula; step S103, constructing a delay compensator, determining the inner loop gain of the delay compensator based on the closed-loop transfer function of the mid-frequency system, and calculating the compensation gain based on the inner loop gain; step S104, defining a variable, calculating the product of this variable, the inner loop gain, and the compensation gain, and determining whether the product is less than a first threshold; step S105, if less than the first threshold, the tuning ends; step S106, if greater than or equal to the first threshold, adjusting the cutoff frequency according to a preset strategy, and returning to step S101. This invention can effectively improve the control accuracy of the inverter system and improve power quality.

Description

Technical Field

[0001] This invention relates to the field of resonator design technology, and in particular to a design method and system for a delay-free proportional resonator. Background Technology

[0002] In distributed generation systems, high-performance current controllers play a crucial role in sophisticated power electronic converters. They not only determine the control efficiency of power exchange between the converter and the main grid but are also a key component in solving power quality problems and handling fault ride-through. Proportional resonant (PR) controllers can directly track sinusoidal reference signals in a stationary coordinate system. Their high resonant gain at the fundamental frequency and high-frequency harmonic suppression capabilities enable them to simultaneously achieve low steady-state error and low total harmonic distortion (THD), making them widely used in distributed generation, motor drives, uninterruptible power supplies (UPS), and active power filters.

[0003] PR controller parameter tuning aims to achieve desired performance. Control systems are often designed in the continuous domain and then transformed into difference equations for practical applications using discretization methods. However, digital implementation introduces frequency offsets, and CNC systems inevitably introduce control delays, which degrade the system's desired performance. Addressing CNC delays while reducing design complexity and avoiding frequency aliasing, and clearly defining the performance indicators of the control system, are urgent problems to be solved. Summary of the Invention

[0004] The purpose of this invention is to provide a design method and system for a delay-free proportional resonator, which aims to solve the problems of limited phase margin and tracking error deviation caused by single-step calculation delay in traditional digital control technology.

[0005] In a first aspect, the present invention provides a design method for a delay-free proportional resonator, the method comprising:

[0006] Step S101: Based on the system phase angle condition and Taylor expansion, establish the relationship between the attenuation factor, phase margin, and cutoff frequency:

[0007] ;

[0008] Step S102: Calculate the zero-point parameters of the controller based on the attenuation factor, and construct the tuning relationship between the zero-point parameters and the controller gain coefficient based on the system amplitude conditions:

[0009] ;

[0010] in, As the attenuation factor, For phase margin, Where T is the cutoff frequency, and T is the sampling frequency. The fundamental frequency, This is the gain coefficient. Zero-point parameter;

[0011] Step S103: Construct a delay compensator, determine the compensation inner loop gain h of the delay compensator according to the closed loop transfer function of the mid-frequency system, and calculate the compensation gain H according to the compensation inner loop gain h;

[0012] Step S104: Define a variable A, calculate the product of variable A, the compensation inner loop gain h, and the compensation gain H, and determine whether the product is less than a first threshold.

[0013] Step S105: If the product is less than the first threshold, the tuning ends;

[0014] Step S106: If the product is greater than or equal to the first threshold, adjust the cutoff frequency according to the preset strategy and return to step S101.

[0015] In summary, based on the aforementioned design method for a delay-free proportional resonator, firstly, optimizing the tuning formula using Taylor expansion significantly improves the tuning accuracy of the phase margin and cutoff frequency. Secondly, by cascading a delay compensation term in the original controller, the convergence process of the sinusoidal reference tracking error is made nearly identical to the ideal case without delay. Compared to the original controller, the delay-free digital proportional resonator proposed in this invention can overcome the phase margin limitation caused by digital control delay, ensuring that the tracking error convergence trajectory highly matches the theoretical expectation, effectively improving the control accuracy of the inverter system and enhancing power quality.

[0016] Secondly, the present invention provides a delay-free proportional resonator design system, the system comprising:

[0017] The first relational construction module is used in step S101 to establish the correlation between the attenuation factor, phase margin, and cutoff frequency based on the system phase angle condition and Taylor expansion.

[0018] ;

[0019] The second relational construction module is used in step S102 to calculate the zero-point parameters of the controller based on the attenuation factor, and to construct the relationship between the zero-point parameters and the gain coefficient of the controller based on the system amplitude conditions:

[0020] ;

[0021] in, As the attenuation factor, For phase margin, Where T is the cutoff frequency, and T is the sampling frequency. The fundamental frequency, This is the gain coefficient. Zero-point parameter;

[0022] The compensation gain calculation module is used in step S103 to construct a delay compensator, determine the compensation inner loop gain h of the delay compensator according to the closed loop transfer function of the mid-frequency system, and calculate the compensation gain H according to the compensation inner loop gain h.

[0023] The detection module is used in step S104 to define a variable A, calculate the product of variable A, the compensation inner loop gain h, and the compensation gain H, and determine whether the product is less than a first threshold.

[0024] The first result output module is used in step S105: if the product is less than the first threshold, the tuning ends.

[0025] The second result output module is used in step S106. If the product is greater than or equal to the first threshold, the cutoff frequency is adjusted according to the preset strategy, and the process returns to step S101.

[0026] Thirdly, the present invention provides a storage medium that stores one or more programs, which, when executed by a processor, implement the above-described design method for a delay-free proportional resonator.

[0027] Fourthly, the present invention provides an electronic device, the electronic device comprising a memory and a processor, wherein:

[0028] The memory is used to store computer programs;

[0029] When the processor is used to execute the computer program stored in the memory, it implements the above-described design method for a delay-free proportional resonator. Attached Figure Description

[0030] Figure 1 This is a flowchart of a design method for a delay-free proportional resonator according to an embodiment of the present invention;

[0031] Figure 2 A schematic diagram of the generalized control structure of a power electronic converter;

[0032] Figure 3 This is the control block diagram of the inverter;

[0033] Figure 4 The unit impulse response curve of E(z);

[0034] Figure 5 Pole-zero distribution diagram of the open-loop system;

[0035] Figure 6 This is a schematic diagram of a control scheme for a delay-free proportional resonator, where... Figure 6 (a) is the control block diagram of the delay-free proportional resonator. Figure 6 (b) is the equivalent control block diagram of the mid-frequency band of the delay-free proportional resonator;

[0036] Figure 7 This is a schematic diagram of the design system of a delay-free proportional resonator proposed in an embodiment of the present invention.

[0037] The following detailed description, in conjunction with the accompanying drawings, will further illustrate the present invention. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art. The terms "comprising" and similar expressions used herein mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, but does not exclude other elements or objects.

[0039] like Figure 1 As shown, an embodiment of the present invention provides a design method for a delay-free proportional resonator, the method comprising:

[0040] Step S101: Based on the system phase angle condition and Taylor expansion, establish the correlation between the attenuation factor, phase margin, and cutoff frequency;

[0041] like Figure 2 and Figure 3 As shown, a single-phase inverter is first constructed. The inverter converts the DC-side voltage into a grid-connected current injected into the grid by controlling a single-phase H-bridge using pulse width modulation. The controlled object is composed of a series L-type output filter stage discrete by the pulse width modulation gain and the zero-order hold method. The grid voltage is obtained through a sampling module, and real-time phase information is obtained using phase-locked loop analysis. Then, the phase information and a given amplitude are used to generate a controller reference signal. The difference between the grid-connected current reference signal and the feedback signal is then calculated to define the tracking error. The tracking error is then sent to the input of a digital proportional resonator to calculate and generate the modulation signal for the next cycle. After a calculation delay of one cycle, the grid-connected current is generated through the controlled object.

[0042] In some embodiments, the expression of the controlled object is:

[0043] (1);

[0044] Sine reference signal Discretize it using the impulse invariance method:

[0045] (2);

[0046] from Starting from the expected exponential convergence, we need to construct... The expression is:

[0047] (3);

[0048] In the formula, For the exponentially decaying term, 'a' is defined as the decay factor and is a positive real number.

[0049] Substituting equations (2) and (3) into ,have to:

[0050] (4);

[0051] like Figure 4 As shown, the convergence speed of the time series E(z) varies with different values ​​of a. The larger the value of a, the faster the tracking error converges.

[0052] System structural constraints and From the summary, we can see that the controller satisfies:

[0053] (5);

[0054] in, Let z be the reference signal, and z be a discrete-domain complex variable. To track errors, For closed-loop transfer function For the error propagation function, For open-loop transfer functions, For controller, As the controlled object, For delay.

[0055] Therefore, the ideal structure of the controller is:

[0056] (6);

[0057] in, For output filter lumped inductance, For pulse width modulation gain, .

[0058] However, the controller using the structure of equation (6) is unusable. In some embodiments, the structure needs to be optimized as follows:

[0059] 1) Ignore The z-term in the numerator is used to ensure that the numerator and denominator of the controller are of the same order, thereby ensuring feasibility.

[0060] 2) In molecules Item replaced with Items, and recommended settings So that the open-loop system Type is This design ensures zero steady-state error.

[0061] 3) Introduce gain coefficient In order to preset the cutoff frequency The optimized controller structure is as follows:

[0062] (7);

[0063] Substitute the above optimized controller Figure 3 The open-loop transfer function of the system can be obtained, as shown in equation (8), and the zero-pole distribution of the open-loop system is as follows: Figure 5 As shown.

[0064] (8);

[0065] The system phase angle condition can be expressed as:

[0066] (9);

[0067] in, To ensure zero steady-state error, the controller zero point is set at the zero point. at cutoff frequency The phase angle generated at that point is expressed as ; Controller conjugate poles and The sum of phase angles is expressed as Delayed process Introduced poles The resulting phase angle is expressed as .

[0068] From the fundamental frequency angle Since the value is relatively small, the Taylor expansion can be used to approximate k:

[0069] (10);

[0070] From equations (9) and (10), the attenuation factor a and , relationship

[0071] (11).

[0072] Step S102: Calculate the zero-point parameters of the controller based on the attenuation factor, and construct the tuning relationship between the zero-point parameters and the gain coefficient of the controller based on the system amplitude conditions;

[0073] It should be noted that the open-loop system is in Gain satisfies We can obtain:

[0074] (12);

[0075] Simplifying the above equation yields the gain coefficient tuning formula:

[0076] (13);

[0077] in, As the attenuation factor, For phase margin, Where T is the cutoff frequency, and T is the sampling frequency. The fundamental frequency, This is the gain coefficient. Zero-point parameter;

[0078] In summary, regarding the parameter tuning formulas (11) and (13) above, it should be noted that traditional proportional resonators are designed and tuned in the continuous time domain, which usually requires digital implementation through discretization. However, the frequency selection offset, control delay, and tuning error associated with discretization will severely degrade the performance of the controller. Based on previous research on digital resonators, this invention simplifies the tuning formula using Taylor expansion and compensates for high-frequency approximation errors to ensure tuning accuracy. It derives an optimized control system performance tuning formula, reducing the phase margin tuning error, which characterizes the system's safety threshold, to 2.2%, and the cutoff frequency tuning error, which characterizes the system's frequency response capability, to 0.46%. This significantly reduces the controller's tuning error and ensures that the actual system meets the design expectations.

[0079] Furthermore, in some embodiments, the interrelationships between various indicators in the previously studied digital resonant controllers were not fully explored. For example, requiring a high phase margin under the premise of system stability would force the system convergence speed to be extremely low, causing the actual system to be unable to quickly track the command signal, and resulting in adverse phenomena such as hysteresis, overshoot, and oscillation in the control process. Based on this, the present invention starts from the critical zeros of the open-loop system, takes system stability as a prerequisite, and explores the constraint relationship between the tracking error convergence speed and the phase margin based on the system phase angle relationship.

[0080] Digital proportional resonator zero point The position on the real axis not only determines the convergence speed of the tracking error of the control system, but also determines the performance indicators of the system. Due to the system's stability constraints, the attenuation factor 'a' is less than 1000. Based on this condition, the following approximate relationship can be derived:

[0081] (14);

[0082] From the phase angle condition (9) of the control system, the zero point can be derived. phase angle satisfy:

[0083] (15);

[0084] According to equation (15), in When determined, increase That is, increase The zero point was increased accordingly. Furthermore, as can be seen from equation (14), Increasing the value of 'a' will decrease 'a', significantly slowing down the error convergence speed. Conversely, to accelerate convergence, the value of 'a' should be increased, but this will cause the zero point to... Decrease (shift left), causing The system's dynamic performance deteriorates as a result of reduced performance.

[0085] Further, refer to Figure 5 The open-loop system shown has a zero-pole distribution, and the zeros are... Must meet The constraint (otherwise there would exist a closed-loop pole outside the unit circle, making the system unstable) is therefore used. This is the critical position; the maximum phase angle is determined by trigonometric relationships. Expressed as:

[0086] (16);

[0087] By combining equations (15) and (16), we can derive the following: Corresponding maximum phase margin Meanwhile, taking zero point into consideration It cannot be too close to the 1+j0 point on the boundary of the unit circle (otherwise the control system will be downgraded to a quasi-zero type, resulting in a DC component in the grid-connected current, i.e., steady-state error). j is the imaginary axis unit, therefore the actual... If m is defined as a margin reserve value in the constraints, then:

[0088] (17);

[0089] For example, if m is 2°, then:

[0090] .

[0091] Step S103: Construct a delay compensator, determine the compensation inner loop gain h of the delay compensator according to the closed loop transfer function of the mid-frequency system, and calculate the compensation gain H according to the compensation inner loop gain h;

[0092] It should be noted that the delay process This causes the closed-loop system to form a pair of conjugate poles, resulting in the tracking error convergence deviating significantly from the expected exponential decay form. Furthermore, The introduced delay poles make The losses were substantial, further exacerbating the situation. and The contradiction between them.

[0093] To eliminate To mitigate the adverse effects while maintaining the resonator's frequency characteristics at the fundamental frequency, the controller structure in equation (7) is modified to... Equivalently removing the control loop, the system structure is determined as follows: Figure 6 (a) Closed-loop transfer function for:

[0094] (18);

[0095] In equation (18), the compensation gain H is used to maintain the preset cutoff frequency of the system unchanged; the compensation inner loop gain h is used to cancel out the error. Delay effect in the mid-frequency band.

[0096] Furthermore, the transfer function of the delay-free digital PR controller used is:

[0097] (19);

[0098] The expression for the introduced compensation inner loop is:

[0099] (20);

[0100] In summary, traditional controller design methods for the aforementioned delay-free proportional resonator implementation structure do not fully consider key performance indicators such as phase margin and control bandwidth of the actual digital implementation system. They are affected by the degradation of control delay, leading to insufficient tracking speed in high-precision scenarios and potentially causing excessive overshoot, severe oscillations, and other system damage. The delay-free proportional resonator proposed in this invention reconstructs the controller structure through cascaded delay compensation stages, effectively removing the delay stage from the control closed loop and eliminating its impact on system performance. With the introduction of the delay compensation stage, the conjugate damped oscillating poles of the traditional digital resonator are attracted to the compensated zero and fall into the real axis, exhibiting overdamped characteristics. This makes the system unaffected by the degradation of control delay, achieving ideal tracking error performance and enabling rapid response to dynamic processes.

[0101] Step S104: Define a variable A, calculate the product of variable A, the compensation inner loop gain h, and the compensation gain H, and determine whether the product is less than a first threshold.

[0102] It should be noted that in this step, to ensure that the delay compensator has the tracking capability of zero steady-state error in the fundamental frequency band and can effectively eliminate the phase angle degradation of the mid-frequency delay element, while not affecting the cutoff frequency of the control system, the parameters are configured as follows:

[0103] 1) Determination of the inner loop gain h

[0104] when hour, The gain tends to infinity, that is, we have Clearly, the closed-loop system has the ability to track the reference signal with zero steady-state error.

[0105] when hour, The controller can usually be approximated as a proportional element. ,Right now And there are At this point, equation (18) can be approximately written as:

[0106] (twenty one);

[0107] Clearly, only the configuration of h needs to satisfy:

[0108] (twenty two);

[0109] but To further simplify:

[0110] (twenty three);

[0111] Equation (23) is equivalent to Figure 6 (b) shows the control structure. Figure 6 (b) indicates that when h is configured using equation (22), in The mid-frequency band (i.e.) ), It was effectively removed from the control loop.

[0112] 2) Determination of compensation gain H

[0113] To ensure The tuning formula is valid, provided that it satisfies the following conditions: ,Right now:

[0114] (twenty four);

[0115] Furthermore, the quadratic equation for the compensation gain H is derived as follows:

[0116] (25);

[0117] consider Solving equation (25) yields:

[0118] (26);

[0119] In the formula, , , .

[0120] In summary, regarding the aforementioned delay compensator parameter configuration formula, this invention, to resolve the contradiction between control delay compensation and frequency selection characteristics, starts from the system's closed-loop transfer function, clarifies the target (control delay), and aims to equivalently remove the delay element in the mid-frequency closed-loop transfer function, thereby deriving the tuning formula for the compensation gain h. Simultaneously, to ensure that the designed system cutoff frequency remains unchanged, the gain H is adjusted to satisfy this requirement. The derived delay compensator possesses tracking capability with zero steady-state error in the fundamental frequency band and equivalent elimination of phase angle degradation from the delay element in the mid-frequency band, thus achieving ideal tracking error performance, while also possessing rapid response capability in dynamic processes.

[0121] Step S105: If the product is less than the first threshold, the tuning ends;

[0122] Step S106: If the product is greater than or equal to the first threshold, adjust the cutoff frequency according to the preset strategy and return to step S101.

[0123] For example, the bounded input-bounded output (BIBO) stability condition, i.e. Does it meet the requirements? If not, reduce the threshold. Then restart the tuning from step S101, for example, by decreasing the speed by 100 rad / s each time, and then return to step S101 to repeat the tuning and make a judgment, until the condition is met. Then the design is complete.

[0124] In summary, based on the aforementioned design method for a delay-free proportional resonator, firstly, the Taylor expansion optimization of the tuning formula significantly improves the tuning accuracy of the phase margin and cutoff frequency. Secondly, by cascading a delay compensation term in the original controller, the convergence process of the sinusoidal reference tracking error is made nearly identical to the ideal case without delay. Compared to the original controller, the delay-free digital proportional resonator proposed in this invention can overcome the phase margin limitation caused by digital control delay, ensuring that the tracking error convergence trajectory highly matches the theoretical expectation, effectively improving the control accuracy of the inverter system and enhancing power quality.

[0125] like Figure 7 As shown, one embodiment of the present invention also provides a delay-free proportional resonator design system, the system comprising:

[0126] The first relational construction module 10 is used in step S101 to establish the correlation between the attenuation factor, phase margin, and cutoff frequency based on the system phase angle condition and Taylor expansion.

[0127] ;

[0128] The second relational construction module 20 is used in step S102 to calculate the zero-point parameters of the controller based on the attenuation factor, and to construct the relationship between the zero-point parameters and the gain coefficient of the controller based on the system amplitude conditions.

[0129] ;

[0130] in, As the attenuation factor, For phase margin, Where T is the cutoff frequency, and T is the sampling frequency. The fundamental frequency, This is the gain coefficient. Zero-point parameter;

[0131] The compensation gain calculation module 30 is used in step S103 to construct a delay compensator, determine the compensation inner loop gain h of the delay compensator according to the closed loop transfer function of the mid-frequency system, and calculate the compensation gain H according to the compensation inner loop gain h.

[0132] The detection module 40 is used in step S104 to define a variable A, calculate the product of variable A, the compensation inner loop gain h, and the compensation gain H, and determine whether the product is less than a first threshold.

[0133] The first result output module 50 is used in step S105: if the product is less than the first threshold, then the tuning ends.

[0134] The second result output module 60 is used in step S106, if the product is greater than or equal to the first threshold, to adjust the cutoff frequency according to a preset strategy and return to step S101.

[0135] In another aspect, the present invention also proposes a storage medium on which one or more programs are stored, which, when executed by a processor, implement the above-described design method for a delay-free proportional resonator.

[0136] In another aspect, the present invention also proposes an electronic device, including a memory and a processor, wherein the memory is used to store a computer program, and the processor is used to execute the computer program stored in the memory to realize the above-described design method for a delay-free proportional resonator.

[0137] Those skilled in the art will understand that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can mean any means that can contain stored, communicated, propagated, or transmitted programs for use by, or in conjunction with, an instruction execution system, apparatus, or device.

[0138] More specific examples of computer-readable media (a non-exhaustive list) include: electrical connections (electronic devices) having one or more wires, portable computer disk drives (magnetic devices), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Furthermore, computer-readable media can even be paper or other suitable media on which the program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in computer memory.

[0139] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0140] While embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations fall within the scope and spirit of the invention as set forth in the claims. Furthermore, the invention described herein may have other embodiments and can be implemented or carried out in various ways.

Claims

1. A design method for a delay-free proportional resonator, characterized in that, The method comprises: Step S101: Based on the system phase angle condition and Taylor expansion, establish the relationship between the attenuation factor, phase margin, and cutoff frequency: ； Step S102: Calculate the zero-point parameters of the controller based on the attenuation factor, and construct the tuning relationship between the zero-point parameters and the controller gain coefficient based on the system amplitude conditions: ； in, As the attenuation factor, For phase margin, Where T is the cutoff frequency, and T is the sampling frequency. The fundamental frequency, This is the gain coefficient. Zero-point parameter; Step S103: Construct a delay compensator, determine the compensation inner loop gain h of the delay compensator according to the closed loop transfer function of the mid-frequency system, and calculate the compensation gain H according to the compensation inner loop gain h; Step S104: Define a variable A, calculate the product of variable A, the compensation inner loop gain h, and the compensation gain H, and determine whether the product is less than a first threshold. Step S105: If the product is less than the first threshold, the tuning ends; Step S106: If the product is greater than or equal to the first threshold, adjust the cutoff frequency according to the preset strategy and return to step S101.

2. The design method for a delay-free proportional resonator according to claim 1, characterized in that, Step S101 further includes: A single-phase inverter is constructed, wherein the inverter converts the DC side voltage into the grid-connected current injected into the grid by controlling the single-phase H-bridge through pulse width modulation. The controlled object is composed of a pulse width modulation gain and an L-type output filter stage discrete by the zero-order hold method connected in series. The grid voltage is obtained through a sampling module, real-time phase information is obtained through phase-locked loop analysis, and then a controller reference signal is generated from the phase information and a given amplitude. ； The difference between the grid-connected current reference signal and the feedback signal is defined as the tracking error, and this tracking error is sent to the input of the digital proportional resonator to calculate and generate the modulation signal for the next cycle. After a one-cycle calculation delay, the grid-connected current is generated through the controlled object. The desired tracking error is calculated according to the following formula: ； System structural constraints and From the summary, we can see that the controller satisfies: ； in, Let z be the reference signal, and z be a discrete-domain complex variable. To track errors, For closed-loop transfer function. For the error propagation function, For open-loop transfer functions, For controller, As the controlled object, For delay; Therefore, the ideal structure of the controller is: ； in, For output filter lumped inductance, This is the pulse width modulation gain.

3. The design method for a delay-free proportional resonator according to claim 2, characterized in that, S101 further includes: The ideal structure of the controller is optimized according to the following formula: ； The system open-loop transfer function is obtained based on the optimized controller structure: ； The system phase angle condition is obtained from the following formula: ； in, To ensure zero steady-state error, the controller zero point is set at the zero point. at cutoff frequency The phase angle generated at point is expressed as ; Controller conjugate poles and The sum of phase angles is expressed as Delayed process Introduced poles The resulting phase angle is expressed as ; Using Taylor expansion, we get: 。 4. The design method for a delay-free proportional resonator according to claim 3, characterized in that, Step S102 further includes: From open-loop system Gain satisfies We can obtain: ； Simplifying the above equation yields the gain coefficient tuning formula.

5. The design method for a delay-free proportional resonator according to claim 4, characterized in that, Following step S102, the following is also included: The following formula is used to construct constraints on the phase margin: ； in, is the maximum phase margin, and m is the margin reserve value.

6. The design method for a delay-free proportional resonator according to claim 5, characterized in that, Step S103 further includes: The expression for the closed-loop transfer function is: ； The controller's transfer function is: ； The transfer function of the delay compensator is: ； when At that time, And there are Then we can obtain: ； in, For the controller's transfer function, This is the introduced compensation inner loop. For the proportional element; The inner loop gain of the configuration compensation satisfies: We can obtain: 。 7. The design method for a delay-free proportional resonator according to claim 6, characterized in that, Step S103 further includes: make We can obtain: ; because Solving for: ; in, , , .

8. A delay-free proportional resonator design system, characterized in that, The system includes: The first relational construction module is used in step S101 to establish the correlation between the attenuation factor, phase margin, and cutoff frequency based on the system phase angle condition and Taylor expansion. ； The second relational construction module is used in step S102 to calculate the zero-point parameters of the controller based on the attenuation factor, and to construct the relationship between the zero-point parameters and the gain coefficient of the controller based on the system amplitude conditions: ； in, As the attenuation factor, For phase margin, Where T is the cutoff frequency, and T is the sampling frequency. The fundamental frequency, This is the gain coefficient. Zero-point parameter; The compensation gain calculation module is used in step S103 to construct a delay compensator, determine the compensation inner loop gain h of the delay compensator according to the closed loop transfer function of the mid-frequency system, and calculate the compensation gain H according to the compensation inner loop gain h. The detection module is used in step S104 to define a variable A, calculate the product of variable A, the compensation inner loop gain h, and the compensation gain H, and determine whether the product is less than a first threshold. The first result output module is used in step S105: if the product is less than the first threshold, the tuning ends. The second result output module is used in step S106. If the product is greater than or equal to the first threshold, the cutoff frequency is adjusted according to the preset strategy, and the process returns to step S101.

9. A storage medium, characterized in that, The storage medium stores one or more programs that, when executed by a processor, implement the design method for a delay-free proportional resonator as described in any one of claims 1-7.

10. An electronic device, characterized in that, The electronic device includes a memory and a processor, wherein: The memory is used to store computer programs; When the processor executes a computer program stored in the memory, it implements the design method of the delay-free proportional resonator as described in any one of claims 1-7.

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