DDR3 memory chip integrated circuit testing method and system based on particle swarm optimization

Abstract

The present application relates to the field of memory monitoring technology and provides a DDR3 memory chip integrated circuit testing method and system based on a particle swarm algorithm. A DDR3 memory chip integrated circuit testing method based on a particle swarm algorithm includes: S1: pre-configuring a testing environment and placing the chip to be tested within the testing environment; S2: powering on the chip to be tested and obtaining a feedback signal output from the output terminal of the chip to be tested; S3: converting the feedback signal into a pulse signal using a pulse conversion module; S5: collecting the frequency information of the chip to be tested at different voltages to establish a link between the frequency information and the operating voltage, and extracting evaluation parameters based on the link relationship to characterize the performance of the chip to be tested. This solution can efficiently and accurately screen out inferior chips with poor clock accuracy or poor voltage adaptability before chip mounting, significantly reducing the associated scrap losses and production costs caused by module-level test failures.

Description

Technical Field

[0001] The present application relates to the field of memory detection technology, and in particular to a DDR3 memory chip integrated circuit testing method and system based on a particle swarm algorithm. Background Art

[0002] The contents of this section merely provide background information related to this application and may not constitute prior art.

[0003] DDR3 SDRAM (Double Data Rate 3 Synchronous Dynamic Random-Access Memory), the mainstream memory technology following DDR2, focuses on improving data transfer rates, reducing power consumption, and increasing storage density. Compared to its predecessor, DDR3 chips achieve significantly higher data transfer bandwidth, improved energy efficiency, and greater single-chip storage capacity. This performance leap relies on higher operating frequencies and stricter timing control requirements, which in turn require more sophisticated clock signal sources and circuit designs.

[0004] Chip-level testing (Chip-Level Testing / Die-Level Testing) is crucial in the DDR3 chip manufacturing process after wafer fabrication and packaging. However, current testing methods commonly used in the industry focus primarily on basic functional verification and defect screening, such as checking for physical damage to the chip, internal circuit connectivity, and whether basic memory cells can be read or written. This type of testing fails to provide a comprehensive and in-depth assessment of the chip's key performance indicators.

[0005] To evaluate performance, such as actual data transmission bandwidth, stability at extreme operating frequencies, data access latency, and reliability under high-density storage, the current mainstream approach is for memory manufacturers to mount the chips onto a printed circuit board (PCB) to assemble them into memory modules. Subsequently, configuration information is burned into the module's serial presence detection chip to ensure basic operational capabilities. Finally, performance testing is completed by running specialized memory diagnostic and performance analysis software on a specialized memory system or test platform.

[0006] Although this testing method based on finished modules can intuitively reflect the overall performance of the final product, its testing cost is extremely high. In essence, this is the final quality inspection of the finished module, rather than a performance screening of the bare chip or the packaged chip itself. Its core disadvantage lies in its destructive nature: once the test finds that the performance does not meet the standards or there are defects, the chip needs to be removed from the PCB, which can easily cause irreversible physical damage to the PCB pads and chip pins. PCBs with obvious signs of disassembly are usually not reusable. Therefore, in practice, the entire assembled PCB, the problematic chip, and other intact electronic components on the board (such as resistors, capacitors, SPD chips, etc.) often have to be scrapped as defective products. This not only results in the waste of the chip itself, but also leads to the collateral loss of the PCB and auxiliary components, significantly increasing the company's overall production costs. Summary of the Invention

[0007] In view of this, the purpose of this application is to provide a DDR3 memory chip integrated circuit testing method and system based on particle swarm algorithm. The DDR3 memory chip integrated circuit testing method and system based on particle swarm algorithm disclosed in this application can solve the technical problems provided by the background technology.

[0008] The purpose of this application is achieved through the following technical solutions:

[0009] A DDR3 memory chip integrated circuit testing method based on a particle swarm algorithm comprises:

[0010] S1: Pre-configure the test environment and place the chip to be tested in the test environment;

[0011] S2: Power on the chip to be tested and obtain the feedback signal output from the output terminal of the chip to be tested;

[0012] S3: The feedback signal is converted into a pulse signal using a pulse conversion module;

[0013] S4: receiving the number of signals generated by the pulse signal output from the output terminal of the chip under test within a unit time, and generating detection frequency information;

[0014] S5: Collect the frequency information of the chip under test at different voltages, establish a link between the frequency information and the operating voltage, and extract the evaluation parameters of the link relationship to characterize the performance of the chip under test based on the particle swarm algorithm.

[0015] The technical solution of this application achieves non-destructive chip-level performance evaluation by directly acquiring and analyzing the clock pulse signals (S1-S4) output by the DDR3 chip under test on a dedicated test platform and establishing a characteristic relationship between its frequency and operating voltage (FV characteristics) (S5). This method effectively avoids the costly process of mounting the chip on a PCB, burning the SPD, and assembling it into a module for destructive testing. Analyzing the uniformity of the pulse interval directly reflects the timing jitter and stability of the chip's internal clock signal; and by examining whether the FV characteristics meet expectations (linearity, response range), the chip's clock circuit's adaptability to voltage changes and process consistency can be evaluated. Consequently, this solution can efficiently and accurately screen out inferior chips with poor clock accuracy or voltage adaptability before chip mounting, significantly reducing the associated scrap losses and production costs caused by module-level test failures.

[0016] When directly testing DDR3 memory chips, applying an inappropriate operating voltage poses a serious risk. Because different DDR3 chip models have different allowable normal operating voltage ranges and maximum withstand voltages, if the test voltage exceeds the tolerance of a specific chip model, it is very likely to cause the chip's internal circuits to break down or burn due to overvoltage, causing permanent damage to the chip. To this end, this application provides the following technical solutions:

[0017] In some possible embodiments, S1 includes the following steps:

[0018] S11: Configure the chip reading system to read the model of the chip to be tested;

[0019] S12: Configuring a power supply module according to the model of the chip to be tested to provide a corresponding power supply environment for the chip to be tested.

[0020] This embodiment configures the chip reading system in step S11, which can automatically identify the specific model of the chip to be tested before the test begins. Based on the identified model information, step S12 dynamically adjusts the output parameters of the power supply module to accurately provide the rated operating voltage and safe test voltage range specified by the model of the current chip to be tested. This solution effectively solves the voltage mismatch problem caused by manual setting errors or universal voltage settings, fundamentally prevents the risk of chip overvoltage breakdown or burning caused by excessive voltage during the test process, and significantly improves the safety and reliability of the test process. At the same time, this solution ensures that the test platform can automatically adapt to a variety of different models of DDR3 chips, laying a safe and adaptive power supply foundation for subsequent performance test steps (S2-S5).

[0021] Relying solely on the single maximum frequency output of the DDR3 memory chip under test makes it difficult to fully and accurately assess the actual performance and overall quality of its internal functional units. Chips typically contain multiple independent or related functional core units (such as different memory banks, control logic, I / O interfaces, etc.). Testing only the overall output frequency may mask performance defects in local units (such as timing anomalies in specific banks or poor signal integrity in some I / O paths), leading to a misjudgment of the chip's overall performance. To this end, this application provides the following technical solutions:

[0022] In some possible embodiments, S2 includes the following steps:

[0023] S21: Obtain the model of the chip to be tested, and obtain the core unit corresponding to each pin of the chip based on the model of the chip to be tested;

[0024] S22: pins corresponding to the same core unit are treated as an information group;

[0025] S23: receiving, for each information group, an original signal generated by each pin after power is applied;

[0026] S24: Collect the original signal of each information group and use all the original signals as feedback signals.

[0027] This embodiment, through steps S21-S22, accurately identifies the internal structure of the chip under test based on its model information and logically groups the relevant pins by functional core unit (such as bank, control logic block, etc.), forming multiple independent information groups. Steps S23-S24 then separately collect and aggregate the raw signals generated by all pins within each information group after power is applied. This functional unit-based grouped signal acquisition mechanism ensures that the signal collection of each information group directly reflects the operating status and performance of its corresponding core unit. By parallelizing the raw signal characteristics of each information group (such as timing, amplitude, and noise), it can reveal performance differences between different functional areas within the chip and locate potential local defects (such as abnormal access latency in a specific bank or signal distortion in a specific I / O path). Compared to relying solely on a single frequency metric, this method provides performance distribution information in a spatial dimension, enabling a refined assessment of the health of each functional unit within the DDR3 chip.

[0028] The core principle of this application is to evaluate the performance of the DDR3 chip under test by analyzing the frequency characteristics of its output signal. However, in a test environment where the chip has not been initialized, configured, or debugged, the raw signal it generates often exhibits dramatic frequency fluctuations and complex amplitude variations. These unstable signal characteristics make it extremely difficult to directly and accurately extract and identify key frequency information, seriously affecting the reliability of performance judgments. Based on this, this application provides the following technical solutions:

[0029] In some possible embodiments, S3 includes the following steps:

[0030] S31: The signal amplifying unit is used to amplify the feedback signal to generate an analog signal;

[0031] S32: Divide the analog signal into three paths and perform amplitude filtering in different ranges on each path to obtain a first filtered signal, a second filtered signal, and a third filtered signal;

[0032] S33: replacing the peaks in the first filtered signal, the second filtered signal, and the third filtered signal with positive pulses, and replacing the troughs with negative pulses, and coupling them into pulse signals.

[0033] After improving the signal-to-noise ratio through signal amplification, the signal processing flow (S31-S33) of this solution critically uses branch amplitude filtering (S32) to separate signal components of different intensities, effectively eliminating mutual interference and frequency aliasing between strong and weak signals. Furthermore, each filtered signal is independently converted from peak / valley to pulse (S33), accurately capturing the periodic characteristics (zero crossings) of the signals in each amplitude interval, significantly suppressing the impact of the original signal fluctuations on frequency recognition. The pulse signal finally generated by coupling integrates the timing information of each amplitude layer, providing a stable and reliable basis for subsequent precise frequency statistics (S4) that better reflects the essential periodic characteristics of the signal, greatly improving the accuracy and robustness of frequency detection, thereby enhancing the credibility of chip performance evaluation.

[0034] In some possible embodiments, the amplitude filtering ranges corresponding to the first filtered signal, the second filtered signal, and the third filtered signal do not intersect with each other.

[0035] In this solution, the amplitude filters corresponding to the first filtered signal, the second filtered signal, and the third filtered signal do not intersect with each other, so the amplitude components corresponding to the first filtered signal, the second filtered signal, and the third filtered signal are different from each other. The fusion of the three can better reflect all the peaks in the feedback signal.

[0036] Due to the high operating frequency of DDR3 memory chips, the pin output signal frequency is extremely high and the waveform is complex. Traditional detection methods that track signal amplitude changes in real time cannot accurately capture the transient characteristics of high-frequency peaks and troughs at limited sampling rates. Missing or offset sampling points can easily lead to misjudgment of the cycle, seriously reducing the frequency detection accuracy.

[0037] In some possible embodiments, the method for replacing a peak with a positive pulse and a trough with a negative pulse includes the following steps:

[0038] S331: setting the peak excitation threshold range and the trough excitation threshold according to the amplitude filtering range;

[0039] S332: Receive the filtered signal, and when the signal enters the excitation threshold range of the peak, it is recorded as a positive pulse; when the signal enters the excitation threshold range of the trough, it is recorded as a negative pulse;

[0040] S333: The positive pulse and the negative pulse have the same duration, generating a pulse signal.

[0041] This application converts high-frequency signal detection into a count of the number of times the signal enters the threshold range by presetting the peak / trough amplitude excitation threshold (S331) and adopting a discrete trigger mechanism (S332), thereby avoiding the strict sampling rate requirements of traditional real-time waveform tracking; this design ensures that under a limited sampling rate (the sampling point spacing is less than the peak spacing but insufficient to cover the details), each real peak / trough only triggers a single equal-width pulse (S333), effectively suppressing misjudgments caused by signal jitter or sampling offset; the final generated pulse signal strictly retains the original number of cycles and eliminates waveform distortion interference, providing a high-fidelity, interference-resistant cycle counting basis for subsequent frequency statistics (S4), significantly improving the accuracy of high-frequency signal detection.

[0042] While the high-frequency signals of DDR3 memory chips reflect basic performance, relying solely on frequency metrics cannot assess actual data transmission stability (such as signal distortion during string operations). However, at ultra-high frequencies, directly detecting signal waveform distortion (such as clipping and flattening) requires ultra-high-speed sampling and real-time analysis, which is difficult to implement in hardware and suffers from low accuracy, leading to a lack of stability assessment. To this end, this application provides the following technical solutions:

[0043] Furthermore, S4 includes the following steps:

[0044] S41: Send the pulse signal to the positive pulse counter, and generate 1 positive counting information when a positive pulse is received;

[0045] S42: Send the pulse signal to the negative pulse counter, and generate 1 negative counting information when a negative pulse is received;

[0046] S43: Send the pulse signal to the pulse change counter, and generate 1 change count information when b pulse signals change direction;

[0047] S44: All positive count information, all negative count information, and all conversion count information are used as frequency information.

[0048] This application uses a triple pulse compression counting mechanism (S41-S43) to efficiently convert high-frequency pulse signals into three core indicators: positive / negative counting information (one count is generated for every a pulse) directly quantifies the basic frequency performance of the chip; transformation counting information (one count is generated for every b direction switches) quantifies signal stability without sampling burden by capturing direction switching omissions (caused by distortion such as clipping / flat bottom); the three are integrated (S44) to form a frequency-stability dual-dimensional evaluation system, breaking through the bottleneck of high-frequency real-time analysis and providing accurate data support for the comprehensive performance judgment of the chip.

[0049] In chip performance evaluation, traditional similarity matching schemes rely too much on the global similarity threshold and are unable to sensitively capture subtle differences in frequency information (such as subtle frequency offsets caused by operating voltage fluctuations). This leads to over-generalization of matching results and seriously restricts the accuracy of chip performance grading.

[0050] In some possible implementations, S5 includes the following steps:

[0051] S51: Obtain frequency information of each information group, and establish a database of frequency information, operating voltage, and performance level for each information group;

[0052] S52: Using the frequency information and the operating voltage as prediction data and the performance level as label data, a corresponding relationship between the prediction data and the label data is established based on the data collected in the database, and a relationship correspondence vector is generated;

[0053] S53: Collect the frequency information and operating voltage of the chip to be tested as prediction data, extract the most corresponding label data from the database based on the particle swarm algorithm, use the label data as the performance level of the chip to be tested, and generate evaluation parameters according to the performance levels of all information groups.

[0054] The technical solution provided by this application does not use similarity matching to match the corresponding label data from a preset database. Instead, it uses a particle swarm algorithm to match the closest label data. Compared with similarity matching, the particle swarm matching method in this application can guide the matching direction and refine the matching requirements by changing the fitness function, thereby increasing the accuracy of the label data description.

[0055] Traditional particle swarm optimization (PSO) algorithms suffer from low convergence efficiency in chip performance matching due to their purely random exploration mechanism: particles rely solely on individual and group experience to blindly search in a two-dimensional parameter space, resulting in a long single match time and failure to meet real-time requirements. Furthermore, high iterative calculations exacerbate system resource consumption. Based on this, this application provides the following technical solutions:

[0056] S53 includes the following steps:

[0057] S531: Randomly generate m particles x in a two-dimensional plane i =(H` i , V` i ), (H` i , V` i ) represents the position of the i-th particle in the two-dimensional plane;

[0058] S532: Setting the fitness function F and calculating the fitness value of the spectrum to be measured;

[0059] ;

[0060] Among them, x i represents the position of the i-th particle in the two-dimensional plane, represents the comprehensive difference of features, Indicates the absolute deviation of the operating voltage;

[0061] ;

[0062] ;

[0063] Indicates the operating voltage of the chip under test, represents the working voltage of the i-th particle recorded in the database, Indicates the first dimension value of the chip to be tested, represents the first dimension value of the i-th particle recorded in the database; λ1 and λ2 represent the first weight parameter and the second weight parameter respectively;

[0064] S533: For each particle i, compare the fitness of the current position, traverse all particles, select the individual optimal position with the highest fitness, and use the individual optimal position as the global optimal position;

[0065] Each particle is updated as follows:

[0066] ;

[0067] in, represents the velocity vector of the i-th particle, represents the inertia weight, and denote the first learning coefficient and the second learning coefficient respectively, 、 as well as Represent the first random factor, the second random factor and the third random factor respectively; represents the individual historical optimal position of particle i; represents the historical optimal position of the group, Indicates the nearest closed plane center. The closed plane is the plane formed by connecting the points of the predicted data corresponding to each performance level in the database in two-dimensional space. represents the updated position of the i-th particle in the two-dimensional plane;

[0068] S534: When the termination condition is met, the update is stopped and the particle with the highest fitness value is selected; the termination condition is that the number of iterations reaches the maximum value, or the fitness change is less than a preset threshold.

[0069] In the technical solution provided by this application, when updating the particle position, it is not updated randomly according to the optimal particle position, but an , it will actively move towards the center of the closest closed plane. In this way, the particles have a clear direction when updating their positions, which can further increase the convergence efficiency of the model and reduce the number of iterations.

[0070] A DDR3 memory chip integrated circuit testing system based on a particle swarm algorithm adopts the DDR3 memory chip integrated circuit testing method based on a particle swarm algorithm to test memory chip performance.

[0071] The core advantage of the technical solution presented in this application is that it enables direct chip-level performance evaluation of DDR3 memory chips, eliminating the traditional steps of mounting the chip on a printed circuit board (PCB), burning SPD information, and assembling it into a complete memory module. By directly acquiring the clock signal output by the chip under test on a dedicated test platform and converting it into a pulse signal using a pulse conversion module, this method can extract and analyze key parameters that characterize the chip's intrinsic performance.

[0072] Signal integrity: Clock signals from low-quality chips often exhibit significant timing jitter and duty cycle distortion. These defects are directly reflected in the converted pulse signal as uneven pulse spacing. This method effectively assesses the accuracy and stability of the chip's internal clock circuit by analyzing the uniformity of the pulse sequence.

[0073] Voltage-Frequency Response Consistency: A high-quality DDR3 chip should exhibit linear or predictable frequency-voltage variation within its nominal voltage range. Poor chip quality (e.g., due to internal clock circuit design flaws or process fluctuations) can result in a frequency response that deviates from expectations (e.g., experiencing abrupt frequency changes at specific voltage points, failing to reach the target frequency, or being overly sensitive or insensitive to voltage changes). The FV link established in step S5 is used to detect these inconsistencies.

[0074] Therefore, the technical solution of this application can efficiently and accurately evaluate the accuracy of the chip's internal clock generation circuit and the consistency of the clock frequency with the operating voltage by directly and non-destructively analyzing the pulse signal characteristics and FV relationship output by the chip under test. This provides an effective means for performance screening and grading after chip packaging and before assembly, fundamentally avoiding the associated scrapping problem caused by module-level test failures described in the background art, significantly reducing testing costs and production losses. BRIEF DESCRIPTION OF THE DRAWINGS

[0075] Figure 1 The flowchart of the DDR3 memory chip integrated circuit testing method based on particle swarm optimization.

[0076] Figure 2 Schematic diagram of the peak threshold of the filtered signal.

[0077] Figure 3 Schematic diagram of particle swarm optimization update.

[0078] Figure 4 This is a structural diagram of a DDR3 memory chip integrated circuit test system based on particle swarm optimization. DETAILED DESCRIPTION

[0079] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific implementation methods. The same figure marks in the accompanying drawings represent the same components. It should be noted that the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the described embodiments of this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0080] Compared to the embodiments shown in the drawings, feasible embodiments within the scope of protection of the present application may have fewer components, other components not shown in the drawings, different components, differently arranged components, or differently connected components, etc. In addition, two or more components in the drawings may be implemented in a single component, or a single component shown in the drawings may be implemented as multiple separate components.

[0081] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by persons of ordinary skill in the field to which this application belongs. The words "first", "second" and similar terms used in the specification and claims of this application do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "a" or "an" do not necessarily indicate a quantitative limitation. "Up", "down" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0082] refer to Figure 1 Embodiment 1: A DDR3 memory chip integrated circuit testing method based on a particle swarm algorithm, comprising:

[0083] S1: Pre-configure the test environment and place the chip to be tested in the test environment.

[0084] S1 includes the following steps:

[0085] S11: Configure the chip reading system to read the model of the chip to be tested;

[0086] The reader system is a pre-prepared test circuit board that primarily powers the chip and receives signals from its pins. At this point, the chip has no program yet programmed; instead, it transmits signals driven by an internal clock source. While these signals have no practical meaning, they indicate the chip's information transmission and processing capabilities.

[0087] The reading system physically contacts the SPD interface of the chip under test through a four-wire probe, uses the I²C serial protocol to send standard query commands, reads the 16-byte JEDEC ID code pre-programmed into the chip, and parses the manufacturer, density, and timing parameters based on the local model database, ultimately outputting the complete chip model to the power module.

[0088] S12: Configuring a power supply module according to the model of the chip to be tested to provide a corresponding power supply environment for the chip to be tested.

[0089] The power module dynamically configures the power supply environment based on the chip model it receives. It automatically matches the voltage strategy (VDDQ = 1.35V for low-voltage models and VDDQ = 1.5V for standard models) and simultaneously sets the overcurrent protection threshold based on chip density (8Gb / 10A, 16Gb / 15A). This is just one example of a power matching solution; the specific power matching method will not be further described here.

[0090] S2: Power on the chip to be tested and obtain the feedback signal output from the output terminal of the chip to be tested;

[0091] S2 includes the following steps:

[0092] S21: Obtain the model of the chip to be tested, and obtain the core unit corresponding to each pin of the chip based on the model of the chip to be tested.

[0093] The system reads the pre-established model-unit mapping database (which stores the internal core unit layout corresponding to various chip models), and automatically retrieves and outputs all core unit definitions (such as "Bank0-7", "Control Logic Unit", "Data Buffer Unit", etc. of the DDR3 chip) based on the chip model to be tested obtained by S11, completing the precise mapping of models to physical units.

[0094] S22: Pins corresponding to the same core unit are regarded as an information group.

[0095] Intelligent pin grouping based on core unit definitions: This approach analyzes chip pin function manuals (such as JEDEC standards) and dynamically groups all pins serving the same core unit (e.g., address lines A0-A14 and data lines DQ0-DQ15 corresponding to Bank 0) into a single information group, forming a "unit-pin group" topology matrix. For example, the output information for pins related to a data buffer unit is grouped together. In practice, multiple units may share a single pin. This solution essentially selects pins with different operating frequencies, and using modular pin grouping offers greater versatility in practice.

[0096] S23: For each information group, receive the original signal generated by each pin after power is turned on.

[0097] A parallel signal acquisition channel is started for each information group: the original voltage waveforms of all pins in the group after power-on are synchronously captured through multiple high-speed ADCs (analog-to-digital converters) to obtain the original signals.

[0098] S24: Collect the original signal of each information group and use all the original signals as feedback signals.

[0099] The original signal sequence of each information group is encapsulated into a data packet, and the data packets of all information groups are finally aggregated to form a structured feedback signal set, that is, feedback information. In this way, the feedback signal is the original signal of different information groups after power is turned on.

[0100] S3: The feedback signal is converted into a pulse signal using a pulse conversion module;

[0101] S3 includes the following steps:

[0102] S31: The signal amplifying unit is used to amplify the feedback signal to generate an analog signal;

[0103] Specifically, the signal amplification method is an existing technology. In order to ensure signal integrity, this application adopts the following solution:

[0104] A dynamic gain control loop is constructed through a programmable gain amplifier to amplify the 50μV analog signal to a 1.5V volt-level analog signal without distortion, and signal integrity is ensured by TVS diode clamping protection and 5μs gain switching delay.

[0105] S32: Divide the analog signal into three paths and perform amplitude filtering in different ranges on each path to obtain a first filtered signal, a second filtered signal, and a third filtered signal;

[0106] The amplitude filtering ranges corresponding to the first filtered signal, the second filtered signal, and the third filtered signal do not intersect with each other.

[0107] Specifically:

[0108] Amplitude separation is achieved using a three-channel bandpass filter bank:

[0109] Channel 1 (0.8V-1.2V) generates the first filtered signal (capturing small fluctuations);

[0110] Channel 2 (1.2V-1.8V) generates the second filtered signal (capturing medium-amplitude fluctuations);

[0111] Channel 3 (1.8V-2.5V) generates the third filtered signal (capturing large fluctuations);

[0112] The threshold range of each channel is strictly isolated and monitored in real time by a voltage comparator (LM393) to ensure there is no overlap.

[0113] In this solution, a three-channel bandpass filter group is used to separate signals well, and the obtained first filtered signal, second filtered signal and third filtered signal are different from each other in signal amplitude.

[0114] S33: replacing the peaks in the first filtered signal, the second filtered signal, and the third filtered signal with positive pulses, and replacing the troughs with negative pulses, and coupling them into pulse signals.

[0115] The method for replacing the peak with a positive pulse and the trough with a negative pulse includes the following steps:

[0116] S331: setting the peak excitation threshold range and the trough excitation threshold according to the amplitude filtering range;

[0117] Based on the amplitude range of the three-channel filtered signal (channel 1: 0.8-1.2V, channel 2: 1.2-1.8V, channel 3: 1.8-2.5V), the dual-threshold excitation range is hardware-fixed through the resistor divider network:

[0118] Peak threshold: 90% to 99% of the upper limit of each channel (e.g., 1.08-1.2V for channel 1);

[0119] Valley threshold: 1% to 10% of the lower limit of each channel (e.g. 0-0.12V for channel 1);

[0120] The three-channel thresholds are strictly isolated and verified to have no overlap by the LM2903 voltage comparator.

[0121] Due to the amplitude compression characteristics of the bandpass filter, a high-amplitude signal will produce a limiting effect when approaching the channel upper limit, resulting in a voltage platform (flat-top area) at the top of the waveform. To avoid triggering multiple false pulse counts in this platform area, this solution actively compresses the upper limit of the peak threshold:

[0122] refer to Figure 2 , Figure 2 The horizontal axis is time in milliseconds, and the vertical axis is amplitude in V. The actual maximum value of the peak threshold is set to 99% of the corresponding channel filter upper limit (e.g., the upper limit of channel 2 is 1.8V → the peak threshold upper limit = 1.8V × 99% = 1.782V). Figure 2 As shown, Figure 2 The dotted line in the figure is the peak threshold interval. It can be seen that only part of the high-amplitude waveform is within the peak threshold, which is much smaller than the unfiltered waveform.

[0123] This design has the following benefits:

[0124] (1) The voltage in the flat-top region is excluded from the threshold range (>1.782V will not trigger), ensuring that only a single positive pulse is generated in the single peak.

[0125] (2) The residence time of high-amplitude signals within the threshold is shortened to less than 1% of the original value.

[0126] (3) Combined with the hysteresis comparator design, the edge jitter of the platform area cannot cross the threshold boundary after compression, thus suppressing false triggering from the source.

[0127] like Figure 2 As shown in the figure, after setting the peak value range, most of the platform area cannot be selected. When the sampling frequency is insufficient, the signal around the platform is sampled with a small probability.

[0128] S332: Receive the filtered signal, and when the signal enters the excitation threshold range of the peak, it is recorded as a positive pulse; when the signal enters the excitation threshold range of the trough, it is recorded as a negative pulse;

[0129] Use voltage monitor to monitor the filtered signal in real time:

[0130] When the signal amplitude is continuously ≥ the lower limit of the peak threshold (for example, channel 1>1.08V), the positive marker signal (high level) is triggered;

[0131] When the signal amplitude is continuously less than or equal to the upper valley threshold (for example, channel 1 is less than 0.12V), a negative-going marker signal (low level) is triggered.

[0132] The filtered signals here refer to the first filtered signal, the second filtered signal and the third filtered signal. In actual work, the first filtered signal, the second filtered signal and the third filtered signal are collected in turn to obtain positive marking signals and negative marking signals of the three filtered signals.

[0133] S333: The positive pulse and the negative pulse have the same duration, generating a pulse signal.

[0134] Use a monostable trigger (such as 74HC123) to convert the marker signal into a standard pulse:

[0135] Positive mark trigger → output 5ns width +3.3V pulse (positive pulse);

[0136] Negative-going mark trigger → outputs a -1V pulse (negative-going pulse) with a width of 5ns;

[0137] Finally, the three-channel pulse streams are coupled through a high-speed OR gate (NC7SZ32) to generate a unified bipolar pulse signal.

[0138] In S33, the analog signal is converted into a pulse signal, which makes the converted analog signal more stable and easier to read the number of peaks. In practice, the high-amplitude filtered signal is input first, so the resulting pulse signal has the frequency information of the high-amplitude component in the front, the frequency information of the medium-amplitude component in the middle, and the frequency information of the low-amplitude component in the back.

[0139] S4: receiving the number of signals generated by the pulse signal output from the output terminal of the chip under test within a unit time, and generating detection frequency information;

[0140] S4 includes the following steps:

[0141] S41: Send the pulse signal to the forward pulse counter, and generate 1 forward counting information when a forward pulses are received.

[0142] The high-speed counter receives the positive pulse component (+3.3V level) of the pulse signal, configures the preset number register to set the threshold a (such as a=8), and when every 8 positive pulse rising edges are accumulated, the counter overflow pin outputs a 50ns width positive counting information (TTL high-level pulse) and automatically resets at the same time.

[0143] S42: Send the pulse signal to the negative pulse counter, and generate 1 negative counting information when a negative pulses are received.

[0144] The same high-speed counter is used to process the negative pulse component (-1V level). The negative pulse is raised to a 0-3.3V signal by a level converter and then input into the counter. The threshold a=8 is set synchronously. When 8 rising edges of negative pulses are accumulated, 50ns negative counting information (TTL high-level pulse) is output to achieve symmetrical counting logic with the positive channel.

[0145] S43: Send the pulse signal to the pulse change counter, and generate 1 change count information when b pulse signals with direction changes are received.

[0146] Specifically:

[0147] Use dual D flip-flops to build an edge state machine, marking a direction change when two consecutive pulses have opposite polarities (such as +3.3V→-1V or -1V→+3.3V);

[0148] Accumulation trigger: The CD4020 counter receives the direction change mark, with a preset threshold b=4 (set by the DIP switch). Every time 4 direction change events are accumulated, a 100ns change count information (CMOS high-level pulse) is output on the Q14 pin.

[0149] S44: All positive count information, all negative count information, and all conversion count information are used as frequency information.

[0150] Frequency information, including the number of positive pulses, the number of negative pulses, and the number of transitions between positive and negative pulses, provides an implicit understanding of the chip's performance. In practice, frequency information also requires the length of the original signal. In practice, the length of the original signal is typically a predetermined unit length, so the content can be directly characterized based on these three values ​​in the frequency information.

[0151] S5: Collect the frequency information of the chip under test at different voltages, establish a link between the frequency information and the operating voltage, and extract the evaluation parameters of the link relationship to characterize the performance of the chip under test based on the particle swarm algorithm.

[0152] S5 includes the following steps:

[0153] S51: Obtain frequency information of each information group, and establish a database of frequency information, operating voltage and performance level for each information group.

[0154] The chip uses different modules, each corresponding to an information group. In this solution, the performance of each information group, that is, each module of the chip, is evaluated, and then the performance level of the entire chip is obtained by combining the performance evaluation of each module.

[0155] The database construction method is as follows: frequency information and operating voltage of chips with known performance are collected in advance, and then the frequency information, operating voltage and performance level of the chip are used as a sample. After collecting multiple samples, a database is formed.

[0156] S52: Using the frequency information and the operating voltage as prediction data and the performance level as label data, a corresponding relationship between the prediction data and the label data is established based on the data collected in the database, and a relationship correspondence vector is generated.

[0157] Frequency information and operating voltage are information that can be measured by the chip under test, and are therefore used as prediction data. Performance level is information that needs to be predicted, and is therefore used as label data.

[0158] The performance levels are pre-set and are mainly divided into levels based on the performance of the chip. The specific division method is not detailed here.

[0159] Furthermore, the relationship correspondence vectors are a number of overlapping cones. Specifically:

[0160] Project the three-dimensional information of frequency information H (a, b, c) into one-dimensional space to generate the first dimension value H';

[0161] ;

[0162] Among them, a represents the number of positive counting information, b represents the number of negative counting information, and c represents the number of conversion counting information. >1, , 、 、 Represents the weight parameter.

[0163] The first dimension value H' is related to the size of a, b, and c. It will only increase when a, b, and c increase synchronously. The reason is as follows: if a is much larger than b, it means that there is a lack of negative pulses, and the corresponding c will inevitably be very small. Then, the first dimension value will gradually decrease due to the increase in the weight of a, and the same is true for the increase in b. Since c is highly correlated with a and b, it is impossible for c to increase rapidly on its own. Therefore, the size of the first dimension value H' can accurately reflect the impact of frequency information on the chip performance level. This projection mechanism dynamically penalizes unbalanced growth (such as unilateral pulse surges) and forces parameter coupling, making H' sensitive only to the coordinated changes of the three parameters, thereby accurately characterizing the intensity of the impact of frequency characteristics on the chip performance level.

[0164] Project the operating voltage into one-dimensional space to generate a second-dimensional value V';

[0165] The operating voltage itself is a one-dimensional series, so the operating voltage is equal to the second dimension value V';

[0166] Project the predicted data onto a two-dimensional plane, using the first and second dimension values ​​as the horizontal and vertical coordinates, respectively. For example, for predicted data R(H', V'), projecting the performance level onto a one-dimensional space generates the third-dimensional value Z'. Since the performance level is also a one-dimensional discrete series, it is equal to the third-dimensional value Z'.

[0167] For each performance level Z`, the corresponding prediction data R(H`, V`) is found from the database, and the closed plane formed by all R(H`, V`) in the database is matched with the performance level Z` to form a cone E(Z`, S), where S represents the projection plane of the cone, and S is composed of the prediction data R that constitute the closed plane.

[0168] S53: Collect the frequency information and operating voltage of the chip to be tested as prediction data, extract the most corresponding label data from the database based on the particle swarm algorithm, use the label data as the performance level of the chip to be tested, and generate evaluation parameters according to the performance levels of all information groups.

[0169] In practice, the number of samples that can be collected is limited. Therefore, not every point in the two-dimensional plane where the predicted data is projected can find matching predicted data in the database. Most data points in the two-dimensional plane do not correspond to the preset data in the database. To this end, this application uses a particle swarm algorithm to diffuse among known data points, traverse all known data points, and then compare the known data points with the data points of the chip to be tested, so that the predicted data in the database that is closest to the chip to be tested can be found relatively accurately.

[0170] refer to Figure 3 , further, S53 includes the following steps:

[0171] S531: Randomly generate m particles x in a two-dimensional plane i =(H` i , V` i ), (H` i , V` i ) represents the position of the i-th particle in the two-dimensional plane;

[0172] S532: Setting the fitness function F and calculating the fitness value of the spectrum to be measured;

[0173] ;

[0174] Among them, x i represents the position of the i-th particle in the two-dimensional plane, represents the comprehensive difference of features, Indicates the absolute deviation of the operating voltage;

[0175] ;

[0176] ;

[0177] Indicates the operating voltage of the chip under test, represents the working voltage of the i-th particle recorded in the database, Indicates the first dimension value of the chip to be tested, represents the first dimension value of the i-th particle recorded in the database; λ1 and λ2 represent the first weight parameter and the second weight parameter, respectively.

[0178] The fitness function is analyzed as follows: when the predicted data of the chip to be tested is exactly the same as the predicted data in the database, the value of the fitness function F is 1; when there is a difference between the two, the fitness function value F will gradually decrease.

[0179] S533: For each particle i, compare the fitness of the current position, traverse all particles, select the individual optimal position with the highest fitness, and use the individual optimal position as the global optimal position;

[0180] Each particle is updated as follows:

[0181] ;

[0182] in, represents the velocity vector of the i-th particle, represents the inertia weight, and denote the first learning coefficient and the second learning coefficient respectively, 、 as well as Represent the first random factor, the second random factor and the third random factor respectively; represents the individual historical optimal position of particle i; represents the historical optimal position of the group, represents the nearest closed plane center, Represents the updated position of the i-th particle in the two-dimensional plane.

[0183] The closed plane is formed by connecting the points of the predicted data corresponding to each performance level in the database in two-dimensional space. When particles are updated, they diffuse toward the center of the closed plane, which can guide the particles to quickly converge to the characteristic area of ​​the corresponding performance level.

[0184] S534: When the termination condition is met, stop updating and select the particle with the highest fitness value;

[0185] The termination condition is that the number of iterations reaches the maximum value, or the fitness change is less than the preset threshold, such as 50 iterations or fitness change <0.001%.

[0186] The above method can be used to obtain the performance level of the module corresponding to each signal group of the chip under test, so as to obtain the evaluation parameters of the comprehensive performance of the chip under test.

[0187] In the technical solution provided in this application, a particle swarm algorithm is used for predictive data matching, which can reduce the number of data comparisons compared to cosine similarity, and at the same time focus more on the differences in detailed information within frequency information, thereby increasing the accuracy of performance prediction.

[0188] refer to Figure 4 , Example 2: A DDR3 memory chip integrated circuit testing system based on particle swarm algorithm, which uses the DDR3 memory chip integrated circuit testing method based on particle swarm algorithm to test the performance of the memory chip.

[0189] Specifically: The DDR3 memory chip integrated circuit test system based on the particle swarm algorithm includes: a chip reading system, a power module, a programmable gain amplifier, a three-channel bandpass filter, a voltage monitor, a monostable trigger, a positive pulse counter, a negative pulse counter, a dual D trigger and a particle swarm module.

[0190] The chip under test is installed in a chip reading system, and a power module supplies power to the chip reading system, ensuring normal operation of the chip under test. A programmable gain amplifier is connected to the chip reading system and is used to amplify the signals from each pin of the chip under test. A three-channel bandpass filter is also connected to the programmable gain amplifier and is used to filter the original signal to generate a first filtered signal, a second filtered signal, and a third filtered signal.

[0191] A voltage monitor is connected to the three-channel bandpass filter signal, and a monostable trigger is connected to the voltage monitor. The voltage monitor and monostable trigger are used to convert the first, second, and third filtered signals into pulse signals. A positive pulse counter, a negative pulse counter, and a dual D flip-flop are respectively connected to the monostable trigger signal to generate frequency information. A particle swarm module is used to receive frequency information and operating voltage and execute the aforementioned particle swarm algorithm to calculate the performance level of the chip under test.

[0192] The above are merely preferred embodiments of the present application and are not intended to limit the present application. Those skilled in the art will readily appreciate that various modifications and variations are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A DDR3 memory chip integrated circuit testing method based on particle swarm optimization, characterized in that: include: S1: Pre-configure the test environment and place the chip to be tested in the test environment; S2: Power on the chip to be tested and obtain the feedback signal output from the output terminal of the chip to be tested; S3: The feedback signal is converted into a pulse signal using a pulse conversion module; S4: receiving the number of signals generated by the pulse signal output from the output terminal of the chip under test within a unit time, and generating detection frequency information; S5: Collect frequency information of the chip under test at different voltages, establish a link between the frequency information and the operating voltage, and extract evaluation parameters of the link relationship to characterize the performance of the chip under test based on the particle swarm algorithm; S3 includes the following steps: S31: The signal amplifying unit is used to amplify the feedback signal to generate an analog signal; S32: Divide the analog signal into three paths and perform amplitude filtering in different ranges on each path to obtain a first filtered signal, a second filtered signal, and a third filtered signal; S33: replacing the peaks in the first filtered signal, the second filtered signal, and the third filtered signal with positive pulses and the troughs with negative pulses, and coupling them into pulse signals; The amplitude filtering ranges corresponding to the first filtered signal, the second filtered signal, and the third filtered signal do not intersect with each other; The method for replacing the peak with a positive pulse and the trough with a negative pulse includes the following steps: S331: setting the peak excitation threshold range and the trough excitation threshold according to the amplitude filtering range; S332: Receive the filtered signal, and when the signal enters the excitation threshold range of the peak, it is recorded as a positive pulse; when the signal enters the excitation threshold range of the trough, it is recorded as a negative pulse; S333: The positive pulse and the negative pulse have the same duration, generating a pulse signal.

2. The DDR3 memory chip integrated circuit testing method based on particle swarm optimization according to claim 1, characterized in that: S1 includes the following steps: S11: Configure the chip reading system to read the model of the chip to be tested; S12: Configuring a power supply module according to the model of the chip to be tested to provide a corresponding power supply environment for the chip to be tested.

3. The DDR3 memory chip integrated circuit testing method based on particle swarm optimization according to claim 1, characterized in that: S2 includes the following steps: S21: Obtain the model of the chip to be tested, and obtain the core unit corresponding to each pin of the chip based on the model of the chip to be tested; S22: pins corresponding to the same core unit are treated as an information group; S23: receiving, for each information group, an original signal generated by each pin after power is applied; S24: Collect the original signal of each information group and use all the original signals as feedback signals.

4. The DDR3 memory chip integrated circuit testing method based on particle swarm optimization according to claim 1, characterized in that: S4 includes the following steps: S41: Send the pulse signal to the positive pulse counter, and generate 1 positive counting information when a positive pulse is received; S42: Send the pulse signal to the negative pulse counter, and generate 1 negative counting information when a negative pulse is received; S43: Send the pulse signal to the pulse change counter, and generate 1 change count information when b pulse signals change direction; S44: All positive count information, all negative count information, and all conversion count information are used as frequency information.

5. The DDR3 memory chip integrated circuit testing method based on particle swarm optimization according to claim 4, characterized in that: S5 includes the following steps: S51: Obtain frequency information of each information group, and establish a database of frequency information, operating voltage, and performance level for each information group; S52: Using the frequency information and the operating voltage as prediction data and the performance level as label data, a corresponding relationship between the prediction data and the label data is established based on the data collected in the database, and a relationship correspondence vector is generated; S53: Collect the frequency information and operating voltage of the chip to be tested as prediction data, extract the most corresponding label data from the database based on the particle swarm algorithm, use the label data as the performance level of the chip to be tested, and generate evaluation parameters according to the performance levels of all information groups.

6. The DDR3 memory chip integrated circuit testing method based on particle swarm optimization according to claim 5, characterized in that: S53 includes the following steps: S531: Randomly generate m particles x in a two-dimensional plane i =(H` i , V` i ), (H` i , V` i ) represents the position of the i-th particle in the two-dimensional plane; S532: Setting the fitness function F and calculating the fitness value of the spectrum to be measured; ； Among them, x i represents the position of the i-th particle in the two-dimensional plane, represents the comprehensive difference of features, Indicates the absolute deviation of the operating voltage; ； ； Indicates the operating voltage of the chip under test, represents the working voltage of the i-th particle recorded in the database, Indicates the first dimension value of the chip to be tested, represents the first dimension value of the i-th particle recorded in the database; λ1 and λ2 represent the first weight parameter and the second weight parameter respectively; S533: For each particle i, compare the fitness of the current position, traverse all particles, select the individual optimal position with the highest fitness, and use the individual optimal position as the global optimal position; Each particle is updated as follows: ； in, represents the velocity vector of the i-th particle, represents the inertia weight, and denote the first learning coefficient and the second learning coefficient respectively, 、 as well as Represent the first random factor, the second random factor and the third random factor respectively; represents the individual historical optimal position of particle i; represents the historical optimal position of the group, Indicates the nearest closed plane center. The closed plane is the plane formed by connecting the points of the predicted data corresponding to each performance level in the database in two-dimensional space. represents the updated position of the i-th particle in the two-dimensional plane; S534: When the termination condition is met, the update is stopped and the particle with the highest fitness value is selected; the termination condition is that the number of iterations reaches the maximum value, or the fitness change is less than a preset threshold.

7. A DDR3 memory chip integrated circuit testing system based on particle swarm optimization algorithm, characterized in that: The performance of a memory chip is tested by using the DDR3 memory chip integrated circuit testing method based on the particle swarm algorithm described in any one of claims 1 to 6.

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