Memory bank test method and test machine

Abstract

The invention relates to the technical field of memory bank testing, and provides a memory bank testing method and a testing machine. The method comprises the following steps: placing a memory bank to be tested on a parallel test station of a test machine; electrically contacting a golden finger of the memory bank to be tested through a golden finger crimping mechanism; performing a multi-physics field coupling test on the to-be-tested memory bank; and predicting the service life of the memory bank to be detected through a time sequence neural network model in combination with an attention mechanism, performing unsupervised anomaly detection on the memory bank to be detected through an isolated forest model, and adaptively adjusting an anomaly threshold to identify the defect of the memory bank to be detected. According to the invention, the performance of the memory bank can be comprehensively evaluated, and the recognition capability of potential defects of the memory bank and the accuracy of life prediction under complex operation conditions are remarkably improved.

Description

Technical Field

[0001] The present application relates specifically to the field of semiconductor memory testing technology, and more specifically to a comprehensive testing method for dynamic random access memory (DRAM) modules (commonly referred to as memory sticks) and a dedicated testing machine for executing the method. Background Art

[0002] Dynamic random access memory (DRAM) memory sticks, as core components of modern computing systems, are widely used in various electronic devices such as personal computers, servers, mobile devices, embedded systems, and high-performance computing (HPC) clusters. Their performance and long-term reliability have a decisive impact on the operating efficiency, data processing capabilities, and user experience of the entire system. With the continuous advancement of semiconductor manufacturing processes, the storage density of memory sticks continues to increase (for example, from DDR3 to DDR4 to DDR5 and higher generations), the operating frequency is increasing (for example, from 1600MT / s to 6400MT / s or even higher), and the operating voltage is constantly decreasing. This makes memory sticks more sensitive to changes in the working environment, minor defects in the manufacturing process, and aging effects caused by long-term operation. Therefore, comprehensive, efficient, and accurate quality inspection and reliability assessment before the memory sticks leave the factory is crucial to ensuring the yield of the final product, reducing the early failure rate, and meeting the requirements of stringent application scenarios (such as data centers, autonomous driving, aerospace, etc.).

[0003] Traditional memory module testing methods can be roughly divided into several categories, including functional testing, parameter testing, and stress testing, based on their testing purposes and methods.

[0004] Functional testing is the most basic type of test, and its main purpose is to verify whether the memory stick can correctly perform basic operations such as reading, writing, and refreshing in accordance with its design specifications. For example, invention patent application publication number CN102339650A discloses a memory stick test device and test method, wherein the memory stick test device includes a memory stick interface, a test control unit, and a functional test unit, wherein the functional test unit is connected to the memory stick interface, and the test control unit is connected to the functional test unit. The functional test unit includes at least one of a power supply bias test module, a memory stress test module, and a signal lead-out test module. This type of test usually uses a specific test vector or algorithm (such as March C-, March B, Walking 1 / 0, etc.) to traverse the memory cell array to check whether there are errors at the logical function level such as stuck-at faults, coupling faults, and address decoding faults. Typical functional test equipment, such as automatic test equipment (ATE), is typically equipped with high-speed pattern generators and data comparators, enabling rapid execution of these test algorithms at room temperature and pressure. However, a limitation of functional testing is that it primarily focuses on the logical correctness of memory modules under ideal conditions and fails to expose performance degradation, intermittent failures, or potential reliability issues that may arise in complex, real-world operating environments. For example, some memory modules that pass functional testing at room temperature may exhibit data errors or increased latency when tested at high temperatures or under vibration.

[0005] Parametric testing focuses on measuring whether the key electrical parameters of a memory module comply with industry standards such as JEDEC (Joint Electron Device Engineering Council) or manufacturer-specified specifications. These parameters typically include: upper and lower limits of operating voltage (Vdd / Vddq), high and low levels of input / output signals (Vih / Vil, Voh / Vol), signal setup time (Setup Time) and hold time (Hold Time), clock cycle (tCK), access time (tAC, tCAC), refresh cycle (tRFC, tREFI), power consumption (IDD courants such as IDD0, IDD2N, IDD3N, IDD4W / R, IDD5B, IDD6, etc.). Parametric testing is also typically performed with ATE, using precise voltage / current sources and measurement units (VMUs). For example, invention patent application publication number CN103035301A discloses a test device and method for memory module power supply performance parameters. The testing equipment includes a main circuit board, a connector, and a test module. The connector and the test module are disposed on the main circuit board. The test module is electrically connected to the main circuit board via the connector. The main circuit board, the connector, and the test module cooperate to test the power performance parameters of a memory stick to be tested. The connector includes a plurality of connection terminals, including at least one first power terminal, which is used to connect to at least one power pin corresponding to the memory stick. The test module is used to test the power performance parameters of the memory stick corresponding to the at least one first power terminal. Parameter testing can more carefully evaluate the electrical characteristic margins of a memory stick. However, these tests are mostly performed under standard or limited environmental corner cases (such as typical voltage / high temperature, low voltage / low temperature, etc.), and cannot fully reflect the actual performance of a memory stick in a dynamically changing, multi-stress superimposed environment. For example, a single high-temperature test may not reveal parameter drift caused by solder joint fatigue or unstable connector contact under the combined effects of vibration and high temperature.

[0006] Stress testing aims to accelerate the exposure of potential defects in memory modules and assess their long-term reliability. Common stress tests include burn-in and highly accelerated life testing (HALT) / highly accelerated stress screening (HASS).

[0007] Burn-in testing usually involves placing the memory stick at a high temperature (e.g., 85°C to 125°C) and rated or slightly higher voltage, and running it continuously for a period of time (several hours to tens of hours) in order to screen out products with a tendency to early failure (Infant Mortality). For example, invention patent application publication number CN119694380A discloses an energy-saving memory stick burn-in test method, apparatus, equipment, and medium relating to the field of memory stick testing technology. The method includes: determining test parameters for the memory stick burn-in test, the test parameters including test duration and test temperature; setting the temperature of the memory stick burn-in test device to the test temperature; when the temperature of the memory stick burn-in test device reaches the test temperature, controlling the temperature of the memory stick burn-in test device to maintain at the test temperature, and starting timing; when the timing time is equal to the test duration, turning off the memory stick burn-in test device, and ending the memory stick burn-in test for the memory stick. Burn-in testing is effective in eliminating early failures caused by process defects, but its testing time is long, the cost is high, and the type of stress applied is single (mainly thermal stress). It does not cover failure modes caused by other factors such as mechanical stress and electromagnetic interference.

[0008] HALT / HASS uses more severe, gradually increasing stress (such as rapid temperature changes, wide-spectrum random vibrations, voltage shocks, etc.) to quickly stimulate potential design and process defects in the product and determine its operating limits (Operating Limits) and destructive limits (Destruct Limits). HALT is mainly used for product design verification and reliability improvement in the R&D stage, while HASS is used for product screening in the production stage. Although HALT / HASS introduces composite stress, its main purpose is "stimulation" rather than "simulation." The stress level applied during the test is usually far higher than the actual use environment of the product, and it is difficult to accurately simulate complex scenarios where multiple physical fields (such as force, heat, electricity, and magnetism) exist and interact simultaneously. In addition, the data generated by HALT / HASS tests are usually used for qualitative judgment or to determine stress boundaries, and have limited ability to accurately predict the remaining useful life (RUL) of memory sticks in specific actual application scenarios.

[0009] In summary, current memory module testing technology faces the following core pain points and challenges: Environmental simulation lacks authenticity: Traditional testing methods are mostly conducted under single, static, or limited combinations of environmental conditions. These methods struggle to replicate the complex stress environments that memory modules encounter in real-world applications (such as automotive electronics, industrial control, and outdoor equipment), including mechanical vibration (from engines, road bumps, and fans), electromagnetic interference (from processors, power modules, wireless communications, and motors), and rapid temperature changes (from power on / off, load fluctuations, and environmental fluctuations). This simulation distortion can lead to misjudgments of the memory module's true reliability, causing some products that perform well in standard testing to fail prematurely in real-world use.

[0010] Lack of lifespan prediction capabilities: Memory stick performance gradually degrades with age and accumulated stress, ultimately leading to failure. Traditional testing methods primarily focus on pass / fail functional verification or parameter measurement, lacking effective means to assess the memory stick's state of health (SoH) and predict its remaining useful life (RUL) under specific operating conditions. This makes it difficult for users to perform predictive maintenance, potentially leading to unplanned downtime of critical systems due to memory failures, resulting in significant losses. Accurate RUL prediction is particularly important for applications requiring high reliability.

[0011] Difficulty detecting early defects and intermittent faults: Certain manufacturing defects or early performance degradation may manifest as very subtle signal anomalies (such as nanosecond-level signal delay fluctuations or slight milliwatt-level power consumption increases) or intermittent faults that only occur under specific stress combinations. Traditional detection methods based on threshold comparisons are often insensitive to these "soft faults" or early signs, making them prone to missed detection. Furthermore, due to the lack of effective online monitoring and intelligent analysis methods, these abnormal signals are often drowned out by the noise in the test data.

[0012] Test efficiency and cost pressures: As memory module capacity and speed increase, the time required to complete a comprehensive test suite also increases. Traditional single-station serial testing methods are no longer able to meet the throughput requirements of large-scale production. While parallel testing solutions have been used, further improving test efficiency and reducing per-chip test costs while ensuring test coverage and depth remain ongoing concerns in the industry. Energy consumption is particularly important for reliability tests that require prolonged stress application, such as burn-in tests.

[0013] Low data utilization and lack of intelligent analysis: Traditional testing processes generate large amounts of raw data, but this data is often used only for simple pass / fail determinations. The underlying information, such as subtle changes in memory module performance, potential correlations, and degradation trends, is not fully mined and utilized. Advanced data analysis methods (such as machine learning and deep learning) are lacking to extract effective features from high-dimensional, time-series test data for deeper fault diagnosis, performance evaluation, and lifespan prediction.

[0014] Therefore, in the face of increasingly stringent requirements for memory stick quality and reliability, as well as the need for intelligent and predictive maintenance in modern computing systems, there is an urgent need for an innovative memory stick testing technology solution that can: (1) realistically simulate the complex working environment of multi-physics coupling; (2) accurately predict the remaining service life of the memory stick under specific working conditions; (3) sensitively detect the weak signal characteristics of early defects and intermittent failures; (4) efficiently execute tests in parallel to improve throughput; (5) intelligently analyze test data to achieve deeper insights; and (6) consider energy conservation and consumption reduction during the testing process. This application aims to propose such a comprehensive solution. Summary of the Invention

[0015] The main purpose of this application is to provide a memory stick testing method and testing machine. The main advancement lies in the integration of parallel testing architecture, non-insertionary crimping contact technology, precise and controllable multi-physics field coupling environment simulation, life prediction model based on deep learning, anomaly detection algorithm based on unsupervised learning, and intelligent energy-saving strategy based on reinforcement learning. It can truly simulate the complex working environment of multi-physics field coupling, accurately predict the remaining service life of the memory stick under specific working conditions, and sensitively detect the weak signal characteristics of early defects and intermittent failures.

[0016] The main purpose of this application is achieved through the following technical solutions: A memory module testing method is proposed, comprising the following steps: S1. Place a memory stick to be tested on a parallel testing station of a test machine, wherein the memory stick to be tested includes a carrier board, a gold finger provided on one side of the carrier board, and a volatile memory chip mounted on the carrier board; S2, electrically contacting the gold finger of the memory stick to be tested through a gold finger pressing mechanism; S3. Performing a multi-physics coupling test on the memory module to be tested to obtain test data, signal delay, and power consumption fluctuation of the memory module to be tested, wherein the multi-physics coupling test includes applying mechanical vibration, simulating an electromagnetic interference environment, and applying temperature changes; S4. Modeling the test data using a temporal neural network model combined with an attention mechanism to predict the lifespan of the memory stick to be tested; S5, performing unsupervised anomaly detection on the memory bar to be tested according to the signal delay and the power consumption fluctuation using an isolation forest model, and adaptively adjusting an anomaly threshold to identify defects of the memory bar to be tested.

[0017] The technical solution using the above method improves test throughput through parallel testing and provides sufficient data for the AI ​​model. It reduces contact noise and improves signal quality through non-pluggable gold finger pressing. It simulates the operating status of memory sticks in actual complex environments and obtains diversified data through multi-physical field coupling testing. It combines timing neural networks with attention mechanisms to model timing data including voltage, frequency, temperature, humidity, etc. to achieve accurate life prediction. It also uses the isolation forest model to perform unsupervised anomaly detection and adaptive threshold adjustment on signal delay and power consumption fluctuations, thereby comprehensively evaluating memory stick performance and significantly improving the ability to identify potential defects of memory sticks and the accuracy of life prediction under complex operating conditions.

[0018] The preferred method example of the present application can be further configured as follows: the parallel test station in step S1 is located in an environmental simulation chamber, and the environmental simulation chamber is provided with a vibration table, an electromagnetic interference source and a temperature change module; in step S3, mechanical vibration is applied through the vibration table, the electromagnetic interference environment is simulated through the electromagnetic interference source, and temperature change is applied through the temperature change module.

[0019] By adopting the above-mentioned preferred technical features, the parallel test station can be set up in an environmental simulation chamber equipped with specific equipment (vibration table, electromagnetic interference source, temperature change module), providing a specific physical environment and implementation means for realizing the multi-physical field coupling test (mechanical field, electromagnetic field, thermodynamic field), ensuring the stability and controllability of the test conditions, so as to reliably simulate the complex stress environment of the memory stick during transportation or actual work.

[0020] The preferred method example of this application can be further configured as follows: Step S2 includes: The probe card electrically contacts the gold fingers of the memory bar to be tested from above, and the spring probe electrically contacts the gold fingers of the memory bar to be tested from below.

[0021] By adopting the above-mentioned preferred technical features, the specific method of electrical contact between the gold finger crimping mechanism and the gold finger of the memory stick to be tested can be clarified. Regardless of upper contact, lower contact or upper and lower combined contact, a stable and reliable non-insertion electrical connection can be achieved; in particular, the use of upper and lower separate contact methods helps to physically separate the test contacts, which may further improve signal integrity and ensure the accuracy of test data.

[0022] The present application can be further configured in a preferred method example as follows: the test data includes the voltage, frequency, temperature and humidity of the memory bar to be tested; in step S4, the voltage, frequency, temperature and humidity of the memory bar to be tested (10) are input into the timing neural network model, and the multi-parameter timing dependency relationship between the voltage, frequency, temperature and humidity of the memory bar to be tested (10) is extracted in combination with the attention mechanism to predict the life of the memory bar to be tested (10).

[0023] By adopting the above-mentioned preferred technical features, the specific test data types used for life prediction modeling can be clarified. These parameters (voltage, frequency, temperature, humidity) are key physical quantities that affect the performance and life of memory sticks. Using them as input features of the timing neural network model can provide the model with information closely related to the memory stick status and aging process, which helps to improve the accuracy and reliability of the life prediction model.

[0024] The preferred method example of this application can be further configured as follows: Step S4 includes: S41. Using a temporal neural network model based on a long short-term memory network, input the test data and control the information flow through a gating mechanism. The temporal neural network model based on a long short-term memory network is expressed as follows: f t =σ(W f ·[h t-1 ,x t ]+b f ), i t =σ(W i ·[h t-1 ,x t ]+b i ), o t =σ(W o ·[h t-1 ,x t ]+b o ), h t =o t ☉tanh(C t ), where f t Represents the forget gate, which is used to determine the previous memory unit C t-1 Information retained in; i t represents the input gating signal, Represents a candidate memory unit, i t and Used as an input gate to control the input feature vector x t For memory unit C t Updates;t Represents the output gate, which is used to determine the current hidden state h t Output content of W f 、W i 、W C 、W o Represents the weight matrices of the forget gate, input gating signal, candidate memory unit, and output gate respectively; b f 、b i 、b C 、b o Respectively represent the bias items of the forget gate, input gating signal, candidate memory unit, and output gate; x t represents the input feature vector of the current time step t, which is determined according to the test data; t-1 represents the hidden state of the previous time step, C t Represents a memory unit, σ represents a Sigmoid function, and ⊙ represents element-wise multiplication; S42, introducing the time step attention weight α into the temporal neural network model based on the long short-term memory network t To enhance the ability to extract time series features, it is expressed as follows: α t =Softmax(v T tanh(W a h t +b a )), Among them, W a represents the attention weight matrix, b a represents the attention bias term, v T represents the attention weight vector, s represents the context vector, which is used to weight the hidden state h of all time steps t , T represents the total time step; Step S43: Input the context vector s into the fully connected network and output the lifespan percentage R of the memory stick to be tested, which is expressed as the following formula: R=Sigmoid(W r ·s+b r ) Among them, W r represents the output layer weight matrix, b r Represents the output layer bias term.

[0025] By adopting the above-mentioned preferred technical features, the gating mechanism of the long short-term memory network (LSTM) can be used to effectively capture the long-term dependencies of test data (such as voltage, temperature, etc.) over time. By introducing the attention mechanism, the model can automatically focus on time steps or events (such as high temperature, voltage drop, etc.) that have a more critical impact on life prediction. Combined with the normalized life percentage output by the fully connected layer, the remaining life of the memory stick under complex conditions can be predicted more accurately and robustly, effectively solving the prediction problem under the influence of multi-parameter coupling.

[0026] The preferred method example of this application can be further configured as follows: Step S4 also includes: Step S44: train the temporal neural network model, using weighted mean square error as the loss function and using AdamW optimizer to suppress overfitting. The loss function is expressed as follows: in, represents the loss function, represents the number of memory sticks to be tested in the training batch, w i represents the weight parameter of the i-th memory bank to be tested, R i Indicates the actual remaining life percentage of the i-th memory module under test, Indicates the predicted remaining lifespan percentage of the i-th memory module to be tested.

[0027] By adopting the above-mentioned preferred technical features and using the weighted mean square error (WMSE) as the loss function, it is possible to give higher attention to key samples such as early failure samples during model training, effectively deal with the sample imbalance problem, and improve the model's prediction accuracy for important situations; at the same time, the AdamW optimizer is used to decouple weight decay from gradient update, which can improve the stability of the training process, effectively suppress model overfitting, enhance the model's generalization ability on unseen data, and further ensure the accuracy and reliability of life prediction.

[0028] The preferred method example of this application can be further configured as follows: Step S5 includes: dividing the data stream containing the signal delay and the power consumption fluctuation into a plurality of sliding windows, and extracting statistical features of the signal delay and the power consumption fluctuation from the sliding windows; Constructing an isolation tree, wherein a feature subset and a partition value of the statistical feature are randomly selected, and the data is recursively partitioned until the sample is isolated; The average of multiple isolated trees is taken to calculate the anomaly score of the sample x containing the signal delay or the power consumption fluctuation, which is expressed as the following formula: Where S(x) represents the anomaly score, h(x) represents the path length of the sample in the isolated tree, E(h(x)) represents the expected value of the path length in multiple isolated trees, and c(n) represents the path length correction term; According to the data distribution in the sliding window, the abnormal threshold T is adaptively adjusted, which is expressed as the following formula: T=μ S +k·σ S , Among them, μ S and σ S They represent the mean and standard deviation of the anomaly score within the sliding window, and k represents the empirical coefficient.

[0029] By adopting the above-mentioned preferred technical features, the isolation forest algorithm can be used to perform unsupervised anomaly detection on features extracted from signal delay and power consumption fluctuation data, eliminating the need to pre-label abnormal data and simplifying the deployment process. By calculating anomaly scores and combining them with anomaly thresholds that are adaptively adjusted based on recent data distribution, potential defects that deviate from normal patterns can be identified efficiently and in real time. At the same time, the adaptive threshold can effectively cope with baseline drift caused by environmental changes or equipment aging, reducing false alarm rates and improving the accuracy and robustness of defect detection.

[0030] The preferred method example of the present application may be further configured as follows: further comprising: S6, an intelligent sleep strategy based on reinforcement learning, dynamically adjusting the power consumption of the test machine according to the test task load, step S6 comprising: S61. Determine the state space, which is expressed as the following formula: s t =(Q queue , P current , T ambient ), Among them, s t Indicates the state of the test machine, Q queue Indicates the queue length to be tested of the test machine, P current Indicates the current power of the test machine, T ambient represents the ambient temperature; S62. Determine the action space, which is expressed as the following formula: a t ∈{Active, Low-Power, Sleep}, Among them, a t Indicates the execution action of the test machine, Active indicates the execution of normal power consumption mode, Low-Power indicates the execution of low power consumption mode, and Sleep indicates the execution of sleep mode; S63, determining the reward function r based on energy consumption and response speed t , expressed as the following formula: r t =-α·P action -β·Delay(a t ), Among them, α and β represent weight coefficients, P action Indicates the power consumption of the test machine's execution action, Delay(a t ) represents the delay caused by switching the execution action of the test machine; S64. Update the intelligent sleep strategy based on a deep Q network algorithm, wherein the Q value is updated by experience replay, the intelligent sleep strategy is optimized, and over-estimation of the Q value is suppressed by a dual network structure of a target network and a prediction network.

[0031] By adopting the above-mentioned preferred technical features and introducing an intelligent sleep strategy based on reinforcement learning (deep Q network), the test machine can make independent decisions to select the appropriate power consumption mode (Active, Low-Power, Sleep) based on real-time status information such as the length of the queue to be tested, current power consumption, and ambient temperature. By optimizing the reward function that balances energy consumption and response speed, the energy consumption of the test machine when idle or under low load can be significantly reduced, thereby achieving energy-saving optimization of the test process.

[0032] The second main purpose of this application is achieved through the following technical solutions: A memory stick tester, used to implement the memory stick test method, the memory stick tester comprising: A test machine body is provided with an environmental simulation chamber for performing a multi-physics coupling test on the memory stick to be tested to obtain test data, signal delay, and power consumption fluctuation of the memory stick to be tested. The multi-physics coupling test includes applying mechanical vibration, simulating an electromagnetic interference environment, and applying temperature changes. The environmental simulation chamber is provided with multiple parallel test stations for placing the memory stick to be tested. The memory stick to be tested includes a carrier board, a gold finger provided on one side of the carrier board, and a volatile memory chip mounted on the carrier board. Each parallel test station is equipped with a gold finger pressing mechanism for electrically contacting the gold finger of the memory stick to be tested. A timing neural network algorithm module and an anomaly detection module are integrated into the test machine body. The timing neural network algorithm module models the test data through a timing neural network model combined with an attention mechanism to predict the life of the memory stick to be tested. The anomaly detection module performs unsupervised anomaly detection on the memory stick to be tested through an isolation forest model based on the signal delay and the power consumption fluctuation. The anomaly detection module also adaptively adjusts the anomaly threshold to identify defects in the memory stick to be tested.

[0033] By adopting the above-mentioned testing machine technical solution, a testing device capable of executing the memory stick testing method is provided. The device realizes high-throughput, multi-physical field coupling environment testing of memory sticks through an integrated environmental simulation chamber (including parallel workstations and multi-physical field application devices), a gold finger pressing mechanism, and a built-in AI algorithm module (timing neural network and anomaly detection). It can also directly perform life prediction and defect identification, thereby improving test efficiency and accuracy, and can comprehensively evaluate the reliability of memory sticks under complex working conditions.

[0034] The preferred testing machine example of the present application can be further configured as follows: the gold finger crimping mechanism includes: a fixing plate having an opening for mounting and fixing the connector; A connector is provided at the opening and is used to establish an electrical connection between a memory stick tester and the memory stick to be tested; the fixing plate and the connector are crimped and installed on a PCB adapter board of the memory stick tester, the connector is electrically connected to the PCB adapter board and electrically contacts the gold fingers of the memory stick to be tested, the connector includes a spring probe and a probe card, the spring probe electrically contacts the gold fingers of the memory stick to be tested from below, and the probe card electrically contacts the gold fingers of the memory stick to be tested from above.

[0035] By adopting the above-mentioned preferred technical features, the specific installation structure of the gold finger crimping mechanism can be clarified. It adopts the method of crimping the fixing plate and the connector on the PCB adapter board. Compared with the traditional welding fixation, the gold finger crimping mechanism can be replaced and maintained more conveniently and quickly when it reaches the end of its service life or needs to be replaced to adapt to different types of memory sticks, thereby improving the flexibility, maintainability and service life of the test equipment.

[0036] In summary, this application includes at least one of the following beneficial technical effects: 1. Parallel testing improves test throughput and provides sufficient data for AI models. A non-pluggable gold finger press-fit method reduces contact noise and improves signal quality. Multi-physics field coupling testing simulates the operating state of memory modules in complex real-world environments and captures diverse data. A time-series neural network and attention mechanism are combined to model time-series data such as voltage, frequency, temperature, and humidity for accurate lifespan prediction. The isolation forest model is used for unsupervised anomaly detection and adaptive threshold adjustment of signal delay and power consumption fluctuations, comprehensively evaluating memory module performance. This significantly improves the ability to identify potential memory module defects and the accuracy of lifespan prediction under complex operating conditions. 2. The gating mechanism of the Long Short-Term Memory (LSTM) network effectively captures the long-term dependencies of test data (such as voltage and temperature) over time. By introducing an attention mechanism, the model automatically focuses on time steps or events (such as high temperatures and voltage drops) that are most critical to lifespan prediction. Combined with the normalized lifespan percentage output by the fully connected layer, this enables more accurate and robust prediction of the remaining lifespan of memory modules under complex conditions, effectively solving the prediction challenge under the influence of multiple parameters. 3. The Isolation Forest algorithm performs unsupervised anomaly detection on features extracted from signal delay and power consumption fluctuation data. This eliminates the need for pre-labeling of anomaly data and simplifies the deployment process. By calculating an anomaly score and combining it with an anomaly threshold that is adaptively adjusted based on recent data distribution, it can efficiently and in real time identify potential defects that deviate from normal patterns. Furthermore, this adaptive threshold effectively addresses baseline drift caused by environmental changes or device aging, reducing false alarm rates and improving the accuracy and robustness of defect detection. 4. An intelligent sleep strategy based on reinforcement learning (deep Q-network) is introduced, enabling the tester to autonomously select the appropriate power consumption mode (Active, Low-Power, Sleep) based on real-time status information such as the test queue length, current power consumption, and ambient temperature. By optimizing the reward function that balances energy consumption and response speed, the tester's energy consumption during idle or low-load periods is significantly reduced, achieving energy-saving optimization during the test process. 5. A test device capable of executing the memory stick testing method is provided. This device utilizes an integrated environmental simulation chamber (including parallel workstations and a multi-physics field application device), a gold finger crimping mechanism, and a built-in AI algorithm module (temporal neural network and anomaly detection) to enable high-throughput, multi-physics field coupled testing of memory sticks. It can also directly predict lifespan and identify defects, thereby improving test efficiency and accuracy and enabling comprehensive evaluation of memory stick reliability under complex operating conditions. 6. The gold finger crimping mechanism is installed on the PCB adapter board by crimping the fixing plate and connector. Compared with traditional soldering fixation, the gold finger crimping mechanism can be replaced and maintained more conveniently and quickly when it reaches the end of its service life or needs to be replaced to adapt to different types of memory modules, thereby improving the flexibility, maintainability and service life of the test equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A schematic diagram illustrating the main steps of a memory stick testing method according to an embodiment of the present application is shown; Figure 2 A schematic structural diagram of a memory module to be tested according to an embodiment of the present application is shown; Figure 3A schematic structural diagram of a memory stick testing machine according to an embodiment of the present application is shown; Figure 4 A schematic diagram illustrating the internal structure of an environmental simulation chamber of a memory stick testing machine according to an embodiment of the present application is shown; Figure 5 A schematic structural diagram of a gold finger crimping mechanism according to an embodiment of the present application is shown; Figure 6 Draw Figure 1 Schematic diagram of the flow of subordinate steps of the main step S4; Figure 7 Draw Figure 1 Schematic diagram of the flow of subordinate steps of the main step S5; Figure 8 Draw Figure 1 Schematic diagram of the flow of subordinate steps of the main step S6; Figure 9 A block diagram illustrating an artificial intelligence algorithm module according to an embodiment of the present application is shown.

[0038] Explanation of the accompanying symbols: 10. Memory stick to be tested; 11. Carrier board; 12. Gold finger; 13. Volatile memory chip; 20. Test machine; 21. Test machine body; 22. Environmental simulation chamber; 22a. Vibration table; 22b. Electromagnetic interference source; 22c. Temperature change module; 23. Display interface; 24. Parallel test station; 25. PCB adapter board; 30. Gold finger pressing mechanism; 31. Fixing plate; 31a. Opening; 32. Connector; 40. Artificial intelligence algorithm module; 41. Temporal neural network algorithm module; 42. Anomaly detection module; 43. Intelligent sleep module. DETAILED DESCRIPTION

[0039] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments for understanding the inventive concept of the present invention, and cannot represent all embodiments, nor are they interpreted as the only embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field on the premise of understanding the inventive concept of the present invention are within the scope of protection of the present invention.

[0040] It should be noted that if any embodiment of the present invention involves directional indications (such as up, down, left, right, front, back, etc.), such directional indications are only used to explain the relative positional relationship and movement of various components in a specific posture. If the specific posture changes, the directional indications will also change accordingly. To facilitate understanding of the technical solution of the present invention, a memory stick testing method and testing machine of the present invention are further described and explained below, but they are not intended to limit the scope of protection of the present invention.

[0041] The accompanying drawings illustrate only the common features of the various embodiments. Differences or distinctions are described in separate text or presented in comparison with the drawings. Therefore, based on the characteristics of the industry and the nature of the technology, those skilled in the art should correctly and reasonably understand and determine whether individual technical features described below, or any combination thereof, represent the same embodiment, or whether mutually exclusive technical features can only represent different variations.

[0042] The embodiments of the present application focus particularly on memory bar reliability assessment, remaining useful life (RUL) prediction, and online, unsupervised detection technology for early defects in a simulated real-world complex stress environment.

[0043] Reference Figure 1 A memory stick testing method disclosed in an embodiment of the present application includes main steps S1-S6, and S1-S6 of the method are described as follows.

[0044] Regarding the main step S1, a plurality of memory modules 10 to be tested are placed on a plurality of parallel testing stations 24 of a testing machine 20. Figure 2 The memory module 10 to be tested includes a carrier board 11, a gold finger 12 provided on one side of the carrier board 11, and a volatile memory chip 13 mounted on the carrier board 11. Figure 3 and Figure 4 The test machine 20 includes a test machine body 21, an environmental simulation chamber 22 and a display interface 23, wherein a plurality of parallel test stations 24 are located in the environmental simulation chamber 22 for placing the memory stick 10 to be tested.

[0045] Regarding the main step S2, the gold finger pressing mechanism 30 electrically contacts the gold finger 12 of the memory module 10 to be tested. Figure 5 The gold finger crimping mechanism 30 includes a fixing plate 31 and a connector 32. The fixing plate 31 has an opening 31a, and the connector 32 is disposed at the opening 31a. The fixing plate 31 and the connector 32 are crimped and mounted on the PCB (printed circuit board) adapter plate 25 of the tester 20. The connector 32 is electrically connected to the PCB adapter plate 25 of the tester 20 and electrically contacts the gold fingers 12 of the memory module 10 under test.

[0046] Compared with the related art in which the adapter is welded and fixed on the PCB adapter board 25 of the test machine 20, the gold finger crimping mechanism 30 can be easily replaced when it reaches the end of its service life by crimping the fixing plate 31 and the connector 32 on the PCB adapter board 25 of the test machine 20, or different gold finger crimping mechanisms 30 can be replaced according to different types of the memory sticks 10 to be tested.

[0047] For reference Figure 5 , the connector 32 may include a spring probe that electrically contacts the gold finger 12 of the memory bar 10 under test from the bottom of the memory bar 10 under test. Optionally, the connector 32 may include a probe card that electrically contacts the gold finger 12 of the memory bar 10 under test from the top of the memory bar 10 under test. In a preferred method example, the connector 32 may include a spring probe and a probe card, wherein the spring probe electrically contacts the lower area of ​​the gold finger 12 of the memory bar 10 under test from the bottom of the memory bar 10 under test, and the probe card electrically contacts the upper area of ​​the gold finger 12 of the memory bar 10 under test from the top of the memory bar 10 under test, so as to physically separate the test contacts of the gold finger 12 of the memory bar 10 under test.

[0048] In main step S3, a multi-physics coupling test is performed on the memory module 10 to obtain test data, signal delay, and power consumption fluctuations of the memory module 10. The multi-physics coupling test includes applying mechanical vibration, simulating an electromagnetic interference environment, and applying temperature changes. The test data includes the voltage, frequency, temperature, and humidity of the memory module 10.

[0049] For reference Figure 4 , the environmental simulation chamber 22 is provided with a vibration table 22a, an electromagnetic interference source 22b and a temperature change module 22c. The vibration table 22a can use an electric vibrator to achieve mechanical vibration with a frequency range of 5-2000Hz. The electric vibrator is installed at the bottom of the environmental simulation chamber 22 through a fixed bracket to ensure that the vibration table 22a can work stably. The electromagnetic interference source 22b can use a signal generator and an antenna combination to achieve electromagnetic interference environment simulation. The signal generator is connected to the antenna through a wire, and the electromagnetic interference intensity and frequency can be adjusted as needed. The temperature change module 22c can use a refrigerant circulation system to achieve rapid temperature changes with a temperature change rate of not less than 10°C / min. The refrigerant circulation system includes a compressor, a condenser, an evaporator and an expansion valve. The components are connected by pipes to form a closed circulation loop.

[0050] The vibration table 22a, the electromagnetic interference source 22b and the temperature change module 22c work in coordination to ensure that multi-physics field coupling testing can be achieved during the test process. Here, multi-physics field coupling testing refers to integrating a variety of different physical environmental factors or stress fields into a test environment for coupling testing. The multi-physics fields include mechanical fields (Mechanical Field), electromagnetic fields (Electromagnetic Field) and thermodynamic fields (Thermodynamic Field). The mechanical field includes mechanical stress (5-2000Hz) applied by the vibration table 22a to simulate the vibration environment during transportation or work. The electromagnetic field includes simulating the working conditions of the equipment in a complex electromagnetic environment through the electromagnetic interference source 22b. The thermodynamic field includes the rapid temperature change (≥10℃ / min, ranging from -20℃ to +85℃) achieved by the temperature change module 22c and the thermal stress generated thereby.

[0051] Regarding the main step S4, the test data is modeled by combining a temporal neural network model with an attention mechanism to predict the life of the memory stick 10 to be tested. Figure 6 , the main step S4 includes subordinate steps S41-S44, and S41-S44 of this step are described as follows.

[0052] Regarding the subordinate step S41, a temporal neural network model based on a long short-term memory network (LSTM) is used to input the test data and control the flow of information through a gating mechanism. The temporal neural network model based on the long short-term memory network is expressed as follows: f t =σ(W f ·[h t-1 ,x t ]+b f ), i t =σ(W i ·[h t-1 ,x t ]+b i ), o t =σ(W o ·[h t-1 ,x t ]+b o ), h t =o t ☉tanh(C t ), where f t Represents the forget gate, which is used to determine the previous memory unit C t-1The information retained in the system (e.g. long-term irrelevant temperature fluctuations can be ignored). t represents the input gating signal, Represents a candidate memory unit, i t and Used as an input gate to control the input feature vector x t For memory unit C t Updates (e.g. recording voltage anomalies caused by high temperature). t Represents the output gate, which is used to determine the current hidden state h t Output content (for example, outputting time series features related to life prediction). Hidden state h t is the final output, passed to the next time step or used for prediction, capturing long-term dependencies (such as the cumulative effect of continuous high temperature on memory life). f 、W i 、W C 、W o is the weight matrix, corresponding to the parameters of the forget gate, input gating signal, candidate memory unit, and output gate. f 、b i 、b C 、b o Is the bias term used to adjust the activation threshold of the forget gate, input gating signal, candidate memory unit, and output gate. t h represents the input feature vector at the current time step t, which is determined based on the test data (e.g. voltage, frequency, temperature, humidity). t-1 Represents the hidden state of the previous time step, used to transmit historical information. t Represents a memory unit. σ represents the Sigmoid function, which is used to compress the input to the interval [0, 1] and represents the degree of gate switching. ⊙ represents element-by-element multiplication, which is used to combine the gate signal with the memory unit.

[0053] Regarding the subordinate step S42, the time step attention weight α is introduced into the temporal neural network model based on the long short-term memory network. t To enhance the ability to extract time series features, it is expressed as follows: α t =Softmax(v T tanh(W a h t +b a )) Among them, α t W represents the attention weight of time step t, indicating the importance of this time step to the prediction. a Represents the attention weight matrix, which is used to transform the hidden state h t Mapped to high-dimensional space. b aRepresents the attention bias term, which is used to adjust the baseline of attention calculation. T represents the attention weight vector, which is used to extract the key time step. s represents the context vector, which is used to weight the hidden state h of all time steps. t . T represents the total time step.

[0054] By introducing α t Attention weight distribution can highlight key periods (such as voltage drops in high temperature and high humidity environments) and suppress irrelevant noise. The context vector s can integrate key timing information to focus on features, thereby improving the accuracy of life prediction (for example, abnormal signals at 85°C have a greater impact on life). By combining LSTM and attention mechanism, the parameter W f 、W i , α t Together, they can realize time series feature extraction and key period focusing, and solve the problem of multi-parameter coupling prediction.

[0055] Regarding the subordinate step S43, the context vector s is input into the fully connected network, and the life percentage R of the memory stick 10 to be tested is output, which is expressed as the following formula: R=Sigmoid(W r ·s+b r ) Among them, W r Represents the output layer weight matrix, which is used to map the context vector s to the lifespan prediction value. r Represents the output layer bias, used to adjust the prediction baseline. R represents the lifespan percentage (0-1). Using a sigmoid function to normalize the output, constraining the predicted value to the [0, 1] range, this provides a visual representation of the remaining lifespan (for example, R = 0.8 indicates 80% lifespan remaining), allowing for direct guidance on memory module production line replacement or maintenance strategies.

[0056] Regarding the subordinate step S44, the temporal neural network model is trained, wherein the weighted mean square error (WMSE) is used as the loss function The AdamW optimizer is used to suppress overfitting.

[0057] The loss function It is expressed as the following formula: in, Indicates the number of memory banks to be tested in the training batch, which is used to standardize the loss value to avoid the difference in loss magnitude caused by different sample numbers. i represents the weight parameter of the i-th memory bank to be tested, which is used to dynamically adjust the weight according to the importance of the sample. The weight of a normal sample is set to w i= 1.0 to avoid overfitting noise, and for early failure samples (such as remaining life R i <0.2) give higher weight (e.g. w i =2.0), so that the temporal neural network model focuses on vulnerable samples. i Indicates the actual remaining lifespan percentage of the i-th memory module under test. represents the predicted remaining lifespan percentage of the i-th memory module under test, obtained through the output of the fully connected network. By adjusting the weights, the loss function can improve the prediction accuracy of the temporal neural network model for key samples (such as early failures) and balance the class imbalance problem (for example, when normal samples far outnumber failure samples).

[0058] The parameter update rule of the AdamW optimizer can be expressed as follows: Among them, θ t Represents model parameters (such as the weight matrix W f 、W i η represents the learning rate (e.g. 0.001), which is used to control the parameter update step size. t and v t represents the exponential moving average estimate of the first moment (mean) and the second moment (variance). ∈ represents a numerical stability constant (e.g. 10 -8 ), used to prevent the denominator from being zero. λ represents the weight decay coefficient (e.g. 0.01), which is used for regularization. The AdamW optimizer can separate weight decay (L2 regularization) from gradient update to avoid the coupling of adaptive learning rate and weight decay, thus improving training stability. At the same time, by increasing λθ t The term directly constrains the parameter amplitude, which can avoid overfitting and enhance the generalization ability of the model.

[0059] Main step S4 solves the problem of insufficient sensitivity of traditional mean square error (MSE) to key samples by introducing dynamic weights in memory life prediction. The AdamW optimizer performs more stably in complex time series data (such as multi-physics field coupling test data), and the model convergence speed is improved by about 15%. By combining WMSE with AdamW and verifying it on public data sets (such as Backblaze hard drive life data), the model prediction error (MAE) is reduced to 7.5%. Main step S4 fully considers the particularity of memory test scenarios (such as sample imbalance and complex time series dependencies) in the selection of loss functions and optimizers, ensuring the high accuracy and robustness of the model.

[0060] Regarding the main step S5, an unsupervised anomaly detection is performed on the memory module 10 to be tested based on the signal delay and the power consumption fluctuation using an isolation forest model, and an anomaly threshold is adaptively adjusted to identify defects of the memory module 10 to be tested. Figure 7 , the main step S5 includes subordinate steps S51-S54, and S51-S54 of this step are described as follows.

[0061] Regarding the subordinate step S51 , the data stream containing the signal delay and the power consumption fluctuation is divided into a plurality of sliding windows, and statistical features of the signal delay and the power consumption fluctuation are extracted from the sliding windows.

[0062] The signal delay is the response time of the memory stick 10 to be tested in the read and write operations (such as nanosecond delay), which may include timing fluctuations or sudden delay increases. The power consumption fluctuation is the power change of the memory stick under different loads (such as standby power consumption, peak power consumption), in which it is necessary to capture abnormal power consumption modes (such as continuous high power consumption or sudden drop). After collecting the signal delay and the power consumption fluctuation, they are pre-processed, and the data stream containing the signal delay and the power consumption fluctuation is divided into sliding windows. The real-time data stream can be divided into 1-second windows, and each window contains multiple samples (for example, 1000 samples per second). Statistical features are extracted from each window. The statistical features of the signal delay may include mean, variance, maximum value, rise time and peak value. The statistical features of the power consumption fluctuation may include average power, power standard deviation, instantaneous peak value, and valley value difference. The statistical features of the signal delay and power consumption fluctuation are combined into a multi-dimensional input vector, for example: input vector = [delay mean, delay variance, delay peak value, power consumption mean, power consumption standard deviation]. Interaction features can also be constructed, for example, by using the ratio of delay to power consumption (mean delay / mean power consumption) to capture the correlation between the two.

[0063] Regarding subordinate step S52, an isolation tree is constructed, wherein a feature subset and a partition value of the statistical feature are randomly selected, and the data is recursively partitioned until the sample is isolated. In the process of constructing the isolation tree, historical normal data (memory bar test data without known defects) is used to train the isolation forest model. During the training process, a feature subset (for example, two features are selected at a time) is randomly selected, and a partition value is randomly selected, and the data is recursively partitioned until the sample is isolated. The path length is recorded, where normal samples require more partitioning steps (longer paths) due to their concentrated distribution, while abnormal samples have shorter paths due to their deviated distribution.

[0064] Regarding the subordinate step S53, the average of multiple isolated trees is taken to calculate the anomaly score of the sample x containing the signal delay or the power consumption fluctuation. The anomaly score S(x) is expressed as follows: Where h(x) represents the path length of the sample in the isolation tree, E(h(x)) represents the expected value of the path length in multiple isolation trees, and c(n) represents the path length correction term. When S(x) is greater than an adjustable threshold, the memory bank 10 under test is determined to be abnormal.

[0065] Regarding the subordinate step S54, the abnormality threshold T is adaptively adjusted according to the data distribution in the sliding window. The abnormality threshold T is expressed as follows: T=μ S +k·σ S , Among them, μ S and σ S Respectively represent the mean and standard deviation of the anomaly score in the sliding window, and k represents an empirical coefficient (e.g., k=3.0). By calculating the mean μ of the recent anomaly score in the sliding window in real time S and standard deviation σ S , and perform adaptive adjustments so that the abnormal threshold can adapt to environmental changes (such as baseline drift caused by equipment aging) and reduce false alarms.

[0066] In one example, when a memory module experienced occasional signal delay anomalies during high-temperature testing, the mean signal delay suddenly increased from 10ns to 50ns, and the standard deviation of power consumption fluctuations rose from 5mW to 20mW. At this point, the isolation forest model identified the joint deviation of delay and power consumption, significantly shortening the path length h(x) and achieving anomaly score S(x) = 0.85, exceeding the threshold T = 0.72, triggering an alert.

[0067] Main step S5 uses the isolation forest model for unsupervised anomaly detection. This model directly learns normal patterns without labeling abnormal data, significantly simplifying the training process. Calculations are performed using feature extraction and tree traversal, resulting in a latency of less than 50ms and high real-time performance. The combined analysis of multiple features, including signal latency and power consumption fluctuations, significantly improves detection recall.

[0068] Regarding the main step S6, based on the intelligent sleep strategy of reinforcement learning (RL), the power consumption of the test machine 20 is dynamically adjusted according to the test task load. Figure 8 , the main step S6 includes subordinate steps S61-S64.

[0069] Regarding the subordinate step S61, the state space is determined. The state s of the test machine t It is expressed as the following formula: s t =(Q queue , P current , T ambient ), where Q queue Indicates the queue length to be tested of the test machine, P currentIndicates the current power of the test machine, T ambient Indicates the ambient temperature.

[0070] Regarding the subordinate step S62, the action space is determined. The execution action a of the test machine t It is expressed as the following formula: a t ∈{Active, Low-Power, Sleep}, Among them, Active means executing normal power consumption mode, Low-Power means executing low power consumption mode, and Sleep means executing sleep mode.

[0071] Regarding subordinate step S63, a reward function is determined based on energy consumption and response speed. t It is expressed as the following formula: r t =-α·P action -β·Delay(a t ), Wherein, α and β represent weight coefficients, which are used to balance energy consumption and response speed (e.g., α = 0.6, β = 0.4). action Indicates the power consumption of the test machine when executing the action (for example, the power consumption in Sleep mode is 10W, and the power consumption in Active mode is 100W), Delay (a t ) indicates the delay caused by switching the execution action of the test machine (for example, it takes 2 seconds to switch from Sleep mode to Active mode).

[0072] This reward function can guide the agent to choose low-power and fast-response actions (for example, switching to Sleep mode during idle periods and waking up quickly when tasks arrive). The reward mechanism can reduce overall energy consumption (power consumption during idle periods is reduced by approximately 35%).

[0073] In subordinate step S64, the intelligent sleep strategy is updated based on the Deep Q Network (DQN) algorithm, wherein the Q value is updated by experience replay, the intelligent sleep strategy is optimized, and the over-estimation of the Q value is suppressed by the dual network structure of the target network and the prediction network.

[0074] The implementation principle of the embodiment of the method of the present application is: to improve the test throughput through parallel testing and provide sufficient data for the AI ​​model, to reduce contact noise and improve signal quality through non-pluggable gold finger pressing, to simulate the operating status of the memory stick in an actual complex environment and obtain diversified data through multi-physical field coupling testing, to combine the timing neural network and the attention mechanism to model the timing data including voltage, frequency, temperature, humidity, etc. to achieve accurate life prediction, and to use the isolation forest model to perform unsupervised anomaly detection and adaptive threshold adjustment on signal delay and power consumption fluctuations, so as to comprehensively evaluate the performance of the memory stick, and significantly improve the ability to identify potential defects of the memory stick under complex operating conditions and the accuracy of life prediction.

[0075] See also Figure 3 - Figure 5 The present application also provides a memory stick tester, primarily for implementing the aforementioned memory testing method. The memory stick tester 20 includes a tester body 21, an environmental simulation chamber 22, a display interface 23, a data acquisition and signal conditioning system, a control and processing system, a power supply system, and an artificial intelligence algorithm module 40 integrated within the tester body 21.

[0076] The tester body 21 typically utilizes a rugged, industrial-grade chassis structure, housing the control system, power supply system, data acquisition and processing unit, and user interface (e.g., display interface 23). The chassis requires excellent electromagnetic shielding to minimize interference from internal components on the test environment and protect the delicate electronic components from external influences.

[0077] The environmental simulation chamber 22 is integrated into the testing machine body (21) or as a tightly connected module. The interior of the chamber is designed with good thermal insulation and sealing properties to maintain the set temperature and humidity environment. Figure 4The environmental simulation chamber 22 is provided with a vibration table 22a, an electromagnetic interference source 22b, and a temperature change module 22c. The vibration table 22a can use an electric vibrator to achieve mechanical vibration in the frequency range of 5-2000Hz. The electric vibrator is installed at the bottom of the environmental simulation chamber 22 via a fixed bracket to ensure that the vibration table 22a can operate stably. The electromagnetic interference source 22b can use a signal generator and an antenna combination to simulate the electromagnetic interference environment. The signal generator is connected to the antenna via a wire, and the electromagnetic interference intensity and frequency can be adjusted as needed. The temperature change module 22c can use a refrigerant circulation system to achieve rapid temperature changes with a temperature change rate of not less than 10°C / min. The refrigerant circulation system includes a compressor, a condenser, an evaporator, and an expansion valve. The various components are connected by pipes to form a closed circulation loop. Optionally, the environmental simulation chamber 22 can also be provided with a humidity control module for controlling the relative humidity in the chamber and an air pressure control module for simulating air pressure environments at different altitudes.

[0078] Several parallel test stations 24 are provided in the environmental simulation chamber 22 for placing the memory stick 10 to be tested. Each parallel test station 24 is equipped with a gold finger pressing mechanism 30 for electrically contacting the gold finger 12 of the memory stick 10 to be tested. The mechanism is responsible for establishing stable, low-impedance, non-destructive electrical contact with the gold finger 12 of the memory stick 10 to be tested for transmitting test signals and power supply.

[0079] In the example of the best memory test machine, refer to Figure 5 The gold finger crimping mechanism 30 includes a fixing plate 31 and a connector 32. The fixing plate 31 has an opening 31a, and the connector 32 is disposed at the opening 31a. The fixing plate 31 and the connector 32 are crimped and mounted on the PCB (printed circuit board) adapter plate 25 of the tester 20. The connector 32 is electrically connected to the PCB adapter plate 25 of the tester 20 and electrically contacts the gold fingers 12 of the memory module 10 under test.

[0080] Compared with the related art in which the adapter is welded and fixed on the PCB adapter board 25 of the test machine 20, the gold finger crimping mechanism 30 can be easily replaced when it reaches the end of its service life by crimping the fixing plate 31 and the connector 32 on the PCB adapter board 25 of the test machine 20, or different gold finger crimping mechanisms 30 can be replaced according to different types of the memory sticks 10 to be tested.

[0081] For reference Figure 5, the connector 32 may include a spring probe that electrically contacts the gold finger 12 of the memory bar 10 under test from the bottom of the memory bar 10 under test. Optionally, the connector 32 may include a probe card that electrically contacts the gold finger 12 of the memory bar 10 under test from the top of the memory bar 10 under test. In a preferred method example, the connector 32 may include a spring probe and a probe card, wherein the spring probe electrically contacts the lower area of ​​the gold finger 12 of the memory bar 10 under test from the bottom of the memory bar 10 under test, and the probe card electrically contacts the upper area of ​​the gold finger 12 of the memory bar 10 under test from the top of the memory bar 10 under test, so as to physically separate the test contacts of the gold finger 12 of the memory bar 10 under test.

[0082] The data acquisition and processing unit, integrated within the tester body 21, is responsible for acquiring electrical signals from the memory stick 10 under test from the gold finger crimping mechanism 30 and obtaining environmental parameters (temperature, humidity, vibration, etc.) from sensors within the environmental simulation chamber 22. The system includes a high-speed ADC (analog-to-digital converter), precision voltage / current measurement units, signal amplifiers, filters, and other components to ensure that the accuracy and bandwidth of the collected data meet test requirements. In particular, measuring signal delays and power consumption fluctuations requires high-precision time measurement circuits (such as TDCs) and high-bandwidth power monitoring circuits.

[0083] The control and processing system typically consists of a high-performance embedded processor (such as an FPGA + ARM processor or an industrial PC) running the test control software (Test Executive). This system is responsible for: parsing the test plan, controlling the stress application devices in the environmental simulation chamber 22 to operate according to the preset profile; controlling the generation and application of test signals; synchronously coordinating data acquisition; running the internally integrated artificial intelligence algorithm module 40 to perform life prediction and anomaly detection calculations; managing the test process, recording test results, and interacting with users or higher-level management systems through the display interface 23 or network interface.

[0084] The artificial intelligence algorithm module 40 is usually implemented in the form of software running on the control and processing system, or through a dedicated hardware accelerator (such as GPU, TPU, NPU). Figure 9, the artificial intelligence algorithm module 40 includes a timing neural network algorithm module 41, an anomaly detection module 42 and an intelligent sleep module 43. The timing neural network algorithm module 41 is used to model the test data through a timing neural network model combined with an attention mechanism to predict the life of the memory stick 10 to be tested. The anomaly detection module 42 is used to perform unsupervised anomaly detection on the memory stick 10 to be tested through the root signal delay and power consumption fluctuation of the isolation forest model, and adaptively adjust the anomaly threshold to identify defects in the memory stick 10 to be tested. The intelligent sleep module 43 is used for an intelligent sleep strategy based on reinforcement learning, which dynamically adjusts the power consumption of the test machine 20 according to the test task load. In addition, the artificial intelligence algorithm module 40 also includes a data preprocessing unit (for cleaning, normalization, feature extraction, etc.) and a model management unit (for loading and updating model parameters, etc.).

[0085] The power supply system is used to provide stable and clean power to various parts of the tester 20, including providing programmable power supply voltage (Vdd / Vddq, etc.) for the memory stick 10 under test. The power supply system needs to have overvoltage and overcurrent protection functions.

[0086] The display interface 23 can provide a graphical user interface (GUI) for test configuration, starting / stopping tests, real-time monitoring of test status (environmental parameters, memory status, prediction results, abnormal alarms, etc.), and viewing historical data and reports.

[0087] The implementation principle of the test machine embodiment of the present application is: to provide a test device capable of executing the memory stick test method, which integrates the above-mentioned environmental simulation chamber 22 (including a parallel test station 24, a vibration table 22a, an electromagnetic interference source 22b and a temperature change module 22c), a gold finger pressing mechanism 30 and an artificial intelligence algorithm module 40 (a timing neural network algorithm module 41, an anomaly detection module 42 and an intelligent sleep module 43), thereby realizing high-throughput, multi-physical field coupling environment testing of the memory stick 10 to be tested, and can directly perform life prediction and defect identification, thereby improving test efficiency and accuracy, and can comprehensively evaluate the reliability of the memory stick under complex working conditions.

[0088] The above are all preferred embodiments of the present application, and are not intended to limit the scope of protection of the present application. Therefore, any equivalent changes made based on the structure, shape, and principle of the present application should be included in the scope of protection of the present application.

Claims

1. A memory stick testing method, characterized in that: include: S1, placing a memory bar (10) to be tested on a parallel testing station (24) of a testing machine (20), wherein the memory bar (10) to be tested comprises a carrier board (11), a gold finger (12) provided on one side of the carrier board (11), and a volatile memory chip (13) mounted on the carrier board (11); S2, electrically contacting the gold finger (12) of the memory stick (10) to be tested through the gold finger pressing mechanism (30); S3, performing a multi-physical field coupling test on the memory bar (10) to be tested to obtain test data, signal delay and power consumption fluctuation of the memory bar (10) to be tested, wherein the multi-physical field coupling test includes: applying mechanical vibration, simulating electromagnetic interference environment and applying temperature change; S4, modeling the test data using a temporal neural network model combined with an attention mechanism to predict the life of the memory stick (10) to be tested; S5. Perform unsupervised anomaly detection on the memory bar (10) to be tested according to the signal delay and the power consumption fluctuation using an isolation forest model, and adaptively adjust an anomaly threshold to identify defects of the memory bar (10) to be tested.

2. The memory bar testing method according to claim 1, wherein: In step S1, the parallel test station (24) is located in an environmental simulation chamber (22), and the environmental simulation chamber (22) is provided with a vibration table (22a), an electromagnetic interference source (22b), and a temperature change module (22c). In step S3, mechanical vibration is applied by the vibration table (22a), an electromagnetic interference environment is simulated by the electromagnetic interference source (22b), and temperature change is applied by the temperature change module (22c).

3. The memory bar testing method according to claim 1, wherein: Step S2 includes: The gold finger (12) of the memory bar (10) to be tested is electrically contacted from above the memory bar (10) through a probe card, and the gold finger (12) of the memory bar (10) to be tested is electrically contacted from below the memory bar (10) through a spring probe.

4. The memory stick testing method according to claim 1, wherein: The test data in step S3 includes the voltage, frequency, temperature and humidity of the memory bar (10) to be tested. In step S4, the voltage, frequency, temperature and humidity of the memory bar (10) to be tested are input into the timing neural network model, and the multi-parameter timing dependency relationship between the voltage, frequency, temperature and humidity of the memory bar (10) to be tested is extracted in combination with the attention mechanism to predict the life of the memory bar (10) to be tested.

5. The memory bar testing method according to claim 1, wherein: Step S4 includes: S41. Using a temporal neural network model based on a long short-term memory network, input the test data and control the information flow through a gating mechanism. The temporal neural network model based on a long short-term memory network is expressed as follows: f t =σ(W f ·[h t-1 ,x t ]+b f ), i t =σ(W i ·[h t-1 ,x t ]+b i ), the t =σ(W o ·[h t-1 ,x t ]+b o ), h t =o t ☉tanh(C t ), Among them, f t Represents the forget gate, which is used to determine the previous memory unit C t-1 Information retained in; i t represents the input gating signal, Represents a candidate memory unit, i t and Used as an input gate to control the input feature vector x t For memory unit C t Updates; t Represents the output gate, which is used to determine the current hidden state h t Output content of W f 、W i 、W C 、W o Represents the weight matrices of the forget gate, input gating signal, candidate memory unit, and output gate respectively; b f 、b i 、b C 、b o Respectively represent the bias items of the forget gate, input gating signal, candidate memory unit, and output gate; x t represents the input feature vector of the current time step t, determined according to the test data; h t-1 represents the hidden state of the previous time step, C t Represents a memory unit, σ represents a Sigmoid function, and ⊙ represents element-wise multiplication; S42, introducing the time step attention weight α into the temporal neural network model based on the long short-term memory network t To enhance the ability to extract time series features, it is expressed as follows: Among them, W a represents the attention weight matrix, b a represents the attention bias term, v T represents the attention weight vector, s represents the context vector, which is used to weight the hidden state h of all time steps t , T represents the total time step; S43, inputting the context vector s into the fully connected network, and outputting the life percentage R of the memory bar (10) to be tested, which is expressed as the following formula: R=Sigmoid(W r ·s+b r ) Among them, W r represents the output layer weight matrix, b r Represents the output layer bias term.

6. The memory stick testing method according to claim 5, wherein: Step S4 further includes: S44. Train the temporal neural network model, use weighted mean square error as the loss function, and use AdamW optimizer to suppress overfitting. The loss function is expressed as follows: in, represents the loss function, represents the number of the memory bars (10) to be tested in the training batch, w i represents the weight parameter of the i-th memory bank (10) to be tested, R i represents the actual remaining life percentage of the i-th memory module (10) to be tested, Indicates the predicted remaining life percentage of the i-th memory stick (10) to be tested.

7. The memory bar testing method according to claim 1, wherein: Step S5 includes: S51, dividing the data stream containing the signal delay and the power consumption fluctuation into a plurality of sliding windows, and extracting statistical features of the signal delay and the power consumption fluctuation from the sliding windows; S52, constructing an isolation tree, wherein a feature subset and a partition value of the statistical feature are randomly selected, and the data is recursively partitioned until the sample is isolated; S53. Take an average of multiple isolated trees to calculate the anomaly score of the sample x containing the signal delay or the power consumption fluctuation, which is expressed as the following formula: Where S(x) represents the anomaly score, h(x) represents the path length of the sample in the isolated tree, E(h(x)) represents the expected value of the path length in multiple isolated trees, and c(n) represents the path length correction term; S54. Adaptively adjust the abnormality threshold T according to the data distribution in the sliding window, which is expressed as the following formula: T=μ S +k·s S , Among them, μ S and σ S They represent the mean and standard deviation of the anomaly score within the sliding window, and k represents the empirical coefficient.

8. The memory bar testing method according to claim 1, wherein: Also includes: S6, based on the intelligent sleep strategy of reinforcement learning, dynamically adjusting the power consumption of the test machine (20) according to the test task load, step S6 includes: S61. Determine the state space, which is expressed as the following formula: s t =(Q queue ,P current ,T ambient ), Among them, s t Indicates the state of the test machine (20), Q queue represents the queue length to be tested of the test machine (20), P current represents the current power of the test machine (20), T ambient represents the ambient temperature; S62. Determine the action space, which is expressed as the following formula: a t ∈{Active,Low-Power,Sleep}, Among them, a t Indicates the execution action of the test machine (20), Active indicates the execution of normal power consumption mode, Low-Power indicates the execution of low power consumption mode, and Sleep indicates the execution of sleep mode; S63, determining the reward function r based on energy consumption and response speed t , expressed as the following formula: r t =-α·P action -β.Delay(a t ), Among them, α and β represent weight coefficients, P action Delay(a) represents the power consumption of the test machine (20) when executing the action. t ) represents the delay caused by the execution action of switching the test machine (20); S64. Update the intelligent sleep strategy based on a deep Q network algorithm, wherein the Q value is updated by experience replay, the intelligent sleep strategy is optimized, and over-estimation of the Q value is suppressed by a dual network structure of a target network and a prediction network.

9. A memory stick testing machine, characterized in that: For implementing a memory stick testing method according to any one of claims 1 to 8, the memory stick testing machine comprises: A test machine body (21) is provided with an environmental simulation chamber (22) for performing a multi-physical field coupling test on the memory bar (10) to be tested, so as to obtain test data, signal delay and power consumption fluctuation of the memory bar (10) to be tested, wherein the multi-physical field coupling test includes: applying mechanical vibration, simulating electromagnetic interference environment and applying temperature change; a plurality of parallel test stations (24) for placing the memory bar (10) to be tested are provided in the environmental simulation chamber (22), wherein the memory bar (10) to be tested includes a carrier board (11), a gold finger (12) provided on one side of the carrier board (11) and a volatile memory chip (13) installed on the carrier board (11); each parallel test station (24) is equipped with a gold finger pressing mechanism (30) for electrically contacting the gold finger of the memory bar (10) to be tested; A time series neural network algorithm module (41) and an anomaly detection module (42) are integrated into the test machine body (21). The time series neural network algorithm module (41) models the test data by combining a time series neural network model with an attention mechanism to predict the life of the memory bar (10) to be tested. The anomaly detection module (42) performs unsupervised anomaly detection on the memory bar (10) to be tested by using an isolation forest model and based on the signal delay and the power consumption fluctuation. The anomaly detection module (42) also adaptively adjusts an anomaly threshold to identify defects in the memory bar (10) to be tested.

10. The memory stick testing machine according to claim 9, characterized in that: The gold finger crimping mechanism (30) comprises: a fixing plate (31) having an opening (31a) for installing and fixing a connector (32); A connector (32) is provided at the opening (31a) and is used to establish an electrical connection between a memory stick tester and the memory stick to be tested (10); the fixing plate (31) and the connector (32) are press-fitted and mounted on a PCB adapter plate (25) of the memory stick tester; the connector (32) is electrically connected to the PCB adapter plate (25) and electrically contacts the gold finger (12) of the memory stick to be tested (10); the connector (32) comprises a spring probe and a probe card; the spring probe electrically contacts the gold finger (12) of the memory stick to be tested (10) from below; and the probe card electrically contacts the gold finger (12) of the memory stick to be tested (10) from above.

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