Semiconductor device, manufacturing method and wafer structure
By removing the passivation layer and retaining buffer layer covering the electrodes during the semiconductor device manufacturing process, the problem of low cutting accuracy caused by etching residue is solved, and a higher precision scribe cutting is achieved.
Patent Information
- Application Number
- CN202510665819.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-10
- Publication Date
- 2025-08-26
AI Technical Summary
During the cutting process of the scribed track area, the cutting accuracy of existing semiconductor devices is not high due to etching residues.
During semiconductor device manufacturing, some or all of the passivation layers of the core area and the scribed lane region are removed, and a buffer layer is retained to cover the first electrode when the first insulating layer of the scribed lane region is removed, avoiding etching to generate by-products.
The accuracy of scribing and cutting is improved, and the impact of etching residues on the cutting path is avoided, ensuring the accuracy of cutting.
Smart Images
Figure CN120545192A_ABST
Abstract
Description
[0001] This application is a divisional application of the Chinese patent application with application number "202510038730.9", application date "January 10, 2025", and title "Semiconductor device and manufacturing method, chip structure". Technical Field
[0002] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device, a manufacturing method, and a chip structure. Background Art
[0003] Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), a third-generation wide-bandgap semiconductor represented by silicon carbide, has become a research hotspot in power semiconductor devices. It has excellent properties such as wide bandgap, high critical breakdown electric field, high electron saturation mobility and high thermal conductivity.
[0004] During the dicing and cutting process of existing semiconductor devices from the dicing street region, etching residues may exist on the surface of the semiconductor body in the dicing street region, thereby resulting in low cutting accuracy in the dicing street region. Summary of the Invention
[0005] The present invention provides a semiconductor device, a manufacturing method and a wafer structure, so as to improve the cutting accuracy of dicing in a dicing lane area during the manufacturing process of the semiconductor device.
[0006] According to one aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising:
[0007] A semiconductor structure is provided, comprising a device core region and a scribe line region; the scribe line region is located on one side of the device core region; the semiconductor structure further comprises a semiconductor body, a first electrode, a first insulating layer, and a buffer layer; the semiconductor body comprises a first surface and a second surface disposed opposite to each other; the first insulating layer is located on the first surface and at least in the scribe line region; the first electrode is located on a side of the first insulating layer away from the semiconductor body and in the device core region; the buffer layer is located on a surface of the first electrode away from the semiconductor body, and the buffer layer is located in the device core region;
[0008] forming a passivation layer on a side of the buffer layer away from the first electrode, wherein the passivation layer is located in the device core region and the dicing street region;
[0009] removing at least a portion of the passivation layer in the device core region and the scribe street region;
[0010] removing the first insulating layer in the scribe line region, wherein the buffer layer is at least partially retained during the removal of the first insulating layer and covers the first electrode;
[0011] removing at least a portion of the buffer layer;
[0012] Scribe cutting is performed in the scribe line area.
[0013] According to another aspect of the present invention, there is provided a semiconductor device manufactured by any of the methods for manufacturing a semiconductor device described in any of the embodiments of the present invention.
[0014] According to another aspect of the present invention, there is provided a wafer structure comprising:
[0015] A semiconductor structure comprising a device core region and a scribe line region; the scribe line region is located on one side of the device core region; the semiconductor structure further comprises a semiconductor body, a first electrode, a first insulating layer, and a buffer layer; the semiconductor body comprises a first surface and a second surface arranged opposite to each other; the first insulating layer is located on the first surface and is at least located in the scribe line region; the first electrode is located on a side of the first insulating layer away from the semiconductor body and is located in the device core region; the buffer layer is located on a surface of the first electrode away from the semiconductor body, and the buffer layer is located in the device core region, the buffer layer being configured to be at least partially retained during removal of the first insulating layer and to cover the first electrode;
[0016] A passivation layer is located on a side of the buffer layer away from the first electrode, and the passivation layer is located in the device core area and the dicing street area.
[0017] The semiconductor device, manufacturing method, and chip structure provided by the embodiments of the present invention, and the technical solution provided by the embodiments of the present invention remove part or all of the passivation layer in the core area and the scribe line area of the device, and remove the first insulating layer in the scribe line area. The buffer layer is at least partially retained during the removal of the first insulating layer and covers the first electrode. That is, during the etching of the passivation layer and the first insulating layer, the first electrode can be covered by the buffer layer, thereby avoiding the first electrode from being etched to generate by-products covering the scribe line area, so that in the subsequent scribe cutting process in the scribe line area, there is no etching residue on the first surface of the semiconductor body in the scribe line area, thereby improving the accuracy of scribe cutting.
[0018] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0020] Figure 1 It is a structural schematic diagram of a semiconductor device provided by the prior art;
[0021] Figure 2 It is a structural schematic diagram of another semiconductor device provided by the prior art;
[0022] Figure 3 is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;
[0023] Figure 4-13 It is a structural schematic diagram corresponding to each step of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;
[0024] Figure 14 yes Figure 3 A flow chart example provided in S110;
[0025] Figure 15 yes Figure 14 Schematic diagram of the structure corresponding to the relevant steps in the figure;
[0026] Figure 16 yes Figure 3 Another example flow chart provided by S110;
[0027] Figure 17 yes Figure 16 Schematic diagram of the structure corresponding to the relevant steps in the figure;
[0028] Figure 18 yes Figure 3 Another flow chart provided by S110. DETAILED DESCRIPTION
[0029] To help those skilled in the art better understand the present invention, the following will provide a clear and complete description of the technical solutions in the embodiments of the present invention, in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments derived by those skilled in the art based on the embodiments of the present invention without creative effort should fall within the scope of protection of the present invention.
[0030] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations of "including" and "having" are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or devices is not necessarily limited to those steps or devices that are clearly listed, but may include other steps or structures that are not clearly listed or inherent to these processes, methods, products or devices.
[0031] Figure 1 It is a structural diagram of a semiconductor device provided by the prior art. Figure 2 This is a schematic diagram of the structure of another semiconductor device provided by the prior art. The manufacturing method of the semiconductor device in the prior art includes:
[0032] like Figure 1 As shown, a semiconductor structure is provided, which includes a device core region 01 and a scribe line region 02; the scribe line region 02 is located on one side of the device core region 01; the semiconductor structure also includes a semiconductor body 100, a first electrode 200 and a first insulating layer 300; the semiconductor body 100 includes a first surface 101 and a second surface 102 arranged opposite to each other; the first insulating layer 300 is located on the first surface 101 and at least in the scribe line region 02; the first electrode 200 is located on the side of the first insulating layer 300 away from the semiconductor body 100, and is located in the device core region 01.
[0033] like Figure 1 As shown, a passivation layer 400 is formed on the side of the first electrode 200 away from the semiconductor body 100 , and the passivation layer 400 covers the device core region 01 and the scribe street region 02 . Then, a mask layer 401 is formed on the side of the passivation layer 400 away from the first electrode 200 .
[0034] like Figure 2 As shown, the passivation layer 400 and the first insulating layer 300 in the device core region 01 and the scribe street region 02 are removed by a dry etching process. During the dry etching process to remove the passivation layer 400 and the first insulating layer 300, it is inevitable that dry etching particles continuously bombard the first electrode 200, thereby generating byproducts, which cover the scribe street region 02.
[0035] like Figure 2As shown, since the byproducts cover the scribe line region 02 , during the process of removing the first insulating layer 300 , etching residues 300 a of the first insulating layer 300 exist on the first surface 101 of the semiconductor body 100 in the scribe line region 02 .
[0036] like Figure 2 As shown, when there are etching residues 300a on the first surface 101 of the semiconductor body 100 in the scribing area 02, a laser cutting process is usually adopted, and a high-power density laser beam is used to irradiate the scribing area 02 for cutting. After the laser is irradiated to the etching residue 300a, it is scattered downward, thereby changing the cutting path of the laser, which in turn leads to low scribing cutting accuracy.
[0037] It should be noted that Figure 1 and Figure 2 The following describes the manufacturing process of a MOSFET semiconductor device as an example.
[0038] In order to improve the cutting accuracy of scribing in the scribing street area during the semiconductor device manufacturing process, the embodiments of the present invention provide the following technical solutions:
[0039] like Figure 3 As shown, Figure 3 1 is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention, the method for manufacturing a semiconductor device comprising the following steps:
[0040] S110. Provide a semiconductor structure, the semiconductor structure including a device core region and a scribe line region; the scribe line region is located on one side of the device core region; the semiconductor structure also includes a semiconductor body, a first electrode, a first insulating layer and a buffer layer; the semiconductor body includes a first surface and a second surface arranged opposite to each other; the first insulating layer is located on the first surface and is at least located in the scribe line region; the first electrode is located on a side of the first insulating layer away from the semiconductor body and is located in the device core region; the buffer layer is located on the surface of the first electrode away from the semiconductor body, and the buffer layer is located in the device core region.
[0041] The process of providing a semiconductor structure is as follows:
[0042] like Figure 4As shown, a semiconductor structure is provided, comprising a device core region 01 and a scribe line region 02; the scribe line region 02 is located on one side of the device core region 01; and the semiconductor structure further comprises a semiconductor body 100, a first electrode 200, and a first insulating layer 300. The semiconductor body 100 comprises a first surface 101 and a second surface 102 disposed opposite each other. The first insulating layer 300 is located on the first surface 101 and at least in the scribe line region 02; the first electrode 200 is located on a side of the first insulating layer 300 away from the semiconductor body 100 and in the device core region 01. In an embodiment of the present invention, the semiconductor body 100 comprises a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the semiconductor body 100 may comprise only the epitaxial layer 20. In other embodiments of the present invention, the semiconductor body 100 may further comprise the substrate 10 and semiconductor layers formed by other processes. The epitaxial layer 20 is a semiconductor layer formed on the substrate 10 through a single epitaxial process, wherein the epitaxial process includes chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), atomic layer epitaxy (ALE) and other processes.
[0043] like Figure 5 As shown, a buffer layer 500 is formed on a surface of the first electrode 200 away from the semiconductor body 100 .
[0044] like Figure 6 As shown, a mask layer 001 is formed on a side of the buffer layer 500 away from the first electrode 200 .
[0045] like Figure 7 As shown, the buffer layer 500 is patterned, and the buffer layer 500 located in the device core region 01 is retained.
[0046] S120 , forming a passivation layer on a side of the buffer layer away from the first electrode, wherein the passivation layer is located in the device core region and the dicing street region.
[0047] like Figure 8 As shown, a passivation layer 400 is formed on a side of the buffer layer 500 away from the first electrode 200 , and the passivation layer 400 is located in the device core region 01 and the scribe street region 02 . A mask layer 002 is also formed on a side of the passivation layer 400 away from the buffer layer 500 .
[0048] S130 , removing at least a portion of the passivation layer in the device core area and the scribe street area.
[0049] like Figure 11 As shown, part or all of the passivation layer 400 in the device core region 01 and the dicing street region 02 is removed.
[0050] S140 , removing the first insulating layer in the scribe line area, wherein the buffer layer is at least partially retained during the removal of the first insulating layer and covers the first electrode.
[0051] like Figure 12 As shown, the first insulating layer 300 in the scribe street region 02 is removed, and the buffer layer 500 is at least partially retained during the removal process of the first insulating layer 300 and covers the first electrode 200 .
[0052] S150: Remove at least a portion of the buffer layer.
[0053] like Figure 13 As shown, at least a portion of the buffer layer 500 is removed.
[0054] S160 , performing scribing and cutting in the scribing street area.
[0055] like Figure 13 As shown, dicing can be performed in the dicing street area 02 by a laser cutting process.
[0056] The technical solution provided by the embodiment of the present invention removes part or all of the passivation layer 400 in the device core area 01 and the scribe line area 02, and removes the first insulating layer 300 in the scribe line area 02. The buffer layer 500 is at least partially retained during the removal of the first insulating layer 300 and covers the first electrode 200. That is, during the etching process of the passivation layer 400 and the first insulating layer 300, it can be ensured that the first electrode 200 is covered by the buffer layer 500, thereby avoiding the first electrode 200 from being etched to generate a by-product covering the scribe line area 02, so that in the subsequent scribe cutting process in the scribe line area 02, there is no etching residue on the first surface 101 of the semiconductor body 100 in the scribe line area 02, thereby improving the accuracy of scribe cutting.
[0057] Optionally, based on the above technical solution, the materials of the first insulating layer 300 and the buffer layer 500 are the same; when removing the first insulating layer 300 in the dicing area 02, the thickness of the buffer layer 500 is greater than the thickness of the first insulating layer 300 to ensure that the first electrode 200 can be covered by the buffer layer 500 during the etching process of the first insulating layer 300.
[0058] Optionally, based on the above technical solution, the materials of the first insulating layer 300 and the buffer layer 500 are different; when removing the first insulating layer 300 in the dicing area 02, an etching gas having a lower etching rate for the buffer layer 500 than the etching rate for the first insulating layer 300 can be selected to control the removal rate of the buffer layer 500 to be lower than the removal rate of the first insulating layer 300, so as to ensure that the first electrode 200 is covered by the buffer layer 500 during the etching process of the first insulating layer 300.
[0059] Optionally, based on the above technical solution, Figure 11 and Figure 12The buffer layer 500 includes at least two sub-buffer layers. When removing the first insulating layer 300 in the dicing street area 02, an etching gas having an etching rate for at least part of the sub-buffer layer lower than the etching rate for the first insulating layer 300 can be selected to control the removal rate of at least part of the sub-buffer layer to be lower than the removal rate of the first insulating layer 300, so as to ensure that the first electrode 200 is covered by the buffer layer 500 during the etching of the first insulating layer 300, thereby avoiding over-etching due to further etching of the buffer layer 500 and exposure of the first electrode after the first insulating layer 300 is completely etched during the etching process of the first insulating layer 300.
[0060] For example, the embodiment of the present invention is described by taking the example that the first insulating layer 300 includes two sub-insulating layers, namely a first sub-insulating layer 301 and a second sub-insulating layer 302 .
[0061] For example, Figure 8 In the embodiment, the buffer layer 500 includes two sub-buffer layers, namely a first sub-buffer layer 501 and a second sub-buffer layer 502 . Figure 9 In the embodiment, the buffer layer 500 comprises a single-layer structure. Figure 10 In the embodiment, the buffer layer 500 includes three sub-buffer layers, namely a first sub-buffer layer 501 , a second sub-buffer layer 502 and a third sub-buffer layer 503 .
[0062] Optionally, based on the above technical solution, when removing the first insulating layer 300 in the dicing area 02, the removal rate of the underlying sub-buffer layer is less than the removal rate of the underlying sub-insulating layer, the underlying sub-buffer layer is the sub-buffer layer in the buffer layer 500 that is in contact with the first electrode 200, and the underlying sub-insulating layer is the sub-insulating layer in the first insulating layer 300 that is in contact with the first surface 101.
[0063] The above technical solution can ensure that after the first sub-insulating layer 301 in the scribe street region 02 is completely removed, the underlying sub-buffer layer still covers the first electrode 200 in the device core region 01. That is, during the etching process of the first insulating layer 300, the first electrode 200 can be covered by the buffer layer 500, thereby preventing the first electrode 200 from being etched to form byproducts covering the scribe street region 02. As a result, during the subsequent dicing process of the scribe street region 02, no etching residue is left on the first surface 101 of the semiconductor body 100 in the scribe street region 02, thereby improving the dicing accuracy.
[0064] Optionally, based on the above technical solution, when removing the passivation layer 400 in the dicing area 02, an etching gas having an etching rate for at least part of the sub-buffer layer lower than the etching rate for the passivation layer 400 can be selected to control the removal rate of at least part of the sub-buffer layer to be lower than the removal rate of the passivation layer 400, so as to ensure that the first electrode 200 is covered by the buffer layer 500 during the etching process of the passivation layer 400, thereby avoiding over-etching due to further etching of the buffer layer 500 and exposure of the first electrode after the etching of the passivation layer 400 is completed.
[0065] Optionally, based on the above technical solution, the sub-buffer layer includes any one of silicon oxide, silicon nitride, polysilicon, silicon, germanium and silicon-germanium heterostructure, or a combination of at least two thereof.
[0066] Optionally, based on the above technical solution, Figure 14 As shown, S110 provides a semiconductor structure including:
[0067] S1101. Provide a semiconductor body, the semiconductor body comprising a first surface and a second surface disposed opposite each other; the semiconductor body further comprising a well region and a first region, the first region being of a first conductivity type and located on the first surface, and the well region being of a second conductivity type and located on a side of the first region away from the first surface. The semiconductor body further comprises a second insulating layer, the second insulating layer being located on the first surface.
[0068] like Figure 15 As shown, a semiconductor body 100 is provided. The semiconductor body 100 includes a first surface 101 and a second surface 102 disposed opposite to each other. The semiconductor body 100 also includes a well region 103 and a first region 104. The first region 104 is of the first conductivity type and is located on the first surface 101. The well region 103 is of the second conductivity type and is located on a side of the first region 104 away from the first surface 101. The semiconductor body 100 also includes a second insulating layer 107. The second insulating layer 107 is located on the first surface 101.
[0069] In other embodiments, the semiconductor body 100 further includes a second region 105 , and the second region 105 is of the second conductivity type.
[0070] S1102 , forming a gate on a side of the second insulating layer away from the first surface, wherein the second insulating layer is used for insulating and spacing the semiconductor body and the gate.
[0071] like Figure 15 As shown, a gate 108 is formed on a side of the second insulating layer 107 away from the first surface 101 . The second insulating layer 107 is used to insulate and space the semiconductor body 100 from the gate 108 .
[0072] S1103 , forming an interlayer insulating layer on a side of the gate away from the semiconductor body.
[0073] like Figure 15 As shown, an interlayer insulating layer 109 is formed on a side of the gate 108 away from the semiconductor body 100 .
[0074] S1104 , forming a first electrode on the first surface of the semiconductor body, the first electrode being a source electrode; an interlayer insulating layer is used to insulate and separate the gate electrode and the source electrode.
[0075] like Figure 15 As shown, a first electrode 200 is formed on the first surface 101 of the semiconductor body 100 , and the first electrode 200 is a source electrode; an interlayer insulating layer 109 is used to insulate and space the gate electrode 108 from the source electrode.
[0076] S1105 , forming a drain on the second surface of the semiconductor body.
[0077] like Figure 15 As shown, a drain 600 is formed on the second surface 102 of the semiconductor body 100 .
[0078] Specifically, the above technical solution prepares a planar structure MOSFET power device.
[0079] Optionally, based on the above technical solution, Figure 16 As shown, S110 provides a semiconductor structure including:
[0080] S1106. Provide a semiconductor body, the semiconductor body comprising a first surface and a second surface disposed opposite to each other; the semiconductor body further comprising a well region and a first region, the first region being of a first conductivity type and located on the first surface, and the well region being of a second conductivity type and located on a side of the first region away from the first surface; a gate trench being disposed on the first surface, the gate trench extending from the first surface into the semiconductor body; and the semiconductor body further comprising a second insulating layer disposed on a bottom surface and sidewalls of the gate trench.
[0081] like Figure 17 As shown, a semiconductor body 100 is provided. The semiconductor body 100 includes a first surface 101 and a second surface 102 disposed opposite each other. The semiconductor body 100 also includes a well region 103 and a first region 104. The first region 104 is of the first conductivity type and is located on the first surface 101. The well region 103 is of the second conductivity type and is located on a side of the first region 104 away from the first surface 101. A gate trench T1 is provided on the first surface 101. The gate trench T1 extends from the first surface 101 into the semiconductor body 100. The semiconductor body 100 also includes a second insulating layer 107. The second insulating layer 107 is located on the bottom surface and sidewalls of the gate trench T1.
[0082] S1107 , forming a gate on a side of the second insulating layer away from the semiconductor body in the gate trench, wherein the second insulating layer is used for insulating and spacing the semiconductor body and the gate.
[0083] like Figure 17 As shown, a gate 108 is formed on a side of the second insulating layer 107 away from the semiconductor body 100 in the gate trench T1 . The second insulating layer 107 is used to insulate and space the semiconductor body 100 from the gate 108 .
[0084] S1108 , forming an interlayer insulating layer on a side of the gate away from the semiconductor body.
[0085] like Figure 17 As shown, an interlayer insulating layer 109 is formed on a side of the gate 108 away from the semiconductor body 100 .
[0086] S1109, forming a first electrode on the first surface of the semiconductor body, the first electrode being a source electrode; an interlayer insulating layer is used to insulate and separate the gate electrode and the source electrode.
[0087] like Figure 17 As shown, a first electrode 200 is formed on the first surface 101 of the semiconductor body 100 , and the first electrode 200 is a source electrode; an interlayer insulating layer 109 is used to insulate and space the gate electrode 108 from the source electrode.
[0088] S11010, forming a drain on the second surface of the semiconductor body.
[0089] like Figure 17 As shown, a drain 600 is formed on the second surface 102 of the semiconductor body 100 .
[0090] Specifically, the above technical solution prepares a MOSFET power device with a single trench structure.
[0091] Optionally, based on the above technical solution, Figure 18 As shown, S110 provides a semiconductor structure including:
[0092] S11011. Provide a semiconductor body, the semiconductor body comprising a first surface and a second surface disposed opposite each other; the semiconductor body further comprising a well region and a first region, the first region being of a first conductivity type and located on the first surface, and the well region being of a second conductivity type and located on a side of the first region away from the first surface; a gate trench being disposed on the first surface, the gate trench extending from the first surface into the semiconductor body; a source trench being disposed on the first surface, the source trench extending from the first surface into the semiconductor body. The semiconductor body further comprises a second insulating layer and a third insulating layer, the second insulating layer being disposed on the bottom surface and sidewalls of the gate trench, and the third insulating layer being disposed on the bottom surface and sidewalls of the source trench.
[0093] like Figure 8As shown, a semiconductor body 100 is provided. The semiconductor body 100 includes a first surface 101 and a second surface 102 disposed opposite to each other. The semiconductor body 100 also includes a well region 103 and a first region 104. The first region 104 is of the first conductivity type and is located on the first surface 101. The well region 103 is of the second conductivity type and is located on a side of the first region 104 away from the first surface 101. A gate trench T1 is provided on the first surface 101, extending from the first surface 101 into the semiconductor body 100. A source trench T2 is provided on the first surface 101, extending from the first surface 101 into the semiconductor body 100. The semiconductor body 100 also includes a second insulating layer 107 and a third insulating layer 112. The second insulating layer 107 is located on the bottom surface and sidewalls of the gate trench T1, and the third insulating layer 112 is located on the bottom surface and sidewalls of the source trench T2.
[0094] S11012. Form a gate on a side of the second insulating layer away from the semiconductor body in the gate trench, wherein the second insulating layer is used for insulating and spacing the semiconductor body and the gate.
[0095] like Figure 8 As shown, a gate 108 is formed on a side of the second insulating layer 107 away from the semiconductor body 100 in the gate trench T1 . The second insulating layer 107 is used to insulate and space the semiconductor body 100 from the gate 108 .
[0096] S11013. Form an interlayer insulating layer on a side of the gate away from the semiconductor body, wherein the interlayer insulating layer covers the gate.
[0097] like Figure 8 As shown, an interlayer insulating layer 109 is formed on a side of the gate 108 away from the semiconductor body 100 , and the interlayer insulating layer 109 covers the gate 108 .
[0098] S11014. Form a trench source structure on a side of the third insulating layer in the source trench away from the semiconductor body; the trench source structure includes a filling layer, and the third insulating layer is used to insulate and space the semiconductor body and the filling layer.
[0099] like Figure 8 As shown, a trench source structure is formed on the side of the third insulating layer 112 away from the semiconductor body 100 in the source trench T2 ; the trench source structure includes a filling layer 113 , and the third insulating layer 112 is used to insulate and space the semiconductor body 100 and the filling layer 113 .
[0100] S11015, forming a first electrode on a side of the first surface away from the second surface; an interlayer insulating layer is used to insulate and separate the gate and the source.
[0101] like Figure 8As shown, a first electrode 200 is formed on a side of the first surface 101 away from the second surface 102 , and the first electrode 200 serves as a source; an interlayer insulating layer 109 is used to insulate and separate the gate 108 and the source.
[0102] S11016. Form a drain on the second surface of the semiconductor body.
[0103] like Figure 8 As shown, a drain 600 is formed on the second surface 102 of the semiconductor body 100 .
[0104] Specifically, the above technical solution prepares a MOSFET power device with a double-trench structure.
[0105] Optionally, based on the above technical solution, Figure 8 、 Figure 15 and Figure 17 As shown, the first insulating layer 300 includes a first sub-insulating layer 301 and a second sub-insulating layer 302; the first sub-insulating layer 301 is located on the first surface 101 of the semiconductor body 100; the first sub-insulating layer 301 and the second insulating layer 107 are located in the same layer; the second sub-insulating layer 302 is located on the side of the first sub-insulating layer 301 away from the first surface 101; the second sub-insulating layer 302 and the interlayer insulating layer 109 are located in the same layer.
[0106] Specifically, the first sub-insulating layer 301 is prepared while the second insulating layer 107 is prepared, and the second sub-insulating layer 302 is prepared while the interlayer insulating layer 109 is prepared, thereby simplifying the preparation process and reducing the preparation cost.
[0107] An embodiment of the present invention also provides a semiconductor device, which is manufactured by any semiconductor device manufacturing method described in any embodiment of the present invention. Therefore, it has the intended effects of any semiconductor device manufacturing method described in any of the above embodiments of the present invention, which will not be repeated here.
[0108] The embodiment of the present invention further provides a wafer structure, such as Figures 8-10As shown, the wafer structure includes: a semiconductor structure, the semiconductor structure including a device core region 01 and a scribe street region 02; the scribe street region 02 is located on one side of the device core region 01; the semiconductor structure also includes a semiconductor body 100, a first electrode 200, and a first insulating layer 300. The semiconductor body 100 includes a first surface 101 and a second surface 102 disposed opposite each other. The first insulating layer 300 is located on the first surface 101 and at least in the scribe street region 02; the buffer layer 500 is used to at least partially remain during the removal process of the first insulating layer 300 and covers the first electrode 200; and the passivation layer 400 is located on the side of the buffer layer 500 away from the first electrode 200, and the passivation layer 400 is located in the device core region 01 and the scribe street region 02.
[0109] The chip structure provided by the embodiment of the present invention can obtain a single semiconductor device after dicing and cutting in the dicing street area 02. During the cutting process, part or all of the passivation layer 400 in the device core area 01 and the dicing street area 02 is removed, and the first insulating layer 300 in the dicing street area 02 is removed. The buffer layer 500 is at least partially retained during the removal of the first insulating layer 300 and covers the first electrode 200. That is, during the etching process of the passivation layer 400 and the first insulating layer 300, it can be ensured that the first electrode 200 is covered by the buffer layer 500, thereby avoiding the first electrode 200 from being etched to generate a by-product covering the dicing street area 02. Therefore, in the subsequent dicing and cutting process of the dicing street area 02, there is no etching residue on the first surface 101 of the semiconductor body 100 in the dicing street area 02, thereby improving the accuracy of dicing and cutting.
[0110] Alternatively, as Figure 8 、 Figure 15 and Figure 17 As shown, the semiconductor structure also includes a terminal region 03; wherein the terminal region 03 is located between the device core region 01 and the dicing street region 02; the terminal region 03 is provided with a semiconductor body 100, a first insulating layer 300 and a passivation layer 400; the first surface 101 of the semiconductor body 100 located in the terminal region 03 is provided with a terminal groove, and the first insulating layer 300 and the passivation layer 400 extend from the first surface 101 to the terminal groove; the semiconductor body 100 located at the bottom of the terminal groove is provided with a plurality of third regions 114 arranged at intervals along a direction perpendicular to the second surface 102 pointing to the first surface 101, the third regions 114 are of the second conductivity type, and the semiconductor body 100 between the third region 114 and the second surface 102 constitutes a depletion layer, thereby increasing the voltage resistance performance of the terminal region 03.
[0111] Optionally, the semiconductor device further includes an ohmic contact layer 110 , so as to form a good ohmic contact between the first electrode 200 and the semiconductor body 100 .
[0112] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.
[0113] The above specific embodiments do not constitute a limitation on the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made to the various embodiments based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.
Claims
1. A method for manufacturing a semiconductor device, characterized in that: include: A semiconductor structure is provided, comprising a device core region and a scribe line region; the scribe line region is located on one side of the device core region; the semiconductor structure further comprises a semiconductor body, a first electrode, a first insulating layer, and a buffer layer; the semiconductor body comprises a first surface and a second surface disposed opposite to each other; the first insulating layer is located on the first surface and at least in the scribe line region; the first electrode is located on a side of the first insulating layer away from the semiconductor body and in the device core region; the buffer layer is located on a surface of the first electrode away from the semiconductor body, and the buffer layer is located in the device core region; forming a passivation layer on a side of the buffer layer away from the first electrode, wherein the passivation layer is located in the device core region and the dicing street region; removing at least a portion of the passivation layer in the device core region and the scribe street region; removing the first insulating layer in the scribe line region, wherein the buffer layer is at least partially retained during the removal of the first insulating layer and covers the first electrode; removing at least a portion of the buffer layer; Perform dicing cuts in the dicing street area; Provide semiconductor structures including: A semiconductor body is provided, the semiconductor body comprising a first surface and a second surface disposed opposite to each other; the semiconductor body further comprising a well region and a first region, the first region being of a first conductivity type and located on the first surface, the well region being of a second conductivity type and located on a side of the first region away from the first surface; the semiconductor body further comprising a second insulating layer, the second insulating layer being located on the first surface; forming a gate on a side of the second insulating layer away from the first surface, wherein the second insulating layer is used for insulating and spacing the semiconductor body and the gate; forming an interlayer insulating layer on a side of the gate away from the semiconductor body; The first electrode is formed on the first surface of the semiconductor body, and the first electrode is a source electrode; the interlayer insulating layer is used to insulate and separate the gate electrode and the source electrode; A drain is formed on the second surface of the semiconductor body.
2. The method for manufacturing a semiconductor device according to claim 1, wherein: The first insulating layer and the buffer layer are made of the same material, and the buffer layer has a thickness greater than that of the first insulating layer.
3. The method for manufacturing a semiconductor device according to claim 1, wherein: The first insulating layer and the buffer layer are made of different materials; When removing the first insulating layer from the scribe line area, a removal rate of the buffer layer is controlled to be lower than a removal rate of the first insulating layer.
4. The method for manufacturing a semiconductor device according to claim 1, wherein: The buffer layer includes at least two sub-buffer layers. When removing the first insulating layer in the scribe line area, the removal rate of at least part of the sub-buffer layers is controlled to be lower than the removal rate of the first insulating layer.
5. The method for manufacturing a semiconductor device according to claim 4, wherein: When removing the passivation layer in the scribe street area, a removal rate of at least a portion of the sub-buffer layer is controlled to be lower than a removal rate of the passivation layer.
6. The method for manufacturing a semiconductor device according to claim 4, wherein: The sub-buffer layer includes any one of silicon oxide, silicon nitride, polysilicon, silicon, germanium, and a silicon-germanium heterostructure, or a combination of at least two thereof.
7. The method for manufacturing a semiconductor device according to claim 1, wherein: The first insulating layer includes a first sub-insulating layer and a second sub-insulating layer; The first sub-insulating layer is located on the first surface of the semiconductor body; the first sub-insulating layer and the second insulating layer are located on the same layer; The second sub-insulating layer is located on a side of the first sub-insulating layer away from the first surface; the second sub-insulating layer and the interlayer insulating layer are located in the same layer.
8. A semiconductor device, characterized in that: The semiconductor device is manufactured by the method for manufacturing the semiconductor device according to any one of claims 1 to 7.
9. A chip structure, characterized in that: include: A semiconductor structure comprising a device core region and a scribe line region; the scribe line region is located on one side of the device core region; the semiconductor structure further comprises a semiconductor body, a first electrode, a first insulating layer, and a buffer layer; the semiconductor body comprises a first surface and a second surface arranged opposite to each other; the first insulating layer is located on the first surface and is at least located in the scribe line region; the first electrode is located on a side of the first insulating layer away from the semiconductor body and is located in the device core region; the buffer layer is located on a surface of the first electrode away from the semiconductor body, and the buffer layer is located in the device core region, the buffer layer being configured to be at least partially retained during removal of the first insulating layer and to cover the first electrode; a passivation layer, located on a side of the buffer layer away from the first electrode, and the passivation layer is located in the device core area and the scribe street area; The semiconductor body further includes a well region and a first region, the first region being of a first conductivity type and located on the first surface, the well region being of a second conductivity type and located on a side of the first region away from the first surface; the semiconductor body further includes a second insulating layer, the second insulating layer being located on the first surface; A gate is located on the second insulating layer away from the first surface, and the second insulating layer is used for insulating and spacing the semiconductor body and the gate; an interlayer insulating layer, located on a side of the gate away from the semiconductor body; The first electrode is a source electrode; the interlayer insulating layer is used to insulate and separate the gate electrode and the source electrode; The drain is located on the second surface of the semiconductor body.