Silicon-based vapor chamber and chip packaging method thereof

Abstract

The invention belongs to the field of heat dissipation devices, and relates to a silicon-based vapor chamber and a chip packaging method thereof. Comprising an upper shell plate and a lower shell plate, the upper shell plate and the lower shell plate form a closed cavity, the upper shell plate and the lower shell plate are both made of silicon materials, and the surface of the upper shell plate is provided with a boiling enhancing structure. Matching of thermal expansion coefficients is achieved between the silicon-based vapor chamber and the chip, the warping problem caused by thermal stress at high temperature is avoided, thermal resistance can be effectively reduced, and the performance and reliability of the immersed cooling device are improved. A boiling enhancing structure is manufactured on the surface of the silicon-based vapor chamber, surface modification can be achieved, and the boiling heat dissipation performance of the surface of the vapor chamber in the immersed cooling process is further enhanced.

Description

Technical Field

[0001] The present invention belongs to the field of heat dissipation devices, and in particular to a silicon-based heat spreader and a method for packaging chips therefor. Background Art

[0002] With the advent of the digital age, data centers, as critical hubs for information storage, processing, exchange, and transmission, are experiencing an annual increase in data processing volume. This places higher demands on the heat dissipation of high-power computing chips used in data center applications. Efficient heat dissipation is crucial for maintaining the long-term high performance of chips. Studies have shown that when a chip exceeds its normal operating temperature range, its failure rate increases by 10% for every 2°C increase in temperature. Two-phase immersion cooling has become widely used in data center cooling due to its low power consumption, compact size, and high heat dissipation efficiency compared to traditional air cooling and direct liquid cooling solutions.

[0003] Most existing chip packaging methods use metal materials as thermal expansion blocks (IHS, integrated heatspreader). There is a mismatch in thermal expansion coefficients between metal and Si chips. Only TIM (thermal grease or silicone) with poor thermal conductivity can be used between the two to alleviate interface cracking caused by interface stress mismatch, affecting the long-term reliability of the chip. If silicon is used as the thermal expansion block material, the interface unreliability caused by thermal mismatch can be eliminated. At the same time, since there is no mismatch in thermal expansion coefficients, a metal TIM with higher thermal conductivity can be used to further reduce thermal resistance. Compared with metal materials, silicon has a lower thermal conductivity (about 140W / (m·K)), but making silicon material into a heat spreader can greatly improve its equivalent thermal conductivity.

[0004] The heat spreader is a commonly used phase change heat transfer device that can efficiently dissipate heat from the heat source through the evaporation-condensation process of the internal working fluid. Applying it to immersion cooling can significantly increase the heat dissipation area of ​​high-power chips and improve the efficiency of immersion cooling. Summary of the Invention

[0005] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a silicon-based heat sink and a method for packaging chips for enhancing the efficiency of immersion cooling, thereby achieving matching of thermal expansion coefficients, avoiding warping problems caused by thermal stress at high temperatures, effectively reducing thermal resistance, and improving the performance and reliability of immersion cooling devices.

[0006] The technical solution adopted by the present invention to solve the technical problem is:

[0007] The first aspect of the present invention is to provide a silicon-based heat sink, comprising: an upper shell plate and a lower shell plate, wherein the upper shell plate and the lower shell plate form a closed chamber, the upper shell plate and the lower shell plate are both made of silicon, and the surface of the upper shell plate has a boiling enhancement structure.

[0008] Furthermore, a plurality of support columns of different heights are integrally formed in the closed chamber.

[0009] Furthermore, a nanoporous layer is formed on the inner wall of the closed chamber and the surface of the support column.

[0010] Furthermore, the upper shell plate and the lower shell plate are made of single crystal silicon or polycrystalline silicon, and the surface of the lower shell plate is polished, with a surface roughness Ra less than 0.1 μm, so as to achieve low contact thermal resistance between the chip and the lower shell plate.

[0011] Furthermore, the boiling enhancement structure on the surface of the upper shell plate is a microchannel array, the width of the microchannel is 2-200 μm, the depth is 10-500 μm, the spacing between adjacent microchannels is 10-500 μm, and the structure is formed by a deep reactive ion etching process or a metal assisted chemical etching process;

[0012] Alternatively, the boiling enhancement structure is a silicon microcolumn array, wherein the silicon microcolumns have a height of 10-500 μm and a diameter of 5-50 μm and are arranged periodically or non-periodically.

[0013] Alternatively, the boiling enhancement structure is a silicon nanowire, the silicon nanowire has a length of 0.5-5 μm and a diameter of 10-500 nm, and is formed by a metal-assisted chemical etching method.

[0014] Alternatively, the boiling enhancement structure is a silicon nanopore having a depth of 0.5-5 μm and a pore diameter of 10-1000 nm, and is formed by electrochemical etching.

[0015] Or the boiling enhancement structure is a silicon microstructure array with nanopores or nanowires modified on the surface. The structure can be summarized as a hierarchical micro-nano composite structure, and the sizes of the corresponding levels are the same as above.

[0016] Furthermore, the upper shell plate and the lower shell plate are connected by a wafer bonding method, and the bonding method includes one of anodic bonding, direct bonding or intermediate layer bonding.

[0017] Furthermore, the material of the nanoporous layer is silicon, the thickness thereof is 0.5-5 μm, the porosity thereof is 30-70%, and the pore diameter thereof is 10-1000 nm.

[0018] A second aspect of the present invention provides a method for packaging a chip using the aforementioned silicon-based vapor chamber, wherein the silicon-based vapor chamber and the chip are mechanically connected and heat-conducted by welding a metal thermal interface material (TIM), wherein the thermal conductivity of the metal thermal interface material (TIM) is greater than 80 W / (m·K).

[0019] Furthermore, the electronic chip and the substrate are electrically connected via micro-bumps. The silicon-based heat spreader and the substrate are bonded via bottom filling adhesive.

[0020] Furthermore, it also includes a silicon interposer, which includes TSV through holes. There are multiple chips, and the silicon interposer is located between the chip and the substrate, and is connected to the chip and the substrate through micro bumps.

[0021] The advantages and positive effects of the present invention are:

[0022] 1. The silicon-based vapor chamber of the present invention achieves matching of thermal expansion coefficients with the chip, avoiding warping problems caused by thermal stress at high temperatures, effectively reducing thermal resistance, and improving the performance and reliability of the immersion cooling device.

[0023] 2. The present invention manufactures a boiling enhancement structure on the surface of the silicon-based heat sink, which can achieve surface modification and further enhance the boiling heat dissipation performance of the heat sink surface during immersion cooling. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is a schematic diagram of the structure of a silicon-based vapor chamber according to the present invention;

[0025] Figure 2 This is a process flow chart for manufacturing a silicon-based vapor chamber according to the present invention;

[0026] Figure 3 This is a structural diagram of a single chip packaged in a silicon-based vapor chamber of the present invention;

[0027] Figure 4 This is a diagram of the structure of the silicon-based vapor chamber packaged with multiple chips of the present invention;

[0028] Figure 5 This is a comparison of the heat dissipation effects of the silicon-based heat sink structure of the present invention and other packaging structures. DETAILED DESCRIPTION

[0029] The present invention will be further described in detail below through specific examples. The following examples are only illustrative and not restrictive, and the scope of protection of the present invention cannot be limited thereto.

[0030] like Figure 1 The silicon-based heat spreader shown includes: an upper shell plate 1 and a lower shell plate 2, wherein the upper shell plate 1 and the lower shell plate 2 form a closed chamber, and both the upper shell plate 1 and the lower shell plate 2 are made of silicon. The surface of the upper shell plate 1 has a boiling enhancement structure 5, forming a heat exchange surface that is conducive to boiling enhancement, thereby improving the immersion cooling heat dissipation efficiency.

[0031] The upper shell plate 1 and the lower shell plate 2 are made of silicon material, which achieves matching of thermal expansion coefficients between the materials and the chip, reduces thermal resistance, and can effectively improve the heat dissipation efficiency of the chip and the stability of the heat dissipation system.

[0032] A plurality of support columns 3 of different heights are formed in a closed chamber to provide mechanical support to prevent the heat spreader from deforming and to promote condensation backflow.

[0033] A nanoporous layer 4 is formed on the inner wall of the closed chamber and the surface of the support column 3 to promote evaporation, condensation and reflux of the working medium and enhance the heat transfer effect of the heat plate.

[0034] The upper and lower shell plates 1 and 2 are made of single-crystal or polycrystalline silicon. The lower shell plate 2 is polished to a surface roughness Ra of less than 0.1 μm to achieve low thermal resistance to the chip. In a preferred embodiment, the upper and lower shell plates 1 and 2 are connected via wafer bonding, using anodic bonding, direct bonding, or interposer bonding.

[0035] As a preferred embodiment, the boiling enhancement structure 5 on the surface of the upper shell plate 1 is a microchannel array, the width of the microchannel is 2-200 μm, the depth is 10-500 μm, the spacing between adjacent microchannels is 10-500 μm, and the structure is formed by a deep reactive ion etching process or a metal assisted chemical etching process.

[0036] As a preferred embodiment, the silicon microcolumns have a height of 10-500 μm and a diameter of 5-50 μm, and are arranged periodically or aperiodically.

[0037] As a preferred embodiment, the silicon nanowires have a length of 0.5-5 μm and a diameter of 10-500 nm, and are formed by metal-assisted chemical etching.

[0038] As a preferred embodiment, the boiling enhancement structure is a silicon nanopore having a depth of 0.5-5 μm and a pore diameter of 10-1000 nm, and is formed by electrochemical etching.

[0039] As a preferred embodiment, the boiling enhancement structure is a silicon microstructure array with nanopores or nanowires modified on the surface. The structure can be summarized as a hierarchical micro-nano composite structure, and the sizes of the corresponding levels are the same as above.

[0040] As a preferred embodiment, the nanoporous layer 4 is made of silicon, has a thickness of 0.5-5 μm, a porosity of 30-70%, and a pore size of 10-1000 nm.

[0041] Figure 2This is a flow chart of the manufacturing process of the silicon-based heat spreader of the present invention. Figure (a) and Figure (d) are the raw materials of the lower shell plate and the upper shell plate of the silicon-based heat spreader, respectively. Figure (d) uses an electrochemical corrosion process to manufacture a boiling enhancement structure on the surface of the upper shell plate, resulting in Figure (e). Figure (a) and Figure (e) both use a composite mask to etch out the air chamber support structure and condensation backflow structure inside the heat spreader, resulting in Figure (b) and Figure (f), respectively. Figure (b) and Figure (e) both use an electrochemical corrosion process to manufacture a nanoporous structure on the inner surface of the heat spreader, resulting in Figure (c) and Figure (g), respectively. Figure (c) and Figure (g) are connected by wafer bonding to obtain Figure (h), a complete silicon-based heat spreader structure.

[0042] Figure 3 This diagram shows the structure of a silicon-based vapor chamber packaged with a single chip. The silicon-based vapor chamber 6 and chip 8 are mechanically connected and heat-conducted by welding a metal thermal interface material (TIM7) with a thermal conductivity greater than 80 W / (m·K). Microbumps 9 electrically connect the electronic chip 8 to the substrate 10. The silicon-based vapor chamber 6 and substrate 10 are bonded together by underfill 11.

[0043] The metal thermal interface material TIM7 can be made of indium foil, which has extremely good heat transfer performance and can significantly reduce the contact thermal resistance of the TIM. Other metal materials with excellent thermal conductivity can also be used.

[0044] Figure 4 This is a structural diagram of the silicon-based heat spreader packaged with multiple chips of the present invention. The multiple chips are supported by a silicon interposer 12, and the multiple chips are arranged at intervals. The silicon interposer 12 includes TSV through-holes 13. There are multiple chips 8. The silicon interposer 12 is located between the chip 8 and the substrate 10, and is connected to the chip 8 and the substrate 10 through micro-bumps 9.

[0045] This application tests the chip heat dissipation effect in six situations, such as Figure 5 As shown, the first type is a bare chip, the second type is chip + MP (a boiling-enhanced silicon micropillar array is fabricated on the chip surface), the third type is a Si structure (a solid Si thermal expansion block is used and connected to the chip via indium foil), the fourth type is a SiMP structure (a solid Si thermal expansion block is used, and a boiling-enhanced silicon micropillar array is fabricated on the surface of the solid Si thermal expansion block and connected to the chip via indium foil), the fifth type is a VC structure (a flat Si-based heat spreader is used as the thermal expansion block and connected to the chip via indium foil), and the sixth type is a VCMP structure (a Si-based heat spreader is used as the thermal expansion block and a boiling-enhanced silicon micropillar array is fabricated on the surface of the thermal expansion block and connected to the chip via indium foil). During the experiment, TDP is defined as the power when the chip reaches 95°C. The higher the TDP value, the better the heat dissipation effect.

[0046] From the test results, it can be seen that the silicon-based heat sink of the present application has the best heat dissipation effect.

[0047] Test Type TDP(W) Bare Chip 70.2 Chip+MP 144 Si structure 134.2 SiMP structure 180.5 VC Structure 336.7 VCMP Structure 373.7

[0048] The above description is only a preferred embodiment of the present invention. It should be pointed out that a person skilled in the art can make several modifications and improvements without departing from the inventive concept, and these all fall within the scope of protection of the present invention.

Claims

1. A silicon-based vapor chamber, characterized in that: include: An upper shell plate (1) and a lower shell plate (2), wherein the upper shell plate (1) and the lower shell plate (2) form a closed chamber, the upper shell plate (1) and the lower shell plate (2) are both made of silicon, and the surface of the upper shell plate (1) has a boiling enhancement structure (5).

2. The silicon-based vapor chamber according to claim 1, wherein: A plurality of support columns (3) of different heights are formed in a closed chamber.

3. The silicon-based vapor chamber according to claim 2, wherein: A nanoporous layer (4) is formed on the inner wall of the closed chamber and the surface of the support column (3).

4. The silicon-based vapor chamber according to claim 1, wherein: The upper shell plate (1) and the lower shell plate (2) are made of single crystal silicon or polycrystalline silicon. The surface of the lower shell plate (2) is polished, and the surface roughness Ra is less than 0.1 μm, so as to achieve low contact thermal resistance between the chip and the lower shell plate.

5. The silicon-based vapor chamber according to claim 1, wherein: The boiling enhancement structure (5) on the surface of the upper shell (1) is a microchannel array, wherein the width of the microchannel is 2-200 μm, the depth is 10-500 μm, the spacing between adjacent microchannels is 10-500 μm, and the structure is formed by a deep reactive ion etching process or a metal assisted chemical etching process; Or the boiling enhancement structure (5) is a silicon microcolumn array, wherein the silicon microcolumns have a height of 10-500 μm and a diameter of 5-50 μm and are arranged periodically or non-periodically. Or the boiling enhancement structure (5) is a silicon nanowire, the length of the silicon nanowire is 0.5-5 μm, the diameter is 10-500 nm, and it is formed by metal-assisted chemical etching. Or the boiling enhancement structure (5) is a silicon nanopore, the silicon nanopore has a depth of 0.5-5 μm and a pore diameter of 10-1000 nm, and is formed by electrochemical etching. Or the boiling enhancement structure (5) is a silicon microstructure array with nanopores or nanowires modified on the surface. The structure can be summarized as a hierarchical micro-nano composite structure, and the sizes of the corresponding levels are the same as above.

6. The silicon-based vapor chamber according to claim 1, wherein: The upper shell plate (1) and the lower shell plate (2) are connected by a wafer bonding method, and the bonding method includes one of anodic bonding, direct bonding or intermediate layer bonding.

7. The silicon-based vapor chamber according to claim 1, wherein: The material of the nanoporous layer (4) is silicon, the thickness thereof is 0.5-5 μm, the porosity thereof is 30-70%, and the pore diameter thereof is 10-1000 nm.

8. The method for packaging a chip using a silicon-based vapor chamber according to any one of claims 1 to 7, wherein: Mechanical connection and heat conduction are achieved between the silicon-based heat spreader (6) and the chip (8) by welding a metal thermal interface material TIM (7), and the thermal conductivity of the metal thermal interface material TIM (7) is greater than 80 W / (m·K).

9. The method for packaging a chip with a silicon-based vapor chamber according to claim 8, wherein: The electronic chip (8) and the substrate (10) are electrically connected via micro-bumps (9). The silicon-based heat spreader (6) and the substrate (10) are bonded via bottom filling glue (11).

10. The method for packaging a chip with a silicon-based vapor chamber according to claim 9, wherein: The invention also includes a silicon intermediary layer (12), wherein the silicon intermediary layer (12) includes a TSV through hole (13), and the chip (8) is multiple. The silicon intermediary layer (12) is located between the chip (8) and the substrate (10), and is connected to the chip (8) and the substrate (10) through micro bumps (9).

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