Interposer device and semiconductor package device

Abstract

An interposer device for providing a plurality of communication signal transmissions between two wafers includes a plurality of wiring layers. The plurality of circuit layers are electrically connected between the two wafers and are arranged along a vertical direction. The plurality of circuit layers transmit communication signals respectively by taking a first direction or a second direction which are opposite to each other as signal transmission directions. The first and second directions are different from the vertical direction. Each of the plurality of circuit layers comprises a plurality of signal wires and grounding wires which are arranged alternately. A plurality of projections of the plurality of signal leads in one of the plurality of line layers on the adjacent line layers along the vertical direction are overlapped with the plurality of grounding leads in the adjacent line layers. In any three of the plurality of circuit layers arranged in sequence, the signal transmission directions of the foremost circuit layer and the last circuit layer are opposite to each other. Interposer devices of the present disclosure may attenuate communication crosstalk between wires.

Description

Technical Field

[0001] The present disclosure relates to signal interference technology in an interposer device, and more particularly to an interposer device and a semiconductor package device that utilize destructive interference to reduce communication crosstalk between conductive lines. Background Art

[0002] In the field of advanced packaging technology, 2.5-dimensional (2.5D) interposer packaging, which lies between two-dimensional (2D) and three-dimensional (3D), is widely used. In 2.5D interposer packaging technology, multiple chips are placed on a substrate via an interposer device, allowing different chips to communicate with each other through the interposer device.

[0003] However, in interposer devices, coupling between wires often causes crosstalk, which in turn affects the quality of communication signals on the wires. Furthermore, when crosstalk between wires reaches constructive interference, it degrades the quality of communication signals on the wires. Therefore, how to mitigate the effects of constructive interference crosstalk is a topic in this field. Summary of the Invention

[0004] The present disclosure document provides an intermediate layer device for providing multiple communication signal transmission between two chips, including multiple circuit layers. The multiple circuit layers are electrically connected between the two chips and arranged along the vertical direction, and each of the multiple circuit layers transmits multiple communication signals in the first direction or the second direction as the signal transmission direction. The first direction is opposite to the second direction, and the first direction and the second direction are different from the vertical direction. Each of the multiple circuit layers includes a plurality of signal conductors and ground conductors arranged alternately with each other. The multiple projections of the multiple signal conductors in one of the multiple circuit layers on the adjacent one of the multiple circuit layers along the vertical direction overlap the multiple ground conductors in the adjacent one of the multiple circuit layers. Among any three of the multiple circuit layers arranged in sequence, the signal transmission direction of the frontmost circuit layer is opposite to the signal transmission direction of the last circuit layer.

[0005] In some embodiments of the interposer device, a line width of the plurality of signal conductive lines is less than or equal to a line width of the plurality of ground conductive lines.

[0006] In some embodiments of the interposer device, distances between each of the plurality of signal conductors and an adjacent one of the plurality of ground conductors are the same as each other.

[0007] In some embodiments of the interposer device, the interposer device further includes a redistribution layer (RDL), which is vertically disposed on the plurality of circuit layers and includes a plurality of signal contacts, each of which is electrically connected to the two chips via a microbump.

[0008] In some embodiments of the interposer device, the interposer device further includes a plurality of through-holes embedded between the redistribution layer and the plurality of wiring layers for electrically connecting the plurality of signal contacts to the plurality of signal conductors.

[0009] In some embodiments of the interposer device, the interposer device further includes a ground mesh coupled to the plurality of ground conductors for providing a ground voltage to the plurality of ground conductors. The ground mesh includes two portions, the two portions of the ground mesh at least partially surrounding the plurality of signal conductors.

[0010] In some embodiments of the interposer device, the number of the plurality of circuit layers is an even number. In the vertical direction, the signal transmission direction of the topmost circuit layer is opposite to that of its adjacent layers, and the signal transmission direction of the bottommost circuit layer is opposite to that of its adjacent layers.

[0011] In some embodiments of the interposer device, the number of the circuit layers is an odd number. In the vertical direction, the signal transmission direction of the topmost circuit layer is opposite to that of its adjacent layers, and the signal transmission direction of the bottommost circuit layer is the same as that of its adjacent layers.

[0012] In some embodiments of the interposer device, the number of the circuit layers is an odd number. In the vertical direction, the signal transmission direction of the topmost circuit layer is the same as that of its adjacent layers, and the signal transmission direction of the bottommost circuit layer is opposite to that of its adjacent layers.

[0013] In some embodiments of the interposer device, the interposer device further includes a plurality of dielectric layers disposed between the plurality of circuit layers to shield the plurality of circuit layers.

[0014] The present disclosure document provides a semiconductor packaging device comprising a first chip, a second chip, a packaging substrate and an interposer device. The second chip is used to transmit multiple communication signals with the first chip through multiple channels. The interposer device is electrically connected to the first chip, the second chip and the packaging substrate, and comprises multiple circuit layers. The multiple circuit layers are electrically connected between the first chip and the second chip to serve as multiple channels and are arranged along a vertical direction. Each of the multiple circuit layers transmits multiple communication signals in a first direction or a second direction as a signal transmission direction. The first direction is opposite to the second direction, and the first direction and the second direction are different from the vertical direction. Each of the multiple circuit layers comprises a plurality of signal conductors and ground conductors arranged alternately with each other. The plurality of signal conductors in one of the multiple circuit layers have a plurality of projections on an adjacent one of the multiple circuit layers along the vertical direction that overlap with the plurality of ground conductors in the adjacent one of the multiple circuit layers. Among any three of the multiple circuit layers arranged in sequence, the signal transmission direction of the frontmost circuit layer is opposite to the signal transmission direction of the last circuit layer.

[0015] In some embodiments of the semiconductor package device, a line width of the plurality of signal conductive lines is smaller than or equal to a line width of the plurality of ground conductive lines.

[0016] In some embodiments of the semiconductor package device, distances between each of the plurality of signal conductors and an adjacent one of the plurality of ground conductors are the same.

[0017] In some embodiments of the semiconductor package device, the interposer device further includes a redistribution layer (RDL), which is vertically disposed on the plurality of circuit layers and includes a plurality of signal contacts, each of which is electrically connected to the two chips via a microbump.

[0018] In some embodiments of the semiconductor package device, the interposer device further includes a plurality of through-holes embedded between the redistribution layer and the plurality of wiring layers for electrically connecting the plurality of signal contacts to the plurality of signal conductors.

[0019] In some embodiments of the semiconductor package device, the interposer device further includes a ground grid coupled to the plurality of ground conductors for providing a ground voltage to the plurality of ground conductors. The ground grid includes two portions, the two portions of the ground grid at least partially surrounding the plurality of signal conductors.

[0020] In some embodiments of the semiconductor package device, the number of the plurality of circuit layers is an even number. In the vertical direction, the signal transmission direction of the topmost circuit layer is opposite to that of its adjacent layers, and the signal transmission direction of the bottommost circuit layer is opposite to that of its adjacent layers.

[0021] In some embodiments of the semiconductor package device, the number of the plurality of circuit layers is an odd number. In the vertical direction, the signal transmission direction of the topmost circuit layer is opposite to that of its adjacent layers, and the signal transmission direction of the bottommost circuit layer is the same as that of its adjacent layers.

[0022] In some embodiments of the semiconductor package device, the number of the plurality of circuit layers is an odd number. In the vertical direction, the signal transmission direction of the topmost circuit layer is the same as that of its adjacent layers, and the signal transmission direction of the bottommost circuit layer is opposite to that of its adjacent layers.

[0023] In some embodiments of the semiconductor package device, the interposer device further includes a plurality of dielectric layers disposed between the plurality of circuit layers to shield the plurality of circuit layers.

[0024] Through the interposer device and semiconductor packaging device disclosed in the present document, the signal transmission directions of the signal conductors in the circuit layer can be arranged according to specific rules, so that the crosstalk between adjacent signal conductors is reduced due to destructive interference, thereby improving the performance of the signal conductors in signal transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] To make the above and other objects, features, advantages and embodiments of the present disclosure more apparent, the accompanying drawings are described as follows:

[0026] Figure 1 is a schematic diagram of a semiconductor packaging device according to some embodiments of the present disclosure;

[0027] Figure 2 A cross-sectional view of an interposer device according to some embodiments of the present disclosure;

[0028] Figure 3A is a schematic diagram illustrating a signal transmission direction in an interposer device according to some examples;

[0029] Figure 3B Based on Figure 3A Schematic diagram of the crosstalk phenomenon of the signal conductors shown in the example;

[0030] Figure 4A is a schematic diagram illustrating a signal transmission direction in an interposer device according to some embodiments of the present disclosure;

[0031] Figure 4B Based on Figure 4A Schematic diagram of the crosstalk phenomenon of the signal conductors shown in the example;

[0032] Figure 5 is a schematic diagram illustrating a signal transmission direction in an interposer device according to some other embodiments of the present disclosure; and

[0033] Figure 6 FIG. 1 is a schematic diagram illustrating the signal transmission direction of signal conductive lines according to some further embodiments of the present disclosure.

[0034]

Explanation of symbols

[0035] 100:Semiconductor packaging device

[0036] 110: Intermediary device

[0037] 120:Packaging substrate

[0038] 1101: first surface

[0039] 1102: Second surface

[0040] A-A': section line

[0041] BP: Micro Bump

[0042] C1, C2: Chip

[0043] CT:Signal contact

[0044] G: Grounding conductor

[0045] GM: Grounding Grid

[0046] M0: Redistribution Layer

[0047] M1~M6: circuit layer

[0048] S1~S12: Signal wires

[0049] VIA: Through hole

[0050] X, Y, Z: direction DETAILED DESCRIPTION

[0051] The following will illustrate the embodiments of the present disclosure with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals represent the same or similar elements or method flows.

[0052] In this disclosure, when an element is referred to as being "connected", it may refer to being "electrically connected" or "optically connected", and when an element is referred to as being "coupled", it may refer to being "electrically coupled" or "optically coupled". "Connected" or "coupled" may also be used to indicate that two or more elements operate or interact with each other. Unless otherwise specified in the context, "one" and "the" may refer to one or more. It will be further understood that the words "comprise", "include", "have" and similar words used herein indicate the features, regions, integers, steps, operations, elements and / or components described therein, but do not exclude one or more other features, regions, integers, steps, operations, elements, components and / or groups thereof described therein or in addition thereto.

[0053] Figure 1 FIG. 1 is a schematic diagram of a semiconductor package device 100 according to some embodiments of the present disclosure. In some embodiments, the semiconductor package device 100 includes an interposer device 110 , a plurality of semiconductor devices (eg, chips C1 and C2 ), and a package substrate 120 .

[0054] In some embodiments, chips C1 and C2 are electrically connected to a first surface 1101 of interposer device 110 to transmit communication signals between them via channels CHA-CHF in interposer device 110. Package substrate 120 is electrically connected to a second surface 1102 of interposer device 110 to transmit power to chips C1 and C2 through interposer device 110. Second surface 1102 is opposite to first surface 1101.

[0055] For details about the internal structure of the interposer device 110, please refer to Figure 2 . Figure 2A cross-sectional view of an interposer device 110 along section line AA' is shown according to some embodiments of the present disclosure. In some embodiments, the interposer device 110 includes a redistribution layer M0, circuit layers M1-M6, and dielectric layers D1-D5. The redistribution layer M0 is disposed vertically (direction Z) above the circuit layers M1-M6. The redistribution layer M0 is provided with a plurality of signal contacts CT, each of which is electrically connected to a chip C1 and a chip C2 via a microbump BP. This allows chip C1 and chip C2 to communicate signals with each other through the interposer device 110.

[0056] Circuit layers M1 - M6 extend in the horizontal direction (directions X, Y) and are sequentially arranged from top to bottom along the vertical direction (direction Z) to implement channels CHA - CHF in the interposer device 110 and provide signal communication between chips C1 and C2 .

[0057] Each of the circuit layers M1-M6 includes a plurality of signal conductors and a plurality of ground conductors, and these signal conductors and ground conductors are alternately arranged in each circuit layer M1-M6. Figure 2 Taking the embodiment as an example, the circuit layer M1 includes a signal wire S1, a ground wire G, a signal wire S2, and a ground wire G arranged in sequence; the circuit layer M2 includes a ground wire G, a signal wire S3, a ground wire G, and a signal wire S4 arranged in sequence; the circuit layer M3 includes a signal wire S5, a ground wire G, a signal wire S6, and a ground wire G arranged in sequence; the circuit layer M4 includes a ground wire G, a signal wire S7, a ground wire G, and a signal wire S8 arranged in sequence; the circuit layer M5 includes a signal wire S9, a ground wire G, a signal wire S10, and a ground wire G arranged in sequence; the circuit layer M6 includes a ground wire G, a signal wire S11, a ground wire G, and a signal wire S12 arranged in sequence.

[0058] In addition, for any of the circuit layers M1 to M6, the projection of the signal conductor along the vertical direction (direction Z) on the adjacent circuit layer will overlap the ground conductor in the adjacent circuit layer. Figure 2 For example, the projections of the signal wires S1 and S2 in the circuit layer M1 along the direction Z on the circuit layer M2 respectively overlap the two ground wires G in the circuit layer M2.

[0059] In some embodiments, the signal conductors S1-S12 have the same line width in direction X, and the ground conductor G has the same line width in direction X. In some preferred embodiments, the line width of the signal conductor is equal to the line width of the ground conductor, but the present disclosure is not limited thereto. In some other embodiments of the present disclosure, the line width of the signal conductor may not be equal to (e.g., smaller than) the line width of the ground conductor.

[0060] In some embodiments, the distances between the signal conductors S1-S12 and the adjacent ground conductors G in the direction X are the same. Figure 2 For example, in the circuit layer M1, the distance between the signal conductor S1 and its adjacent (ie, right) ground conductor G is equal to the distance between the signal conductor S2 and its adjacent (ie, left or right) ground conductor G.

[0061] like Figure 2 As shown, since the signal conductors S1 to S12 and the plurality of ground conductors G extend along the direction Y, the communication signal can be transmitted in the forward direction (e.g., into the drawing) or the reverse direction (e.g., out of the drawing) along the direction Y. In some embodiments, the communication signals transmitted by the signal conductors located in the same circuit layer are in the same direction. In other words, Figure 2 For example, the communication signals transmitted by the signal wires S1 and S2 are in the same direction, the communication signals transmitted by the signal wires S3 and S4 are in the same direction, and so on.

[0062] Dielectric layers D1-D5 are respectively disposed between circuit layers M1-M6. For example, dielectric layer D1 is disposed between circuit layers M1 and M2, dielectric layer D2 is disposed between circuit layers M2 and M3, and so on. Dielectric layers D1-D5 serve to shield circuit layers M1-M6, thereby reducing interference between communication signals within circuit layers M1-M6.

[0063] In some embodiments, the interposer device 110 further includes a plurality of vias (VIAs) embedded between the redistribution layer (RDL) M0 and the wiring layers (M1-M6) to electrically connect the signal contacts (CT) of the RDL M0 to the signal conductors (S1-S12) in the wiring layers (M1-M6).

[0064] In some embodiments, the interposer device 110 further includes a ground grid GM. The ground grid GM includes two parts (eg, Figure 2 The two ground meshes GM in FIG. 2 at least partially surround the signal conductors S1 to S12. In addition, the ground mesh GM is connected to the ground conductor G, so the ground mesh GM can be used to provide a ground voltage to the ground conductor G.

[0065] As mentioned above, since multiple communication signals can be transmitted in two opposite directions in the signal conductors S1-S12, for example, chip C1 can send communication signals to chip C2 through a portion of the signal conductors S1-S12, and receive communication signals from chip C2 through another portion of the signal conductors S1-S12. Figure 3A , Figure 3A Schematic diagram of signal transmission direction in an interposer device according to some examples. For the sake of simplicity of the drawings, Figure 3A 、 Figure 4A 、 Figure 5 、 Figure 6 The redistribution layer M0, dielectric layers D1-D5 and through vias VIA are omitted.

[0066] Figure 3A The example shown in the figure is often implemented as a signal direction configuration method in a common interposer device. Specifically, in the interposer device 110, the signal conductors (e.g., signal conductors S1-S6) in the upper half (e.g., wiring layers M1-M3) are configured as TX signal lines (i.e., conductors for sending communication signals, indicated by dots), while the signal conductors (e.g., signal conductors S7-S12) in the lower half (e.g., wiring layers M4-M6) are configured as RX signal lines (i.e., conductors for receiving communication signals, indicated by slashes). In this way, chip C1 can send communication signals to chip C2 via signal conductors S1-S6, and receive communication signals from chip C2 via signal conductors S7-S12. In some common and unillustrated examples, the configuration of the communication signal transmission direction can be opposite to the aforementioned example.

[0067] However, the common communication signal direction configuration mentioned above may cause crosstalk between signal conductors to achieve constructive interference, thereby affecting the quality of communication signals. Figure 3B , Figure 3B Based on Figure 3A FIG. 1 is a schematic diagram illustrating the crosstalk phenomenon around the signal conductor S3 as shown in FIG.

[0068] exist Figure 3B In the diagram, the arrows surrounding signal wires S1, S2, S5, and S6 represent the direction of the magnetic field generated by crosstalk with signal wire S3. Since signal wires S1, S2, S5, and S6 are all configured as TX signal lines, the signal transmission directions of these wires are identical, and therefore the direction of the magnetic field generated by crosstalk with signal wire S3 is also identical. In this case, the crosstalk from signal wires S1 and S5 constructively interferes with signal wire S3, while the crosstalk from signal wires S2 and S6 constructively interferes with signal wire S3, thereby affecting the signal transmission performance of signal wire S3.

[0069] In order to improve the above phenomenon, this disclosure document provides other communication signal direction configuration methods. Figure 4A , Figure 4A FIG. 1 is a schematic diagram illustrating a signal transmission direction in an interposer device 110 according to some embodiments of the present disclosure.

[0070] In some embodiments, the signal transmission directions of each signal conductor buried in the same circuit layer are the same. Figure 4AFor example, the signal transmission directions of the signal conductors S1 and S2 in the circuit layer M1 are the same, the signal transmission directions of the signal conductors S3 and S4 in the circuit layer M2 are the same, and so on.

[0071] exist Figure 4A In the embodiment, the signal conductors S1 and S2 in the topmost circuit layer M1 are configured as TX signal lines, the signal conductors S3 to S6 in the circuit layers M2 and M3 are configured as RX signal lines, the signal conductors S7 to S10 in the circuit layers M4 and M5 are configured as TX signal lines, and the signal conductors S11 and S12 in the bottommost circuit layer M6 are configured as RX signal lines. Therefore, the circuit layers M1, M4, and M5 are used to send communication signals, while the circuit layers M2, M3, and M6 are used to receive communication signals. Furthermore, chip C1 can send communication signals to chip C2 via the signal conductors S1 to S2 and S7 to S10 in the circuit layers M1, M4, and M5, and receive communication signals from chip C2 via the signal conductors S3 to S6 and S11 to S12 in the circuit layers M2, M3, and M6.

[0072] In some embodiments not shown, the communication signal transmission direction of the interposer device 110 may be configured in the same manner as Figure 4A In other words, the interposer device 110 may be configured such that the circuit layers M1 , M4 , and M5 are used to receive communication signals, while the circuit layers M2 , M3 , and M6 are used to send communication signals.

[0073] Figure 4B Based on Figure 4A Schematic diagram of the crosstalk phenomenon around the signal conductor S3 according to the embodiment of FIG. Figure 4B In the figure, the arrows around the signal wires S1, S2, S5 and S6 represent the direction of the magnetic field caused by crosstalk with the signal wire S3. Since the signal wires S1 and S2 are configured as TX signal wires, and the signal wires S5 and S6 are configured as RX signal wires, the signal transmission direction of the signal wires S1 and S2 is opposite to that of the signal wires S5 and S6, so the direction of the magnetic field caused by crosstalk with the signal wire S3 is also opposite (e.g. Figure 4B (as shown). In this case, the crosstalk from signal conductors S1 and S5 to signal conductor S3 will cause destructive interference, while the crosstalk from signal conductors S2 and S6 to signal conductor S3 will also cause destructive interference. Therefore, by configuring the communication signal transmission direction, the crosstalk effect from signal conductors S1, S2, S5, and S6 on signal conductor S3 can be reduced, thereby effectively improving the communication signal quality on signal conductor S3.

[0074] In some embodiments, the interposer device 110 may have other numbers of circuit layers. Figure 5 , Figure 5 FIG. 1 is a schematic diagram illustrating the signal transmission direction in the interposer device 110 according to some other embodiments of the present disclosure.

[0075] exist Figure 5 In the embodiment, the interposer device 110 has only four circuit layers (i.e., circuit layers M1 to M4). The signal conductors S1 and S2 in the topmost circuit layer M1 are configured as TX signal lines, the signal conductors S3 to S6 in the circuit layers M2 and M3 are configured as RX signal lines, and the signal conductors S7 and S8 in the bottommost circuit layer M4 are configured as TX signal lines. Therefore, circuit layers M1 and M4 are used to send communication signals, while circuit layers M2 and M3 are used to receive communication signals. Furthermore, chip C1 can send communication signals to chip C2 via the signal conductors S1 to S2 and S7 to S8 in the circuit layers M1 and M4, and receive communication signals from chip C2 via the signal conductors S3 to S6 in the circuit layers M2 and M3.

[0076] In some embodiments not shown, the communication signal transmission direction of the interposer device 110 may be configured in the same manner as Figure 5 In other words, the interposer device 110 may be configured such that the circuit layers M1 and M4 are used to receive communication signals, while the circuit layers M2 and M3 are used to send communication signals.

[0077] comprehensive Figure 4A and Figure 5 In the embodiment, when the number of circuit layers in the interposer device 110 is an even number, among the three circuit layers arranged in sequence, the signal transmission direction of the front circuit layer will be opposite to the signal transmission direction of the last circuit layer. For example, for the circuit layers M1 to M3 arranged in sequence, the front circuit layer M1 is used to send communication signals, and the last circuit layer M3 is used to receive communication signals. In addition, for the top and bottom circuit layers, their communication signal directions are opposite to the communication signal directions of the adjacent circuit layers. Figure 5 For example, the signal transmission direction of the topmost circuit layer M1 is opposite to that of the adjacent circuit layer M2, and the signal transmission direction of the bottommost circuit layer M4 is opposite to that of the adjacent circuit layer M3.

[0078] Figure 6 FIG. 1 is a schematic diagram illustrating the signal transmission direction in the interposer device 110 according to some other embodiments of the present disclosure. Figure 6In the embodiment of the present invention, there are five circuit layers in the interposer device 110 (i.e., circuit layers M1 to M5). The signal conductors S1 and S2 in the topmost circuit layer M1 are configured as TX signal lines, the signal conductors S3 to S6 in the circuit layers M2 and M3 are configured as RX signal lines, and the signal conductors S7 to S10 in the circuit layer M4 and the bottommost circuit layer M5 are configured as TX signal lines. Therefore, the circuit layers M1, M4, and M5 are used to send communication signals, while the circuit layers M2 and M3 are used to receive communication signals. Furthermore, the chip C1 can send communication signals to the chip C2 through the signal conductors S1 to S2 and S7 to S8 in the circuit layers M1, M4, and M5, and receive communication signals from the chip C2 through the signal conductors S3 to S6 in the circuit layers M2 and M3.

[0079] In some embodiments not shown, the communication signal transmission direction of the interposer device 110 may be configured in the same manner as Figure 6 In other words, the interposer device 110 may be configured such that the circuit layers M1 , M4 , and M5 are used to receive communication signals, while the circuit layers M2 and M3 are used to send communication signals.

[0080] In some embodiments not shown, the communication signal transmission direction in the intermediate layer device 110 can also be configured as the circuit layers M1, M2, and M5 are used to receive communication signals, while the circuit layers M3 and M4 are used to send communication signals; or the circuit layers M1, M2, and M5 are used to send communication signals, while the circuit layers M3 and M4 are used to receive communication signals.

[0081] Figure 6 Examples and Figure 4A 、 Figure 5 The embodiment is similar in that when the number of circuit layers in the interposer device 110 is an odd number, in the three sequentially arranged circuit layers, the signal transmission direction of the frontmost circuit layer is also opposite to the signal transmission direction of the last circuit layer.

[0082] However, with Figure 4A 、 Figure 5 The difference between the embodiment of FIG. 1 and FIG. 2 is that when the number of circuit layers in the interposer device 110 is an odd number, for the topmost and bottommost circuit layers (eg, Figure 6 For the circuit layers M1 and M5 in FIG, the communication signal direction of one of them is opposite to the communication signal direction of the adjacent circuit layer, while the communication signal direction of the other one is the same as the communication signal direction of the adjacent circuit layer. Figure 6 As shown, the signal transmission direction of the topmost circuit layer M1 is opposite to that of the adjacent circuit layer M2 , while the signal transmission direction of the circuit layer M5 is the same as that of the adjacent circuit layer M4 .

[0083] It should be noted that the number of circuit layers and the number of signal conductors and ground conductors in each circuit layer in this disclosure are merely examples and are not intended to limit this disclosure. The number of other circuit layers and the number of signal conductors and ground conductors in each circuit layer are all within the scope of this disclosure provided that the following configuration conditions are met: (1) in three sequentially arranged circuit layers, the signal transmission direction of the frontmost circuit layer is opposite to the signal transmission direction of the rearmost circuit layer; (2) when the number of circuit layers is an even number, the communication signal direction of the topmost and bottommost circuit layers is opposite to the communication signal direction of the adjacent circuit layers; and (3) when the number of circuit layers is an odd number, the communication signal direction of one of the topmost and bottommost circuit layers is opposite to the communication signal direction of the adjacent circuit layers, while the communication signal direction of the other is the same as the communication signal direction of the adjacent circuit layers.

[0084] The semiconductor package device 100 of the present disclosure can be used to configure the signal transmission directions of signal conductors within each circuit layer according to specific rules for interposer devices 110 having different numbers of circuit layers. This reduces crosstalk between adjacent signal conductors due to destructive interference, thereby improving the quality of communication signals within the signal conductors. Furthermore, because the semiconductor package device 100 proposed in the present disclosure only changes the signal transmission direction of the interposer device 110, it does not require significant changes to the internal structure of the semiconductor package device 100, thereby reducing manufacturing costs.

[0085] The above are merely preferred embodiments of the present disclosure. Various modifications and equivalent variations of the present disclosure are possible without departing from the scope or spirit of the present disclosure. In summary, all modifications and equivalent variations of the present disclosure within the scope of the following claims are intended to be encompassed by the present disclosure.

Claims

1. An interposer device, characterized in that: It is used to provide multiple communication signal transmission between two chips, including: A plurality of circuit layers are electrically connected between the two chips and arranged along a vertical direction. The plurality of circuit layers each transmits the plurality of communication signals in a first direction or a second direction as a signal transmission direction, wherein the first direction is opposite to the second direction, and the first direction and the second direction are different from the vertical direction. Each of the plurality of circuit layers includes a plurality of signal conductors and ground conductors that are alternately arranged. Projections of the signal conductors in one of the circuit layers along the vertical direction on an adjacent one of the circuit layers overlap the ground conductors in the adjacent one of the circuit layers, and In any three of the plurality of circuit layers arranged in sequence, the signal transmission direction of a frontmost circuit layer is opposite to the signal transmission direction of a rearmost circuit layer.

2. The interposer device according to claim 1, wherein: The line widths of the plurality of signal conductors are smaller than or equal to the line widths of the plurality of ground conductors.

3. The interposer device according to claim 1, wherein: The distances between each of the plurality of signal conductors and an adjacent one of the plurality of ground conductors are the same.

4. The interposer device according to claim 1, wherein: The invention also comprises a redistribution layer, wherein the redistribution layer is arranged on the plurality of circuit layers in the vertical direction and comprises a plurality of signal contacts, and each signal contact is electrically connected to the two chips through a micro bump.

5. The interposer device according to claim 4, wherein: The device further comprises a plurality of through holes, which are buried between the redistribution layer and the plurality of wiring layers and are used to electrically connect the plurality of signal contacts to the plurality of signal wires.

6. The interposer device according to claim 1, wherein: The invention also includes a ground grid coupled to the plurality of ground wires for providing a ground voltage to the plurality of ground wires, wherein the ground grid includes two parts, and the two parts of the ground grid at least partially surround the plurality of signal wires.

7. The interposer device according to claim 1, wherein: The number of the multiple circuit layers is an even number, and in the vertical direction, the signal transmission direction of the topmost of the multiple circuit layers is opposite to that of its adjacent layers, and the signal transmission direction of the bottommost of the multiple circuit layers is opposite to that of its adjacent layers.

8. The interposer device according to claim 1, wherein: The number of the multiple circuit layers is an odd number. In the vertical direction, the signal transmission direction of the topmost circuit layer is opposite to that of its adjacent layers, and the signal transmission direction of the bottommost circuit layer is the same as that of its adjacent layers.

9. The interposer device according to claim 1, wherein: The number of the multiple circuit layers is an odd number. In the vertical direction, the signal transmission direction of the topmost circuit layer is the same as that of its adjacent layers, and the signal transmission direction of the bottommost circuit layer is opposite to that of its adjacent layers.

10. The interposer device according to claim 1, wherein: It also includes a plurality of dielectric layers, which are arranged between the plurality of circuit layers and used for shielding the plurality of circuit layers.

11. A semiconductor packaging device, characterized in that: Include: a first chip; a second chip, configured to transmit a plurality of communication signals to the first chip through a plurality of channels; a packaging substrate; and An interposer device is electrically connected to the first chip, the second chip, and the package substrate, and includes a plurality of circuit layers, wherein the plurality of circuit layers are electrically connected between the first chip and the second chip to serve as the plurality of channels and are arranged along a vertical direction. The plurality of circuit layers each transmits the plurality of communication signals in a first direction or a second direction as a signal transmission direction, wherein the first direction is opposite to the second direction, and the first direction and the second direction are different from the vertical direction. Each of the plurality of circuit layers includes a plurality of signal conductors and ground conductors that are alternately arranged. Projections of the signal conductors in one of the circuit layers along the vertical direction on an adjacent one of the circuit layers overlap the ground conductors in the adjacent one of the circuit layers, and In any three of the plurality of circuit layers arranged in sequence, the signal transmission direction of a frontmost circuit layer is opposite to the signal transmission direction of a rearmost circuit layer.

12. The semiconductor package device according to claim 11, wherein The line widths of the plurality of signal conductors are smaller than or equal to the line widths of the plurality of ground conductors.

13. The semiconductor package device according to claim 11, wherein The distances between each of the plurality of signal conductors and an adjacent one of the plurality of ground conductors are the same.

14. The semiconductor package device according to claim 11, wherein The interposer device further includes a redistribution layer, which is arranged on the plurality of circuit layers in the vertical direction and includes a plurality of signal contacts, and each signal contact is electrically connected to the two chips through a micro bump.

15. The semiconductor package device according to claim 14, wherein The intermediary layer device further includes a plurality of through holes, which are buried between the redistribution layer and the plurality of wiring layers to electrically connect the plurality of signal contacts to the plurality of signal wires.

16. The semiconductor package device according to claim 11, wherein The interposer device further includes a ground grid coupled to the plurality of ground conductors for providing a ground voltage to the plurality of ground conductors. The ground grid includes two parts, and the two parts of the ground grid at least partially surround the plurality of signal conductors.

17. The semiconductor package device according to claim 11, wherein The number of the multiple circuit layers is an even number, and in the vertical direction, the signal transmission direction of the topmost of the multiple circuit layers is opposite to that of its adjacent layers, and the signal transmission direction of the bottommost of the multiple circuit layers is opposite to that of its adjacent layers.

18. The semiconductor package device according to claim 11, wherein The number of the multiple circuit layers is an odd number. In the vertical direction, the signal transmission direction of the topmost circuit layer is opposite to that of its adjacent layers, and the signal transmission direction of the bottommost circuit layer is the same as that of its adjacent layers.

19. The semiconductor package device according to claim 11, wherein The number of the multiple circuit layers is an odd number. In the vertical direction, the signal transmission direction of the topmost circuit layer is the same as that of its adjacent layers, and the signal transmission direction of the bottommost circuit layer is opposite to that of its adjacent layers.

20. The semiconductor package device according to claim 11, wherein The intermediate layer device further includes a plurality of dielectric layers disposed between the plurality of circuit layers for shielding the plurality of circuit layers.

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