Phase delay test and compensation method of active power filter

Abstract

The invention provides a phase delay test and compensation method for an active power filter, and the method comprises the steps: generating a sine wave control signal with the frequency range of 1 kHz to 20 kHz through an FPGA, and driving a half-bridge inverter of the active power filter to output an analog signal; measuring delay time of three delay links in the active power filter by modules, wherein the delay time comprises delay 1 of an error detection link, delay 2 of an inversion link and delay 3 of a digital processing link; and taking the sum of the delay 1 of the error detection link, the delay 2 of the inversion link and the delay 3 of the digital processing link as the total delay of the system, introducing a phase compensation parameter in an LMS algorithm, and adjusting the phase of the offset current to enable the phase difference between the offset current and the harmonic current of the power grid to be 180 + / -5 degrees. According to the technical scheme, the delay parameter in the active power filter can be measured, phase alignment of the output signal of the active power filter and the harmonic current in the power grid is achieved in a compensation mode, and suppression of the harmonic current of the power grid is achieved.

Description

Technical Field

[0001] The invention belongs to the technical field of electromagnetic compatibility, and in particular relates to a phase delay test and compensation method for an active power filter. Background Art

[0002] When the active power filter based on the LMS algorithm is connected in parallel to the power grid, the interference frequency point is an isolated linear spectrum. Due to the internal delay of the active power filter itself, the phase difference between its actual output at some frequency points (frequency bands) and the grid harmonic current deviates by 180°, which seriously weakens the suppression effect of the active power filter. When the phase difference increases to a certain extent, it even enhances the harmonics and causes oscillation.

[0003] The traditional LMS algorithm is widely used in the acoustics field. To control the delay between the loudspeaker and the noise detection microphone in the secondary channel of the noise control system, white noise injection is used. However, when LMS is applied to active power filters, white noise injection can affect the stability of the power system. Furthermore, due to the presence of harmonic interference in the power grid, white noise injection is not applicable.

[0004] Therefore, how to propose a phase delay test and compensation method for active power filters that can test the internal delay parameters of active power filters, effectively avoid injecting white noise interference into the power grid, and achieve the suppression of power grid harmonic currents has become a technical problem that needs to be solved urgently. Summary of the Invention

[0005] In response to the problems existing in the prior art, the present invention provides a phase delay testing and compensation method for an active power filter, which can measure the delay parameters inside the active power filter and achieve phase alignment of the output signal of the active power filter with the harmonic current in the power grid through compensation, thereby suppressing the harmonic current of the power grid.

[0006] In an embodiment of the present invention, a method for testing and compensating phase delay of an active power filter is provided, comprising:

[0007] S101, generating a sinusoidal wave control signal with a frequency range of 1 kHz to 20 kHz through the FPGA to drive the half-bridge inverter of the active power filter to output an analog signal;

[0008] S102, measuring the delay time of three delay links inside the active power filter by modules, including:

[0009] Error detection delay 1: The delay from the Rogowski coil current detection to the differential voltage signal before ADC sampling, calculated by synchronously observing the time domain signals of the current caliper and voltage probe;

[0010] Inverter delay 2: The delay from the half-bridge midpoint voltage to the current signal after the capacitor is injected. This is calculated by synchronously observing the time domain signals of the voltage probe and current caliper.

[0011] Digital processing delay 3: The combined delay of ADC sampling, FPGA operation, and half-bridge conversion, calculated based on the ADC sampling clock frequency and the FPGA divided clock period;

[0012] S103. The sum of the delay 1 of the error detection link, the delay 2 of the inverter link, and the delay 3 of the digital processing link is taken as the total system delay. A phase compensation parameter is introduced into the LMS algorithm to adjust the phase of the offset current so that its phase difference with the grid harmonic current is 180°±5°.

[0013] Furthermore, the specific measurement of delay 1 in the error detection link includes:

[0014] Generate a sine wave control signal with a frequency of 5kHz, 10kHz or 15kHz through FPGA to drive the half-bridge inverter to generate an analog current signal;

[0015] Connect a high-precision current caliper to the error detection Rogowski coil, and connect a differential voltage probe in parallel to the differential signal end before AD sampling;

[0016] The signals of the current caliper and voltage probe are synchronously acquired using a dual-channel oscilloscope. The data are imported into Matlab for time domain alignment. The difference in the number of sampling points of the two signals, ΔN1, is calculated. The duration of Delay 1 is determined based on the oscilloscope sampling interval, Δt1: Delay 1 of the error detection link = ΔN1 × Δt1.

[0017] Furthermore, the specific measurement of delay 2 of the inverter link includes:

[0018] Connect a high-voltage differential probe to the midpoint voltage of the half-bridge, and connect a high-bandwidth current clamp in series to the current signal end after the injection capacitor;

[0019] The voltage and current signals are collected synchronously by an oscilloscope. After digital filtering of the two signals using Matlab, the difference in the number of time domain sampling points ΔN2 is calculated, and the duration of Delay 2 is determined based on the sampling interval Δt2: Delay 2 of the inverter link = ΔN2 × Δt2.

[0020] Furthermore, the specific measurement of the delay 3 of the digital processing link includes:

[0021] Calculate AD conversion delay based on ADC sampling clock frequency;

[0022] Calculate FPGA operation delay based on the operation cycle of the FPGA program and the divided clock frequency;

[0023] The total duration of Delay 3 of the digital processing link is determined by combining the AD conversion delay and the FPGA operation delay.

[0024] Furthermore, the phase compensation parameter is introduced as follows:

[0025] Insert a time-shift module corresponding to the total delay time T_total into the reference signal path of the LMS algorithm. The time shift amount is: ΔT = T_total = delay 1 + delay 2 + delay 3;

[0026] By adjusting the phase offset of the time shift module The phase of the offset current satisfies: Where f is the harmonic frequency.

[0027] Furthermore, in the grid harmonic suppression, the total harmonic distortion (THD) of the active power filter after phase compensation is reduced to below 3%, and the system stability margin is ≥10dB.

[0028] Furthermore, the injection of white noise into the power grid is avoided during the submodule test, and the signal-to-noise ratio (SNR) of all measurement signals is ≥60dB.

[0029] Furthermore, a sine wave control signal with a frequency range of 1kHz to 20kHz is generated by the FPGA, including:

[0030] A control signal with a frequency of 5 kHz, 10 kHz or 15 kHz is generated, and the generation of the control signal is achieved through FPGA programming.

[0031] The beneficial effects brought about by the present invention are as follows:

[0032] As can be seen from the above scheme, an embodiment of the present invention provides a phase delay testing and compensation method for an active power filter. An FPGA generates a sinusoidal control signal with a frequency range of 1kHz to 20kHz, driving the half-bridge inverter of the active power filter to output an analog signal. The delay time of the three delay links within the active power filter is measured in modules, including: delay 1 of the error detection link, delay 2 of the inverter link, and delay 3 of the digital processing link. The sum of delay 1 of the error detection link, delay 2 of the inverter link, and delay 3 of the digital processing link is used as the total system delay. A phase compensation parameter is introduced into the LMS algorithm to adjust the phase of the offset current so that its phase difference with the grid harmonic current is 180°±5°. The technical solution of the present invention can measure the delay parameters within the active power filter and achieve phase alignment of the output signal of the active power filter with the harmonic current in the grid through compensation, thereby suppressing the grid harmonic current. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A flow chart of a phase delay test and compensation method for an active power filter according to an embodiment of the present invention;

[0034] Figure 2 A schematic diagram of current vector superposition of a phase delay test and compensation method for an active power filter according to an embodiment of the present invention;

[0035] Figure 3 A schematic diagram of a phase shift generating link in an active power filter of a phase delay testing and compensation method for an active power filter according to an embodiment of the present invention;

[0036] Figure 4 A schematic diagram showing three steps of generating delay in a method for phase delay testing and compensation of an active power filter according to an embodiment of the present invention. DETAILED DESCRIPTION

[0037] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0038] like Figures 1 to 4 As shown, Figure 1 This is a flow chart of a phase delay test and compensation method for an active power filter according to an embodiment of the present invention. Figure 2 Schematic diagram of current vector superposition of a phase delay test and compensation method for an active power filter according to an embodiment of the present invention. Figure 3 Schematic diagram of a phase shift generating link in an active power filter of a phase delay testing and compensation method of an active power filter according to an embodiment of the present invention. Figure 4 A schematic diagram showing three steps of generating delay in a method for phase delay testing and compensation of an active power filter according to an embodiment of the present invention.

[0039] Figure 1 A method for testing and compensating phase delay of an active power filter includes:

[0040] S101, generating a sinusoidal wave control signal with a frequency range of 1 kHz to 20 kHz through the FPGA to drive the half-bridge inverter of the active power filter to output an analog signal;

[0041] S102, measuring the delay time of three delay links inside the active power filter by modules, including:

[0042] Error detection delay 1: The delay from the Rogowski coil current detection to the differential voltage signal before ADC sampling, calculated by synchronously observing the time domain signals of the current caliper and voltage probe;

[0043] Inverter delay 2: The delay from the half-bridge midpoint voltage to the current signal after the capacitor is injected. This is calculated by synchronously observing the time domain signals of the voltage probe and current caliper.

[0044] Digital processing delay 3: The combined delay of ADC sampling, FPGA operation, and half-bridge conversion, calculated based on the ADC sampling clock frequency and the FPGA divided clock period;

[0045] S103. The sum of the delay 1 of the error detection link, the delay 2 of the inverter link, and the delay 3 of the digital processing link is taken as the total system delay. A phase compensation parameter is introduced into the LMS algorithm to adjust the phase of the offset current so that its phase difference with the grid harmonic current is 180°±5°.

[0046] In this embodiment of the present invention, the delay of each link is directly obtained through modular testing, without the need to inject white noise, and interference-free measurement can avoid the risk of power grid stability. Combining hardware measurement (delay 1, delay 2) with software calculation (delay 3) can achieve high-precision compensation, with a total delay error of ≤5% and a phase difference of ±5° after compensation. The time shift module in the LMS algorithm can be dynamically adjusted according to the harmonic frequency, which is suitable for wide-band (1kHz-20kHz) harmonic suppression.

[0047] In another embodiment of the present invention, the specific measurement of delay 1 of the error detection link includes:

[0048] Generate a sine wave control signal with a frequency of 5kHz, 10kHz or 15kHz through FPGA to drive the half-bridge inverter to generate an analog current signal;

[0049] Connect a high-precision current caliper to the error detection Rogowski coil, and connect a differential voltage probe in parallel to the differential signal end before AD sampling;

[0050] The signals of the current caliper and voltage probe are synchronously acquired using a dual-channel oscilloscope. The data are imported into Matlab for time domain alignment. The difference in the number of sampling points of the two signals, ΔN1, is calculated. The duration of Delay 1 is determined based on the oscilloscope sampling interval, Δt1: Delay 1 of the error detection link = ΔN1 × Δt1.

[0051] In another embodiment of the present invention, the specific measurement of the delay 2 of the variable link includes:

[0052] Connect a high-voltage differential probe to the midpoint voltage of the half-bridge, and connect a high-bandwidth current clamp in series to the current signal end after the injection capacitor;

[0053] The voltage and current signals are collected synchronously by an oscilloscope. After digital filtering of the two signals using Matlab, the difference in the number of time domain sampling points ΔN2 is calculated, and the duration of Delay 2 is determined based on the sampling interval Δt2: Delay 2 of the inverter link = ΔN2 × Δt2.

[0054] In yet another embodiment of the present invention, the specific measurement of the delay 3 of the digital processing link includes:

[0055] Calculate AD conversion delay based on ADC sampling clock frequency;

[0056] Calculate FPGA operation delay based on the operation cycle of the FPGA program and the divided clock frequency;

[0057] The total duration of Delay 3 of the digital processing link is determined by combining the AD conversion delay and the FPGA operation delay.

[0058] In another embodiment of the present invention, the phase compensation parameter is introduced as follows:

[0059] Insert a time-shift module corresponding to the total delay time T_total into the reference signal path of the LMS algorithm. The time shift amount is: ΔT = T_total = delay 1 + delay 2 + delay 3;

[0060] By adjusting the phase offset of the time shift module The phase of the offset current satisfies: Where f is the harmonic frequency.

[0061] In another embodiment of the present invention, the active power filter after phase compensation reduces the total harmonic distortion (THD) to below 3% in grid harmonic suppression, and the system stability margin is ≥10dB.

[0062] In yet another embodiment of the present invention, white noise is avoided from being injected into the power grid during the sub-module test, and the signal-to-noise ratio (SNR) of all measurement signals is ≥60 dB.

[0063] In yet another embodiment of the present invention, a control signal with a frequency of 5 kHz, 10 kHz or 15 kHz is generated, and the generation of the control signal is achieved through FPGA programming.

[0064] Figure 2 In the active power filter, the noise current I DM With the offset current I cancel After vector synthesis, the offset current I q At this time, I q The phase of I DM , I cancel The amplitude and phase of . Ideally, IDM with I cancel The amplitudes are equal and the phases are 180° apart, e.g. Figure 2 (a), the interference signal can be suppressed. But in fact, the system is in Figure 2 (b) The vector superposition state, at this time due to the internal effect of the filter, the phase changes, I q with I cancel The phase difference also changes with frequency.

[0065] Figure 3 The factors that cause phase shift inside the active power filter show the characteristics of delay in time. There are three main parts that cause delay. Combined with the specific circuit analysis, the specific delay is as follows: Figure 4 shown.

[0066] Delay 1: The delay caused by the differential voltage signal before the error current passes through the Rogowski coil and bandpass filter to the AD chip;

[0067] Delay 2: The delay caused by the current signal after the midpoint voltage of the inverter half-bridge passes through the transformer and reaches the injection capacitor;

[0068] Delay 3: Delay caused by ADC chip and FPGA program.

[0069] Delay 1 is the delay between the current signal at the error detection Rogowski coil and the differential voltage signal before ADC sampling. An FPGA program is written to generate a sinusoidal control signal of a specified frequency, and a corresponding analog signal is generated through a half-bridge inverter. After passing through the load, the current is detected by the Rogowski coil and converted into a differential voltage signal. After ADC conversion, it is input to the FPGA and observed via an oscilloscope using a current caliper and a voltage probe.

[0070] Taking the measurement of 5kHz delay as an example, the steps are as follows:

[0071] 1) Use FPGA to generate 5Khz control signal;

[0072] 2) Clamp the current clamp on the error detection Rogowski coil, connect the current clamp to the differential signal before AD detection and observe it with an oscilloscope;

[0073] 3) Save the oscilloscope signal and import it into Matlab for observation;

[0074] 4) Calculate the point difference between the two signals using the obtained signal, and calculate the delay time between the two based on the oscilloscope sampling time.

[0075] Delay 2 is the delay from the voltage signal at the midpoint of the half-bridge to the current signal injected into the injection capacitor. This is observed by connecting an oscilloscope to a voltage probe and a current clamp. Taking the 5kHz delay measurement as an example, the steps are as follows:

[0076] 1) Use FPGA to generate 5Khz control signal;

[0077] 2) Connect a voltage probe to the half-bridge and set the digital filter to 50kHz. Connect a current clamp after the injection capacitor and observe the two signals with an oscilloscope.

[0078] 3) Save the oscilloscope signal and import it into Matlab for observation;

[0079] 4) Calculate the point difference between the two signals using the obtained signal, and calculate the delay time between the two based on the oscilloscope sampling time.

[0080] Delay 3 is caused by AD sampling, FPGA operation, specifically the ADC sample-convert-hold time, FPGA program timing, and half-bridge conversion.

[0081] The AD sampling clock is divided by the FPGA and is 400kHz, so the AD delay is roughly calculated as:

[0082]

[0083] The input clock of the FPGA program is 400k, that is, the delay caused by running a floating-point operation is:

[0084]

[0085] The FPGA program is divided into a main program and an LMS subroutine. The main program uses a 200MHz clock, which causes negligible delays. The LMS algorithm, on the other hand, uses a 400kHz clock divided by 200MHz, which causes significant delays.

[0086] 2.5us*10=25us

[0087] Since then, all three delays of the active power filter device have been measured, as shown in Table 1:

[0088] Table 1 Test results

[0089] Frequency / hz. Cycle / us Delay 1 / us Delay 2 / us Delay 3 / us Delay 1+2 / us 1000 1000 179 835 25 39 5000 200 95 38 25 158 10000 100 60 21 25 106 15000 67 46 15 25 86 20000 50 40 11 25 76

[0090] The phase delay is compensated by the delay parameters obtained through the test, and the active power filter can effectively suppress the interference.

[0091] An embodiment of the present invention provides a phase delay testing and compensation method for an active power filter. An FPGA generates a sinusoidal control signal with a frequency range of 1kHz to 20kHz, driving the active power filter's half-bridge inverter to output an analog signal. The delay times of three delay links within the active power filter are measured in modules: error detection link delay 1, inverter link delay 2, and digital processing link delay 3. The sum of error detection link delay 1, inverter link delay 2, and digital processing link delay 3 is used as the total system delay. A phase compensation parameter is introduced into the LMS algorithm to adjust the phase of the offset current so that its phase difference with the grid harmonic current is 180°±5°. The technical solution of the present invention can measure the delay parameters within the active power filter and, through compensation, align the phase of the active power filter's output signal with the grid harmonic current, thereby suppressing the grid harmonic current.

[0092] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A phase delay test and compensation method for an active power filter, characterized in that: The method comprises: S101, generating a sinusoidal wave control signal with a frequency range of 1 kHz to 20 kHz through the FPGA to drive the half-bridge inverter of the active power filter to output an analog signal; S102, measuring the delay time of three delay links inside the active power filter by modules, including: Error detection delay 1: The delay from the Rogowski coil current detection to the differential voltage signal before ADC sampling, calculated by synchronously observing the time domain signals of the current caliper and voltage probe; Inverter delay 2: The delay from the half-bridge midpoint voltage to the current signal after the capacitor is injected. This is calculated by synchronously observing the time domain signals of the voltage probe and current caliper. Digital processing delay 3: The combined delay of ADC sampling, FPGA operation, and half-bridge conversion, calculated based on the ADC sampling clock frequency and the FPGA divided clock period; S103. The sum of the delay 1 of the error detection link, the delay 2 of the inverter link, and the delay 3 of the digital processing link is taken as the total system delay. A phase compensation parameter is introduced into the LMS algorithm to adjust the phase of the offset current so that its phase difference with the grid harmonic current is 180°±5°.

2. The phase delay test and compensation method of an active power filter according to claim 1, characterized in that: The specific measurement of delay 1 in the error detection link includes: Generate a sine wave control signal with a frequency of 5kHz, 10kHz or 15kHz through FPGA to drive the half-bridge inverter to generate an analog current signal; Connect a high-precision current caliper to the error detection Rogowski coil, and connect a differential voltage probe in parallel to the differential signal end before AD sampling; The signals of the current caliper and voltage probe are synchronously acquired using a dual-channel oscilloscope. The data are imported into Matlab for time domain alignment. The difference in the number of sampling points of the two signals, ΔN1, is calculated. The duration of Delay 1 is determined based on the oscilloscope sampling interval, Δt1: Delay 1 of the error detection link = ΔN1 × Δt1.

3. The phase delay testing and compensation method of an active power filter according to claim 1, characterized in that: The specific measurement of delay 2 of the inverter link includes: Connect a high-voltage differential probe to the midpoint voltage of the half-bridge, and connect a high-bandwidth current clamp in series to the current signal end after the injection capacitor; The voltage and current signals are collected synchronously by an oscilloscope. After digital filtering of the two signals using Matlab, the difference in the number of time domain sampling points ΔN2 is calculated, and the duration of Delay 2 is determined based on the sampling interval Δt2: Delay 2 of the inverter link = ΔN2 × Δt2.

4. The phase delay testing and compensation method of an active power filter according to claim 1, characterized in that: Specific measurements of the delay 3 of the digital processing link include: Calculate AD conversion delay based on ADC sampling clock frequency; Calculate FPGA operation delay based on the operation cycle of the FPGA program and the divided clock frequency; The total duration of Delay 3 of the digital processing link is determined by combining the AD conversion delay and the FPGA operation delay.

5. The phase delay testing and compensation method of an active power filter according to claim 1, characterized in that: The phase compensation parameters are introduced as follows: Insert a time-shift module corresponding to the total delay time T_total into the reference signal path of the LMS algorithm. The time shift amount is: ΔT = T_total = delay 1 + delay 2 + delay 3; By adjusting the phase offset φ of the time shift module, the phase of the offset current satisfies: φ=2π×f×ΔT, where f is the harmonic frequency.

6. The phase delay testing and compensation method of an active power filter according to claim 1, characterized in that: The active power filter after phase compensation reduces the total harmonic distortion (THD) to below 3% in power grid harmonic suppression, and the system stability margin is ≥10dB.

7. The phase delay testing and compensation method of an active power filter according to claim 1, characterized in that: In the submodule test, white noise is avoided from being injected into the power grid, and the signal-to-noise ratio (SNR) of all measurement signals is ≥60dB.

8. A phase delay testing and compensation method for an active power filter according to any one of claims 1 to 7, characterized in that: Generates a sine wave control signal with a frequency range of 1kHz to 20kHz through the FPGA, including: A control signal with a frequency of 5 kHz, 10 kHz or 15 kHz is generated, and the generation of the control signal is achieved through FPGA programming.

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