Switching tube driving anti-straight-through interlocking protection circuit

Abstract

The invention discloses a switch tube driving anti-straight-through interlocking protection circuit, which comprises four input ends, the four input ends are respectively used for being connected with a micro control unit (MCU), the MCU inputs a driving signal of a switch tube on a first bridge arm of a single-phase full-bridge inverter from the first input end, and the MCU outputs a driving signal of the switch tube on a second bridge arm of the single-phase full-bridge inverter from the second input end. A driving signal of the MCU to a lower switching tube of a first bridge arm of the single-phase full-bridge inverter is input from the second input end, a driving signal of the MCU to an upper switching tube of a second bridge arm of the single-phase full-bridge inverter is input from the third input end, and a driving signal of the MCU to a lower switching tube of the second bridge arm of the single-phase full-bridge inverter is input from the fourth input end. According to the invention, the driving signal of the switching tube is processed, the abnormal signal possibly causing direct connection damage of the switching tube is filtered out, the fault rate of the inverter is reduced, and the reliability of the system is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of electrical engineering, and in particular to a switch tube driven anti-shoot-through interlock protection circuit. Background Art

[0002] With the rapid development of power electronics technology, research on the application of switching devices has become a hot topic. Currently, short-circuit overcurrent faults are one of the main causes of failure of devices such as SiC MOSFETs and IGBTs.

[0003] This is especially true for high-power inverter systems, which feature high power, high output current, and complex electromagnetic environments. The drive signals for the switches in the inverter's main circuit are generated by a control circuit and discharged by an amplifier circuit. These signals are small compared to the main circuit and are susceptible to interference from surrounding signals, leading to timing disruptions. High-power, high-voltage inverters, with output voltages reaching tens of kV, pose even more severe interference challenges. In systems where a single control unit provides switch drive signals to multiple inverters simultaneously, interference can affect all inverters. In severe cases, this interference can cause a direct current to the upper and lower switches in the same arm, leading to damage. Summary of the Invention

[0004] In response to the problems existing in the prior art, the present invention provides a switch tube drive anti-straight-through interlock protection circuit, which processes the switch tube drive signal and filters out abnormal signals that may cause straight-through damage to the switch tube, thereby reducing the inverter failure rate and improving system reliability.

[0005] The purpose of the present invention is achieved through the following technical solutions.

[0006] A switch tube drive anti-shoot-through interlock protection circuit includes four input terminals, each of which is used to connect to a microcontroller unit (MCU). The MCU receives a drive signal for the switch tube on the first bridge arm of a single-phase full-bridge inverter from the first input terminal, receives a drive signal for the switch tube on the lower bridge arm of the first bridge arm of the single-phase full-bridge inverter from the second input terminal, receives a drive signal for the switch tube on the upper bridge arm of the second bridge arm of the single-phase full-bridge inverter from the third input terminal, and receives a drive signal for the switch tube on the lower bridge arm of the second bridge arm of the single-phase full-bridge inverter from the fourth input terminal.

[0007] The first input end is respectively connected to the sixth pin of the non-Schmitt trigger and the thirteenth pin of the AND gate, the second input end is respectively connected to the fifth pin of the non-Schmitt trigger and the first pin of the AND gate, the third input end is respectively connected to the second pin of the non-Schmitt trigger and the sixth pin of the AND gate, and the fourth input end is respectively connected to the first pin of the non-Schmitt trigger and the eighth pin of the AND gate; the fourth pin of the output end of the non-Schmitt trigger is respectively connected to the second pin and the twelfth pin of the AND gate; the third pin of the output end of the non-Schmitt trigger is respectively connected to the fifth pin and the ninth pin of the AND gate; the eleventh pin of the AND gate is connected to the first output end of the protection circuit through a filter resistor; the third pin of the AND gate is connected to the second output end of the protection circuit through a filter resistor; the fourth pin of the AND gate is connected to the third output end of the protection circuit through a filter resistor; and the tenth pin of the AND gate is connected to the fourth output end of the protection circuit through a filter resistor.

[0008] The driving signals of the upper and lower switching tubes of the same bridge arm are first processed by a non-AND Schmitt trigger to filter out the driving waveform that may cause the bridge arm to be directly turned on during the entire switching cycle.

[0009] The waveform processed by the non-Schmitt trigger and the PWM signal output by the MCU are processed through the AND gate, so that the driving waveform that may cause the bridge arm to pass through is filtered out in each driving signal.

[0010] Compared with the prior art, the advantages of the present invention are:

[0011] 1. The present invention uses a logic circuit to process the disturbed driving waveform and filter out the driving waveform that may cause the upper and lower switches of the same bridge arm of the inverter to be directly turned on;

[0012] 2. The normal driving waveform can pass through the anti-shoot-through circuit intact and will not be affected;

[0013] 3. Simple circuit design, easy and quick to embed into existing high-power inverter power supply system. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is a schematic diagram of the anti-shoot-through interlock protection circuit for the switch tube drive of the present invention.

[0015] Figure 2 This is a switch tube driven anti-straight-through interlock protection circuit board of the present invention. DETAILED DESCRIPTION

[0016] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0017] The present invention adopts a logic operation chip and components such as resistors and capacitors, mainly including a four-input NAND Schmitt trigger, a four-input AND gate, input resistors before the AND gate input pins, and a filter capacitor used for the VCC pin of the logic operation chip.

[0018] Refer to the accompanying drawings Figure 1 As shown, the NAND Schmitt trigger N1 in this application is implemented using a CD4093 chip. The fourteenth pin of the NAND Schmitt trigger N1 is connected to the +12V power supply, the seventh pin is connected to the GND pin, and the VCC pin is connected to filter capacitors C0 and C1. The AND gate N2 in this application is implemented using a CD4081 chip. The fourteenth pin of the NAND gate N2 is connected to the +12V power supply, the seventh pin is connected to the GND pin, and the VCC pin is connected to filter capacitors C2 and C3.

[0019] The first input terminal A of the protection circuit is respectively connected to the sixth pin of the NAND Schmitt trigger N1 and the thirteenth pin of the AND gate N2, the second input terminal B is respectively connected to the fifth pin of the NAND Schmitt trigger N1 and the first pin of the AND gate N2, the third input terminal C is respectively connected to the second pin of the NAND Schmitt trigger N1 and the fifth pin of the AND gate N2, and the fourth input terminal D is respectively connected to the first pin of the NAND Schmitt trigger N1 and the eighth pin of the AND gate N2.

[0020] The fourth pin of the output terminal of the NAND Schmitt trigger N1 is connected to the second pin and the twelfth pin of the AND gate N2 respectively. The third pin of the output terminal of the NAND Schmitt trigger N1 is connected to the sixth pin and the ninth pin of the AND gate N2 respectively.

[0021] The 11th pin of AND gate N2 is connected to one end of filter resistor R1, the other end of which is connected to the first output terminal OUTA of the entire protection circuit. The 3rd pin of AND gate N2 is connected to one end of filter resistor R2, the other end of which is connected to the second output terminal OUTB of the entire protection circuit. The 4th pin of AND gate N2 is connected to one end of filter resistor R3, the other end of which is connected to the third output terminal OUTC of the entire protection circuit. The 10th pin of AND gate N2 is connected to one end of filter resistor R4, the other end of which is connected to the fourth output terminal OUTD of the entire protection circuit.

[0022] The working principle of the anti-shoot-through interlock protection circuit of a switch tube drive disclosed in this application is as follows:

[0023] In actual use, the MCU (Microcontroller) inputs the driving signal of the switch tube on the first bridge arm of the single-phase full-bridge inverter from the first input terminal A, the MCU inputs the driving signal of the switch tube on the lower bridge arm of the first bridge arm of the single-phase full-bridge inverter from the second input terminal B, the MCU inputs the driving signal of the switch tube on the second bridge arm of the single-phase full-bridge inverter from the third input terminal C, and the MCU inputs the driving signal of the switch tube on the lower bridge arm of the second bridge arm of the single-phase full-bridge inverter from the fourth input terminal D.

[0024] Taking the first leg of a single-phase full-bridge inverter as an example, if the drive waveforms of A and B overlap, this can cause the upper and lower switches in the first leg to conduct simultaneously. This application discloses a switch drive shoot-through prevention interlock protection circuit that first processes the drive signals of A and B using a NAND Schmitt trigger, effectively filtering out the overlapping portions of the drive waveforms. It then uses an AND gate circuit to obtain the processed drive signal.

[0025] This embodiment is based on a high-power high-voltage power supply system, and a switch tube drive anti-shoot-through interlock protection circuit disclosed in this application is added to the control module of the inverter. Figure 2 shown.

[0026] The indicators of the high-power high-voltage power supply system are as follows:

[0027] 1) Input voltage: three-phase 380V AC;

[0028] 2) Output voltage: -30~-40kV;

[0029] The high-voltage power supply prototype consists of three parts: a control section, an inverter circuit, and a high-voltage boost rectifier. The control section generates PWM control signals to control the high-power inverter in the inverter circuit. The switch tube drive anti-shoot-through interlock protection circuit disclosed in this application should be incorporated into the control section to protect the inverter drive signal.

[0030] When the drive waveforms of the upper and lower switches in the same inverter arm overlap, a NAND Schmitt trigger is first used to process the drive signal. This is equivalent to filtering out the overlapping waveforms of the upper and lower switches during the full switching cycle, and then processing them using an AND gate circuit to obtain an inverter drive waveform without the risk of shoot-through.

[0031] The present invention is applicable to scenarios such as high-power power supply systems where the electromagnetic environment is complex and the driving signal is susceptible to interference.

[0032] Based on the fundamental principles of logic circuits, this invention proposes a switch driver shoot-through prevention circuit. This circuit processes potential abnormal drive signals to ensure that the drive waveforms of the upper and lower switches in the same bridge arm do not reach valid trigger levels at the same timing, thus achieving hardware logic interlocking. This circuit has been proven in practical applications to effectively prevent shoot-through of the upper and lower switches in the same bridge arm of an inverter, ensuring long-term reliable operation of the power supply system.

Claims

1. A switch tube drive anti-shoot-through interlock protection circuit, characterized in that: The MCU comprises four input terminals, each of which is used to connect to a microcontroller unit MCU. The MCU receives a driving signal for the upper switch tube of the first bridge arm of the single-phase full-bridge inverter from the first input terminal, receives a driving signal for the lower switch tube of the first bridge arm of the single-phase full-bridge inverter from the second input terminal, receives a driving signal for the upper switch tube of the second bridge arm of the single-phase full-bridge inverter from the third input terminal, and receives a driving signal for the lower switch tube of the second bridge arm of the single-phase full-bridge inverter from the fourth input terminal.

2. A switch tube drive anti-shoot-through interlock protection circuit according to claim 1, characterized in that: The first input terminal is respectively connected to the sixth pin of the NAND Schmitt trigger and the thirteenth pin of the AND gate, the second input terminal is respectively connected to the fifth pin of the NAND Schmitt trigger and the first pin of the AND gate, the third input terminal is respectively connected to the second pin of the NAND Schmitt trigger and the sixth pin of the AND gate, and the fourth input terminal is respectively connected to the first pin of the NAND Schmitt trigger and the eighth pin of the AND gate; the fourth pin of the output terminal of the NAND Schmitt trigger is respectively connected to the second pin and the twelfth pin of the AND gate; the third pin of the output terminal of the NAND Schmitt trigger is respectively connected to the fifth pin and the ninth pin of the AND gate; the eleventh pin of the AND gate is connected to the first output terminal of the protection circuit through a filter resistor; The third pin of the AND gate is connected to the second output terminal of the protection circuit through a filter resistor; the fourth pin of the AND gate is connected to the third output terminal of the protection circuit through a filter resistor; and the tenth pin of the AND gate is connected to the fourth output terminal of the protection circuit through a filter resistor.

3. The switch tube drive anti-shoot-through interlock protection circuit according to claim 2, characterized in that: The driving signals of the upper and lower switching tubes of the same bridge arm are first processed by a non-AND Schmitt trigger to filter out the driving waveform that may cause the bridge arm to be directly turned on during the entire switching cycle.

4. A switch tube drive anti-shoot-through interlock protection circuit according to claim 3, characterized in that: The waveform processed by the non-Schmitt trigger and the PWM signal output by the MCU are processed through the AND gate, so as to filter out the driving waveform that may cause the bridge arm to pass through in each driving signal.

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