Programmable dead time control circuit
Through the programmable dead-time control circuit, the charging circuit current and external resistance are adjusted, the problem of additional loss of dead-time circuits is solved, the circuit efficiency is improved and layout design is simplified, and suitable for power management, portable equipment and communication equipment.
Patent Information
- Application Number
- CN202510488617.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-18
- Publication Date
- 2025-08-26
AI Technical Summary
The existing dead time circuits will increase the dead time regardless of whether the input signal has an on-time difference, resulting in additional losses or inefficiency. The dynamic dead time may superimpose the on-time difference of the input signal itself, further increasing the loss.
The programmable dead time control circuit is adopted to adjust the current magnitude and external resistance value in the charging circuit, programmable control of the dead time is achieved, ensuring that the dead time of the output signal is selected longer to avoid additional losses, and simplifying the circuit structure.
It realizes flexible setting of dead time according to circuit needs, improve circuit efficiency, simplify layout design, and is suitable for power management, portable equipment and communication equipment systems.
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Figure CN120546449A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of integrated circuits, and in particular to a dead time control circuit, and more specifically to a programmable dead time control circuit. Background Art
[0002] Dead-time drive circuits are a common module used in drive circuits. They generally refer to circuits with at least two drive signals, with a dead-time requirement between them. Drive circuits with dead-time not only prevent simultaneous conduction of power transistors but can also be used in some resonant circuits. Therefore, they have a wide range of applications, such as half-bridge and full-bridge circuits, externally excited synchronous rectifier circuits, and active clamp forward circuits. Setting the dead-time requires careful consideration: it should not be too short, causing cross-conduction of the power transistors, nor too long, resulting in low circuit efficiency. Depending on whether the dead-time is fixed, dead-time drive circuits can be divided into two categories: fixed dead-time drive circuits and dynamic dead-time drive circuits. Their different circuit characteristics make them suitable for different applications.
[0003] A dynamic dead-time driver circuit features a variable dead-time based on the circuit's operating conditions. This dynamic dead-time not only ensures that the switches are not simultaneously on but also minimizes the dead-time, thereby reducing power loss and improving circuit efficiency. For example, in synchronous rectification circuits, dynamic dead-time drivers are generally based on the principle that the switch must turn on when the voltage drops to zero and turn off when the current drops to zero. Specific circuit implementations require detection of both the voltage and current zero crossings.
[0004] Different from the two dead-time drive circuits mentioned above, there is also a programmable dead-time circuit that allows for manual adjustment of the dead-time according to different applications. This dead-time control is achieved through an external dead-time pin. Depending on how this pin is connected, the resulting dead-time varies.
[0005] The main problem with existing dead-time circuits is that, regardless of whether the two input signals have an on-time difference (also known as the input signal's dead time), a fixed dead time is added to the output signal. This means that regardless of whether the input signals have a dead time, the output signal will always have a dead time, which can lead to additional circuit losses. Another problem with existing dead-time circuits is that if the two input signals have an on-time difference, the dead time generated by the dead-time circuit may be added to the existing on-time difference between the two input signals, which can also cause additional losses or reduce efficiency. Summary of the Invention
[0006] The main object of the present application is to provide a programmable dead time control circuit, comprising an input module and a dead time module, wherein the dead time module comprises a first module and a second module, respectively generating a first output signal and a second output signal for outputting the dead time, wherein the first module and the second module respectively have a first input terminal and a second input terminal, and wherein the dead time and the input signals inputted at the first input terminal and the second input terminal have the following relationship:
[0007] If there is no time difference between the signals input from the first input terminal and the second input terminal, the dead time is the time set by the programmable dead time control circuit;
[0008] or
[0009] The input signals inputted from the first input terminal and the second input terminal have a time difference τ, and the dead time is set to δ. If τ>δ, the dead time is set to τ; if τ<δ, the dead time is δ.
[0010] In some embodiments, the first module and the second module have the same structure.
[0011] In some embodiments, the input module and the dead time module are integrated into one chip.
[0012] In some embodiments, the chip is a CMOS integrated circuit chip.
[0013] In some embodiments, the dead time module includes a pulse generating circuit, a latch, a comparator, and a ramp generating circuit.
[0014] According to the technical solution of the present application and the further improved technical solution in certain exemplary embodiments thereof, the present application has the following beneficial effects:
[0015] Programmable control of the dead time is achieved only by adjusting the current in the charging circuit. When the input signal has no on-time difference, the dead time can be easily set through the external terminal to meet the needs of different circuits. When the input signal has an on-time difference, the operation of the digital logic gate can make the dead time of the output signal always select the longer one of the dead time generated by the dead time module and the on-time difference of the input signal itself, which can not only ensure that the dead time meets the requirements, but also avoid generating additional losses. The technical solution of the present application also improves the symmetry of the circuit, simplifies the circuit structure, and saves the time of later layout drawing. And when the dead time is programmably controlled, the change of the dead time is linear. The technical solution of the present application has a wide range of applications and can be applied to power management, portable devices, sensors, communication equipment and other systems. The size of the dead time can be programmably adjusted according to actual usage.
[0016] The present application will be further described below in conjunction with the accompanying drawings and specific embodiments. Additional aspects and advantages of the present application will be partially given in the following description, partially become apparent from the following description, or be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] The drawings that constitute part of this application are used to provide a further understanding of this application. The specific implementation methods, illustrative examples, and their descriptions of this application are used to explain this application and do not constitute an improper limitation on this application. In the drawings:
[0018] Figure 1 Schematic diagram of the input module structure according to a specific embodiment of the present application;
[0019] Figure 2 Schematic diagram of the dead time module circuit structure according to a specific embodiment of the present application;
[0020] Figure 3 Schematic diagram of the corresponding relationship between the input signal waveform and the output signal waveform;
[0021] Figure 4 Schematic diagram showing the relationship between the dead time of the input signal and the dead time set by the programmable dead time control circuit. DETAILED DESCRIPTION
[0022] It should be noted that, in the absence of conflict, the specific implementations, exemplary embodiments, and features thereof in this application may be combined with each other. This application will now be described in detail with reference to the accompanying drawings and in conjunction with the following content.
[0023] In order to enable those skilled in the art to better understand the solution of this application, the following will be combined with the drawings in the specific implementation methods and exemplary embodiments of this application to clearly and completely describe the technical solutions in the specific implementation methods and exemplary embodiments of this application. Obviously, the exemplary embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the specific implementation methods and exemplary embodiments in this application, all other implementation methods and embodiments obtained by ordinary technicians in this field without making creative work should fall within the scope of protection of this application.
[0024] The technical solution of the present application is based on CMOS (complementary metal oxide semiconductor) process design, and realizes programmable control of the dead time circuit by changing the resistance value of the external resistor. Unlike the traditional dead time circuit adjusted by resistor, the circuit structure is simplified, and the programmable control of the dead time is achieved only by adjusting the current in the charging circuit, and a special discharge circuit is no longer required. Common dead time circuits have the problem of adding a dead time to the output signal regardless of whether the two input signals themselves have a conduction time difference, which will cause additional losses in the circuit. The present application solves this problem, and the dead time of the output signal will always be selected as the longer of the dead time generated by the dead time module and the conduction time difference of the input signal itself. The circuit module of the present application has strong symmetry, which is conducive to saving time for later layout drawing. The layout drawing personnel only need to draw one part, and the other part can be directly copied, which greatly saves layout design time.
[0025] Example
[0026] The programmable dead time control circuit of the present application is based on CMOS technology and integrates an input module and a dead time module in one chip. Figure 1 and Figure 2 As shown in FIG. The dead time module includes a first module and a second module with identical structures, each generating a first output signal OUTA and a second output signal OUTB, respectively. The time difference between the first output signal OUTA and the second output signal OUTB is the dead time δ output by the module. In this example, the first module and the second module have a first input terminal and a second input terminal, respectively, for connecting to the input signals INA and INB. Figure 2 In the example, although the first module and the second module have the same structure, the input signals connected to the two input terminals of the two modules are just swapped. That is, one input terminal of the NAND gate NAND1 of the first module is connected to the input signal INA, and one input terminal of the corresponding NAND gate of the second module is connected to the input signal INB; similarly, one input terminal of the NAND gate NAND3 of the first module is connected to the input signal INB, and one input terminal of the corresponding NAND gate of the second module is connected to the input signal INA. Figure 2 shown.
[0027] The input module structure of the programmable dead time control circuit in this example is very simple and does not require a special discharge circuit, such as Figure 1 As shown in the figure, the DeadTime pin (DT pin for short) is an external pin of the chip, and Vref is the reference voltage generated by the chip. There are three ways to connect the DT pin:
[0028] 1) Connect VDD (power supply voltage); at this time there is no dead time (less than 0.2ns), that is, δ = 0.
[0029] 2) Grounding through a resistor; at this time, the size of the dead time is related to the resistance value of the external resistor. By changing the resistance value of the external resistor, programmable control of the dead time can be achieved.
[0030] 3) Leave it unconnected; the dead time is less than 10ns.
[0031] The dead time module in this example consists of two identical modules, the first module and the second module. Figure 2 As shown. It mainly includes pulse generating circuit, latch, comparator, ramp generating circuit, etc.
[0032] The specific working principle of the programmable dead time control circuit in this example is described as follows:
[0033] Figure 2 In the chip, ENP is the enable terminal, which is connected to the enable signal given by the chip. It is high level during normal operation. When the chip detects an abnormality, the enable terminal becomes low level and the output is turned off.
[0034] When the DT pin is connected to VDD, VDD>Vref, that is, the negative end of the comparator COMP1 is greater than the positive end, COMP1 outputs a low level, at this time transistors M1, M2, and M3 are turned off, and transistors Q1, M6, and M7 are turned on. The current capacity of the M7 tube is designed to be greater than the current capacity of the M4 tube, so at this time VO3 outputs a low level and VO4 outputs a high level.
[0035] After a series of logic operations on VO3 and input signal INA, the output of NAND gate NAND2 is high level. After the input signals INB and ENP pass through NAND gate NAND3, they output a square wave with the opposite phase to INB. After the high level output of NAND gate NAND2 is operated by NOR gate NOR1, OUTB outputs a square wave exactly the same as INB. Figure 2 The circuit below is identical to the circuit above, differing only in the input signal. By analogy, OUTA outputs a square wave identical to INA. That is, when the DT pin is connected to VDD, there is no dead time between the two output signals.
[0036] When the DT pin is grounded through resistor R, in the input module, comparator COMP1 and transistor M1 form a negative feedback loop, which clamps the voltage of the DT pin to Vref. At this time, transistors M1, M2, and M3 are turned on, and Q1, M6, and M7 are turned off. The current capacity of the M3 transistor is designed to be greater than that of the M5 transistor. At this time, VO3 outputs a high level and VO4 outputs a low level. The current value I1 flowing through the circuit of VDD-M2-M1-external resistor R-GND is
[0037]
[0038] Among them, Vref is a reference voltage generated by the chip reference module, W2 and L2 are the width and length of transistor M2, u p is the mobility of hole carriers, C ox is the gate oxide capacitance per unit area of the MOS tube, V GS2 is the voltage difference between the gate and source of transistor M2, V th2 is the on-threshold of transistor M2.
[0039] In the first module, after the input signal INA passes through a NAND gate and an inverter, one branch directly enters the input end of the OR gate OR1, and the other branch passes through an inverter and then passes through an RC low-pass filter circuit before entering the other input end of the OR gate OR1. The RC low-pass filter circuit prolongs the rise time and fall time of the input signal INA. At this time, the two input ends of the OR gate OR1 are two square waves with opposite phases but different rise times and fall times. After the OR gate OR1 operation, a pulse signal will be output. This pulse signal is a narrow pulse that is usually high and suddenly changes to a low level. The narrow pulse appears at the end of one cycle of the input signal. The narrow pulse will subsequently be input into a latch, which is a NAND gate SR latch. Figure 2 It is marked as SR in the middle and is collectively referred to as SR latch below.
[0040] The output of point A of the SR latch is a waveform that is normally low and flips when a falling edge signal appears at the input terminal. The waveform acts on the gate of transistor M9 through the inverter. When the input terminal of transistor M9 is at a high level, transistor M9 is turned on, forming a current path of VDD-M8-M9-GND. Since the current capacity of transistor M9 is set to be stronger than that of transistor M8, the positive phase terminal of comparator COMP2 is at a low level at this time. When the input terminal of M9 flips to a low level, transistor M9 is turned off, but transistor M8 is still in the on state. The current charges capacitor C2 through transistor M8 and tends to pull the positive phase terminal of comparator COMP2 to a high level.
[0041] When the voltage at the non-inverting terminal of comparator COMP2 exceeds the voltage at its inverting terminal, the output will change from a low level to a high level, and then be sent to the input terminal of the SR latch after passing through the inverter. Because the output signal of the SR latch will flip when there is a falling edge at the input terminal, when the voltage at the non-inverting terminal of comparator COMP2 is higher than the voltage at the inverting terminal, not only the output level of comparator COMP2 will flip, but the gate voltage of transistor M9 will also flip. That is, when the voltage at the non-inverting terminal of COMP2 rises to exceed the voltage at its inverting terminal VO2, the gate voltage of transistor M9 will become a high level again, transistor M9 will be turned on, and the non-inverting terminal of comparator COMP2 will become a low level again. The final effect is that comparator COMP2 outputs a waveform that is usually low level but has a high level pulse.
[0042] At this point, we find that both inputs of the SR latch are always high, with a waveform of low-level pulses, but the time they generate the low-level pulses is different. According to the characteristics of the SR latch, we can know that its output is a signal with a narrow square wave. The width of the square wave is the time difference between the two inputs generating the low-level pulses. The width of the square wave is related to the capacitance of capacitor C2 and the resistance of external resistor R. The principle analysis is as follows:
[0043] From the circuit diagram and the above discussion, we can see that the inverting terminal voltage of comparator COMP2 is V02 = V DT = Vref. Because the V GS Both are VO1-VDD and are of the same type, so the current I2 through transistor M8 is proportional to the current I1 through transistor M2, that is:
[0044]
[0045] Wherein, W8 and L8 are the width and length of the transistor M8, and R is the resistance value of the external resistor.
[0046] It is known that the amount of charge Q that a capacitor can store is:
[0047] Q=CΔU=It(3)
[0048] Where C is the capacitance of the capacitor, ΔU is the voltage change on the positive plate of the capacitor, I is the charging current, and t is the charging time. In this circuit, we know that C is the capacitance of capacitor C2, ΔU=V02=V DT =Vref, I=I2, combining formula (1)(2)(3) we can calculate the time t as
[0049]
[0050] This time t is the narrow square wave width mentioned above, and is also the dead time δ we set. From formula (4), we can see that after we determine the width-to-length ratio of the M2 and M8 tubes inside the chip and the capacitance of the capacitor C2, the dead time can be changed by changing the resistance of the external resistor, and the dead time and the resistance of the external resistor are linearly related.
[0051] The inputs of NAND2 are one normally high, narrow square wave pulse, and the other a square wave with a phase opposite to INA. After these two signals pass through NAND2, the rising edge of the square wave flips after a delay of one dead time. The inputs of NOR1 are two square waves with the same phase but different falling edges. After the NOR operation, OUTB and INB are in phase, but the rising edge of OUTB is delayed by one dead time compared to the rising edge of INB.
[0052] Similarly, the output signals OUTA and INA of the second module have the same phase, but the rising edge time of OUTA is delayed by a dead time than the rising edge time of INA.
[0053] At this time, there is a dead time δ between the two output signals OUTB and OUTA, and they will not be turned on at the same time.
[0054] When the DT pin is floating, transistors M1, M2, M3, M6, and M7 are all turned off, and transistors M4 and M5 are turned on. Therefore, VO3 outputs a high level, and VO4 outputs a high level. In the first module, transistor M8 is turned off and transistor M10 is turned on. At this time, transistors M9, M10, and M11 can be regarded as an inverter. The working principle of the first module is similar to that when the DT pin is connected to an external resistor, except that the transistors that charge capacitor C2 are changed from M8 to M10 and M11, and the gate-source voltage V GS11 Much larger than the gate-source voltage V when M8 charges C2 GS8 Therefore, from formula (3), we can see that the dead time will be greatly reduced, approximately within 10ns.
[0055] Figure 2 In the figure, the output of NAND2 is a square wave with the same phase as INA with an added dead time. The output of NAND3 is a square wave with the opposite phase to the INB signal. The input of NOR1 is two square waves with the same phase but different falling edge times. Depending on the input signal, NOR1 has five different input conditions, and the output has five corresponding conditions, such as Figure 3 As shown, they are described below:
[0056] 1. The first input signal INA and the second input signal INB have the same pulse width and are exactly the same phase, that is, there is no conduction time difference between the first input signal and the second input signal (τ = 0). At this time, the output of NAND2 is a square wave with an added dead time δ and the same phase as INA. The output of the NAND gate NAND3 is a square wave with only the opposite phase to the INB signal. The input of the NOR gate NOR1 is two square waves with the same phase but different falling edge times. Therefore, after the NOR gate operation, OUTB is a square wave with the opposite phase to INA. The rising edge of INA and the falling edge of OUTB are at the same time. Compared with the falling edge of INA, the rising edge of OUTB is delayed by a dead time δ. The output of OUTA is analyzed in the same way, and the following can be obtained: Figure 3 In case (1) shown in the figure, the rising edges of INA and INB are both delayed by a dead time, which adds a dead time δ to the input signal. This dead time can be set as needed or can be 0.
[0057] 2. The pulse widths of INA and INB are different. The falling edge of INA and the rising edge of INB are at the same time. The rising edge of INA is delayed for a period of time compared to the falling edge of INB, and this time is greater than the dead time generated by the circuit. At this time, the output of NAND2 is a square wave with the same phase as INA, with a dead time added to the falling edge, but the rising edge remains unchanged. The output of NAND3 is a square wave with the same phase as the INB signal. The input of NOR1 is two square waves with the same phase, but different falling and rising edge times. Therefore, after the NOR gate operation, OUTB is a square wave with a phase opposite to INA. The rising edge of OUTB is delayed by a dead time compared to the falling edge of INB, and the falling edge of OUTB is at the same time as the rising edge of INB. The output of OUTA is analyzed in the same way, and the following can be obtained: Figure 3 In case (2) shown in the figure, the waveforms of OUTA and INA are exactly the same. The rising edge of OUTB has a dead time compared with the rising edge of INB, but the falling edge time remains unchanged.
[0058] 3. The pulse widths of INA and INB are different. The rising edge of INA is delayed for a period of time compared to the falling edge of INB, and the rising edge of INB is delayed for a period of time compared to the falling edge of INA. Both delay times are greater than the dead time generated by the circuit. At this time, the output of NAND2 is a square wave with the same phase as INA, with a dead time added to the falling edge, but the rising edge remains unchanged. The output of NAND3 is a square wave with the same phase as the INB signal. The input of NOR1 is two square waves with the same phase, but different falling and rising edge times. Therefore, after the NOR gate operation, OUTB is a signal that is completely identical to the INB waveform. The output of OUTA can be analyzed in the same way, and the following can be obtained: Figure 3As shown in case (3), the waveforms of OUTA and INA are completely consistent, and the waveforms of OUTB and INB are completely consistent.
[0059] 4. The pulse widths of INA and INB are the same. The rising edge of INB is delayed for a period of time compared to the falling edge of INA, and the rising edge of INA is delayed for a period of time compared to the falling edge of INB. The two delayed times are the same and are greater than the dead time generated by the circuit. At this time, the output of NAND2 is a square wave with the same phase as INA, with a dead time added to the falling edge, but the rising edge remains unchanged. The output of NAND3 is a square wave with the same phase as the INB signal. The input of NOR1 is two square waves with the same phase, but different falling and rising edge times. Therefore, after the NOR gate operation, the rising edge of OUTB is at the same time as the rising edge of INB, and the falling edge of OUTB is at the same time as the falling edge of INA. The output of OUTA is analyzed in the same way, and the following can be obtained: Figure 3 As shown in situation (4), we can find that the falling edge of OUTA is at the same time as the falling edge of INA, the rising edge of OUTA is the falling edge of INB delayed by a dead time, the rising edge of OUTB is at the same time as the rising edge of INB, and the falling edge of OUTB is at the same time as the falling edge of INA.
[0060] 5. The pulse widths of INA and INB are different. The falling edge of INB is delayed for a period of time compared to the rising edge of INA, and the falling edge of INA is delayed for a period of time compared to the rising edge of INB. Both of these delayed times are greater than the dead time generated by the circuit. At this time, the output of NAND2 is a square wave with the same phase as INA, with a dead time added to the falling edge, but the rising edge remains unchanged. The output of NAND3 is a square wave with only the opposite phase to the INB signal. The input of NOR1 is two square waves with the same phase, but different falling and rising edge times. Therefore, after the NOR gate operation, the falling edge of OUTB and the rising edge of INA are at the same time, and the rising edge of OUTB is delayed by a dead time compared to the falling edge of INA. The output of OUTA is analyzed in the same way, and the following can be obtained: Figure 3 As shown in case (5), the falling edge of OUTB and the rising edge of INA are at the same time, the rising edge of OUTB is delayed by a dead time than the falling edge of INA, the rising edge of OUTA is delayed by a dead time than the falling edge of INB, and the falling edge of OUTA and the rising edge of INB are at the same time.
[0061] In actual use, there are three situations for the size of the on-time difference τ between the input signals and the dead time δ set by the dead time module:
[0062] The first is that there is no dead time between input signals, that is, when τ = 0, the dead time between output signals is completely determined by the dead time set by the programmable dead time control circuit (related to the external resistor), which is δ;
[0063] The second is when the dead time τ of the input signal is greater than the dead time δ set by the programmable dead time control circuit, that is, when τ>δ, the dead time of the output signal is the dead time of the input signal itself, that is, the dead time is set to τ;
[0064] The third is when the dead time of the input signal is less than the dead time set by the programmable dead time control circuit, that is, when τ<δ, the dead time of the output signal is the dead time set by the programmable dead time control circuit (related to the external resistor), which is δ. Figure 4 shown.
Claims
1. A programmable dead time control circuit, comprising an input module and a dead time module, wherein the dead time module comprises a first module and a second module, each of which generates a first output signal and a second output signal, respectively, for outputting the dead time, wherein the first module and the second module respectively have a first input terminal and a second input terminal, and wherein: The dead time has the following relationship with the input signals inputted from the first input terminal and the second input terminal: If there is no time difference between the signals input from the first input terminal and the second input terminal, the dead time is the time set by the programmable dead time control circuit; or The input signals inputted from the first input terminal and the second input terminal have a time difference τ, and the dead time is set to δ. If τ>δ, the dead time is set to τ; if τ<δ, the dead time is δ.
2. The programmable dead time control circuit according to claim 1, wherein: The first module and the second module have the same structure.
3. A programmable dead time control circuit according to claim 1 or 2, characterized in that: The input module and dead time module are integrated into one chip.
4. The programmable dead time control circuit according to claim 3, wherein: The chip is a CMOS integrated circuit chip.
5. The programmable dead time control circuit according to claim 3, wherein: The dead time module includes a pulse generating circuit, a latch, a comparator, and a ramp generating circuit.