Semiconductor memory device and manufacturing method thereof

Abstract

A method of manufacturing a semiconductor memory device includes the following steps. A bit line structure is formed on a substrate, wherein the bit line structure includes a bit line conductive portion and a bit line dielectric portion. And forming a silicon carbon oxide (SiCO) layer on the bit line structure. And performing a hydrogen plasma process on the SiCO layer. And performing a hydrofluoric acid etching process on the SiCO layer. A silicon nitride layer is formed over the bit line structure and the remaining SiCO layer that is not etched by the hydrofluoric acid etching process. Therefore, the remaining SiCO layer is completely covered by the silicon nitride layer, and there is no damaged path of the remaining SiCO layer.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor memory device and a method for manufacturing the same. Background Art

[0002] Integrated circuit (IC) devices (also known as semiconductor chips) can contain millions of transistors and other circuit elements fabricated on a single silicon crystal substrate (wafer). In semiconductor memory devices, the bit line is a key component responsible for carrying data during read and write operations. It connects to the memory cells within the array and allows the transfer of binary information. During a read operation, the bit line senses the state of the memory cell, while during a write operation, it facilitates the updating of the data within the cell. The bit line structure typically involves metal lines, transistors, and other components to ensure efficient data transmission and storage in the memory device. Summary of the Invention

[0003] The present disclosure provides an innovative semiconductor memory device and a manufacturing method thereof to solve the problems of the prior art.

[0004] In some embodiments disclosed herein, a method for fabricating a semiconductor memory device includes: forming a bit line structure on a substrate, wherein the bit line structure includes a bit line conductive portion and a bit line dielectric portion; forming a silicon oxycarbide (SiCO) layer on the bit line structure; performing a hydrogen plasma process on the SiCO layer; performing a hydrofluoric acid etching process on the SiCO layer; and forming a silicon nitride layer over the bit line structure and a portion of the SiCO layer remaining unetched by the hydrofluoric acid etching process.

[0005] In some embodiments of the present disclosure, the method further includes performing a nitride etching process on the silicon nitride layer until the bit line dielectric portion is exposed.

[0006] In some embodiments of the present disclosure, the hydrogen plasma process is performed by applying a bias voltage of 100V to 400V.

[0007] In some embodiments of the present disclosure, the SiCO layer is composed of 37% silicon, 48% oxygen, and 15% carbon.

[0008] In some embodiments of the present disclosure, the bit line dielectric portion is located on top of the bit line conductive portion.

[0009] In some embodiments of the present disclosure, the bit line conductive portion includes a tungsten portion, a polysilicon portion, and a diffusion barrier layer located between the tungsten portion and the polysilicon portion.

[0010] In some embodiments of the present disclosure, a top portion of the remaining SiCO layer is completely surrounded by the bit line dielectric and the remaining silicon nitride layer that is not etched by the nitride etching process.

[0011] In some embodiments disclosed herein, a method for fabricating a semiconductor memory device includes: forming a bit line structure on a substrate, wherein the bit line structure includes a bit line conductive portion and a bit line dielectric portion; forming a silicon oxycarbide (SiCO) layer on the bit line structure; performing a hydrogen plasma process to oxidize a portion of the SiCO layer; performing a hydrofluoric acid etching process to remove the oxidized portion of the SiCO layer; and forming a silicon nitride layer over the bit line structure and the remaining portion of the SiCO layer not etched by the hydrofluoric acid etching process.

[0012] In some embodiments of the present disclosure, the SiCO layer is composed of 37% silicon, 48% oxygen, and 15% carbon.

[0013] In some embodiments of the present disclosure, the oxidized portion of the SiCO layer is composed of 60% oxygen and 40% silicon.

[0014] In some embodiments of the present disclosure, the hydrogen plasma process is performed by applying a bias voltage of 100V to 400V.

[0015] In some embodiments of the present disclosure, the method further includes performing a nitride etching process on the silicon nitride layer until the bit line dielectric portion is exposed.

[0016] In some embodiments of the present disclosure, a top portion of the remaining SiCO layer is completely surrounded by the bit line dielectric and the remaining silicon nitride layer that is not etched by the nitride etching process.

[0017] In some embodiments of the present disclosure, the bit line dielectric portion is located on top of the bit line conductive portion.

[0018] In some embodiments of the present disclosure, the bit line conductive portion includes a tungsten portion, a polysilicon portion, and a diffusion barrier layer located between the tungsten portion and the polysilicon portion.

[0019] In some embodiments disclosed herein, a semiconductor memory device includes: a bit line structure disposed on a substrate, wherein the bit line structure includes a bit line conductive portion and a bit line dielectric portion; a silicon oxycarbide (SiCO) layer disposed on sidewalls of the bit line structure; and a silicon nitride layer disposed on the sidewalls of the bit line structure, wherein a top portion of the SiCO layer is completely surrounded by the bit line dielectric portion and the silicon nitride layer.

[0020] In some embodiments of the present disclosure, a top portion of the bit line dielectric is not covered by the SiCO layer.

[0021] In some embodiments of the present disclosure, the SiCO layer is composed of 37% silicon, 48% oxygen, and 15% carbon.

[0022] In some embodiments of the present disclosure, the bit line dielectric portion is located on top of the bit line conductive portion.

[0023] In some embodiments of the present disclosure, the bit line conductive portion includes a tungsten portion, a polysilicon portion, and a diffusion barrier layer located between the tungsten portion and the polysilicon portion.

[0024] In summary, the semiconductor memory device manufacturing method disclosed herein utilizes a hydrogen plasma process to oxidize unwanted portions of the SiCO layer, and then performs a hydrofluoric acid etching process to remove the oxidized portions of the SiCO layer. Consequently, the remaining SiCO layer is completely covered by the silicon nitride layer, eliminating any path for damage to the remaining SiCO layer.

[0025] The following will describe the above description in detail with reference to implementation examples, and provide further explanation of the technical solutions disclosed herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] To make the above and other objects, features, advantages and embodiments of the present disclosure more apparent and understandable, the accompanying drawings are described as follows:

[0027] Figure 1-Figure 5 A partial cross-sectional view illustrating some manufacturing steps of a semiconductor memory device according to some embodiments of the present disclosure; and

[0028] Figure 6 The figure illustrates the process steps of a semiconductor memory manufacturing process according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0029] To make the description of this disclosure more detailed and complete, reference is made to the accompanying drawings and various embodiments described below, in which the same numbers represent the same or similar elements. On the other hand, well-known elements and steps are not described in the embodiments to avoid unnecessary limitations on this disclosure.

[0030] refer to Figures 1-6 , Figure 1-Figure 5 sectional views illustrating several steps of a semiconductor memory manufacturing process according to some embodiments of the present invention, Figure 6A flowchart illustrating the process steps of a semiconductor memory process 200 according to some embodiments of the present disclosure is shown. This cross-sectional view shows a portion of a memory device 100 including a bit line structure and a gate structure. A semiconductor substrate is processed to form the active region. Semiconductor processing typically involves several steps. A suitable semiconductor substrate, such as silicon (Si), is selected based on the desired device specifications and requirements. A thin layer of silicon dioxide (SiO2) may be located on the surface of the substrate. This can be achieved by thermal oxidation (exposing the substrate to a high-temperature, oxygen-rich environment) or by using deposition techniques such as chemical vapor deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD). A layer of photosensitive material (called photoresist) is applied over the oxide layer. The photoresist is then exposed to ultraviolet (UV) light through a mask containing the desired pattern. This step transfers the pattern to the photoresist. The exposed photoresist is developed using a suitable developer solution. This selectively removes either the exposed areas (positive photoresist) or the unexposed areas (negative photoresist) of the photoresist, leaving the desired pattern. An etching process, such as plasma etching or wet etching, is used to selectively remove the exposed oxide layer that will form the active region. Patterned photoresist acts as a mask, protecting areas where oxide is desired. Ion implantation is performed to introduce p-type or n-type dopant atoms into the exposed areas of the semiconductor substrate where active devices will form. The dopants alter the substrate's electrical properties, creating areas with the desired conductive characteristics. The implanted dopants are activated, and annealing repairs any lattice damage caused by the implantation process. This step typically involves subjecting the substrate to high temperatures for a specific period of time.

[0031] In step 202 of process 200, a bitline structure 105 is formed in a bitline trench 101 of a substrate comprising silicon 102 and silicon oxide 103. The bitline structure 105 includes a bitline conductive portion 104 and a bitline dielectric portion 106. The bitline dielectric portion 106 is located on top of and in contact with the bitline conductive portion 104. The bitline conductive portion 104 includes a tungsten portion 104a, a polysilicon portion 104c, and a diffusion barrier layer 104b located between the tungsten portion 104a and the polysilicon portion 104c. Forming the bitline structure 105 in the bitline trench 101 of the substrate may include the following multi-step process. The bitline trench 101 may be formed in the substrate using photolithography and etching techniques. The polysilicon portion 104c may be formed as a conductive material in a semiconductor process. A diffusion barrier layer 104b may be deposited within the trench 101 to prevent material mixing between the tungsten portion 104a and the polysilicon portion 104c of the bitline structure 105. The tungsten portion 104a may be deposited on the diffusion barrier layer 104b. The bitline dielectric portion 106 may be formed by depositing a dielectric material over the bitline conductive portion 104. A planarization technique, such as chemical mechanical polishing (CMP), may be performed to remove excess dielectric material and produce a smooth, planar surface.

[0032] In step 204 of process 200 (refer to Figure 1 ), a silicon oxycarbide (SiCO) layer 108 may be formed as a low-k dielectric layer on the bit line structure 105. Forming the SiCO layer 108 may involve a variety of methods, and the selection depends on the specific manufacturing process and available equipment.

[0033] In one or more embodiments, the SiCO layer 108 may be formed by chemical vapor deposition (CVD). For example, the substrate may be loaded into a CVD chamber, a precursor gas containing silicon, carbon, and oxygen may be introduced into the CVD chamber, and deposition parameters such as temperature, pressure, and flow rate may be controlled to achieve a desired thickness and dielectric constant of the SiCO layer 108.

[0034] In one or more embodiments, the SiCO layer 108 may be formed by spin-on deposition. For example, a liquid precursor solution containing silicon, carbon, and oxygen may be applied to the substrate, the substrate may be spun to obtain a uniform layer, and the spin-on material may be cured to remove the solvent and produce the SiCO layer.

[0035] In one or more embodiments, the SiCO layer 108 may be formed by atomic layer deposition (ALD). For example, the substrate may be exposed to silicon, carbon, and oxygen precursor gases in a cyclical manner, with each exposure resulting in the deposition of a single layer, and the cycle is repeated until the desired SiCO thickness is achieved.

[0036] In one or more embodiments, the SiCO layer 108 may be formed by plasma enhanced chemical vapor deposition (PECVD). For example, the substrate may be loaded into a PECVD chamber, a combination of silicon, carbon, and oxygen precursors may be applied, and plasma may be introduced to enhance the chemical reaction and promote film deposition.

[0037] In one or more embodiments, the SiCO layer 108 may be formed by physical vapor deposition (PVD). For example, the substrate may be placed in a PVD chamber, a target containing silicon, carbon, and oxygen may be evaporated or sputtered, and the evaporated material may be condensed onto the substrate to form the SiCO layer.

[0038] In step 206 of process 200 (refer to Figure 2 ), a hydrogen (H2) plasma process HP can be performed to oxidize portions of the SiCO layer 108. For example, hydrogen (H2) gas can be introduced into the chamber of the plasma system to create a low-pressure environment. First, RF (radio frequency) or microwave power is applied to generate a plasma. This energized state of hydrogen gas promotes a chemical reaction with the SiCO layer, resulting in oxidation. Process parameters such as gas flow rate, pressure, and power can be controlled to achieve the desired oxidation level.

[0039] In one or more embodiments, portions (108a, 108c) of the SiCO layer 108 are oxidized by a hydrogen plasma process HP. In one or more embodiments, the hydrogen plasma process HP is performed by applying a bias voltage ranging from 100 V to 400 V. For example, the effect of plasma ion energy on the oxidized portion of the SiCO layer 108 has been studied by applying a bias voltage between 100 V and 400 V. In one or more embodiments, the SiCO layer is composed of 37% silicon, 48% oxygen, and 15% carbon. In one or more embodiments, the oxidized portion of the SiCO layer is composed of 60% oxygen and 40% silicon.

[0040] In step 208 of process 200 (see Figure 3 ), a hydrofluoric acid (HF) etching process is performed to remove the oxidized portion (108a, 108c) of the SiCO layer. In one or more embodiments, the HF etching process can be HF etching diluted with deionized water, such as an HF 1% acid solution. In one or more embodiments, the damage consumption of the SiCO layer 108 has been measured as a function of the HF 1% immersion time. For a 100V bias applied during the H2 plasma, the oxidized portion of the SiCO layer has a thickness of approximately 6 nanometers. For a 250V bias applied during the H2 plasma, the oxidized portion of the SiCO layer has a thickness of approximately 10 nanometers. For a 400V bias applied during the H2 plasma, the oxidized portion of the SiCO layer has a thickness of approximately 16 nanometers.

[0041] In step 210 of process 200 (refer to Figure 4 and Figure 5 ), a silicon nitride layer may be formed over the bit line structure 105 and the remaining SiCO layer 108b not etched by the hydrofluoric acid etching process. For example, a silicon nitride layer 110 may be deposited to refill the bit line trench 101 of the substrate, and a silicon nitride layer 112 may be deposited over the bit line structure 105 and the remaining SiCO layer 108b not etched by the hydrofluoric acid etching process. In one or more embodiments, the silicon nitride layer 112 may be deposited using atomic layer deposition (ALD) to form a conformal layer over the bit line structure 105 and the remaining SiCO layer 108b, with the silicon nitride layer 112 being connected to the silicon nitride layer 110.

[0042] In step 212 of process 200 (refer to Figure 5), a nitride etching process can be performed on the silicon nitride layers (110, 112) until the top 106t of the bit line dielectric 106 is exposed. In one or more embodiments, the top 108te of the remaining SiCO layer 108b is completely surrounded by the bit line dielectric 106 and the remaining silicon nitride layer 112 that is not etched by the nitride etching process. In one or more embodiments, the bottom 108be of the remaining SiCO layer is completely covered by the nitride layer 110a that is not etched by the nitride etching process. Therefore, there is no damage path (e.g., a path damaged by the bare etch) to the remaining SiCO layer 108b.

[0043] In summary, the semiconductor memory device manufacturing method disclosed herein utilizes a hydrogen plasma process to oxidize unwanted portions of the SiCO layer, and then performs a hydrofluoric acid etching process to remove the oxidized portions of the SiCO layer. Consequently, the remaining SiCO layer is completely covered by the silicon nitride layer, eliminating any path for damage to the remaining SiCO layer.

[0044] Although the present disclosure has been disclosed above in the form of embodiments, it is not intended to limit the present disclosure. Those skilled in the art may make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the appended claims.

[0045]

Explanation of symbols

[0046] To make the above and other objects, features, advantages and embodiments of the present disclosure more apparent and understandable, the accompanying symbols are explained as follows:

[0047] 100: Memory device

[0048] 101: Bit line trench

[0049] 102: Silicon

[0050] 103: Silicon oxide

[0051] 104: Bit line conductive portion

[0052] 104a: Tungsten

[0053] 104b: Diffusion barrier layer

[0054] 104c: Polysilicon part

[0055] 105: Bit line structure

[0056] 106: Bit line dielectric part

[0057] 106t: Top

[0058] 108:SiCO layer

[0059] 108a: Part

[0060] 108b: Remaining SiCO layer

[0061] 108c: Part

[0062] 108te: Top

[0063] 108be: bottom

[0064] 110: Silicon nitride layer

[0065] 110a: Nitride layer

[0066] 112: Silicon nitride layer

[0067] 200: Craftsmanship

[0068] 202: Steps

[0069] 204: Steps

[0070] 206: Steps

[0071] 208: Steps

[0072] 210: Steps

[0073] 212: Steps

[0074] HP: Hydrogen plasma process.

Claims

1. A method for manufacturing a semiconductor memory device, characterized in that: include: forming a bit line structure on a substrate, wherein the bit line structure includes a bit line conductive portion and a bit line dielectric portion; forming a silicon oxycarbide (SiCO) layer on the bit line structure; performing a hydrogen plasma process on the SiCO layer; performing a hydrofluoric acid etching process on the SiCO layer; and A silicon nitride layer is formed over the bit line structure and the remaining portion of the SiCO layer not etched by the hydrofluoric acid etching process.

2. The method according to claim 1, characterized in that Also includes: A nitride etching process is performed on the silicon nitride layer until the bit line dielectric portion is exposed.

3. The method according to claim 1, characterized in that The hydrogen plasma process is performed by applying a bias voltage of 100V to 400V.

4. The method according to claim 1, wherein The SiCO layer is composed of 37% silicon, 48% oxygen and 15% carbon.

5. The method according to claim 1, characterized in that The bit line dielectric portion is located on top of the bit line conductive portion.

6. The method according to claim 1, characterized in that The bit line conductive portion includes a tungsten portion, a polysilicon portion, and a diffusion barrier layer located between the tungsten portion and the polysilicon portion.

7. The method according to claim 2, characterized in that The top of the remaining SiCO layer is completely surrounded by the bit line dielectric portion and the remaining silicon nitride layer that is not etched by the nitride etching process.

8. A method for manufacturing a semiconductor memory device, characterized in that: include: forming a bit line structure on a substrate, wherein the bit line structure includes a bit line conductive portion and a bit line dielectric portion; forming a silicon oxycarbide (SiCO) layer on the bit line structure; performing a hydrogen plasma process to oxidize a portion of the SiCO layer; performing a hydrofluoric acid etching process to remove the oxidized portion of the SiCO layer; and A silicon nitride layer is formed over the bit line structure and the remaining portion of the SiCO layer not etched by the hydrofluoric acid etching process.

9. The method according to claim 8, characterized in that The SiCO layer is composed of 37% silicon, 48% oxygen and 15% carbon.

10. The method according to claim 8, characterized in that The oxidized portion of the SiCO layer consists of 60% oxygen and 40% silicon.

11. The method according to claim 8, characterized in that The hydrogen plasma process is performed by applying a bias voltage of 100V to 400V.

12. The method according to claim 8, characterized in that Also includes: A nitride etching process is performed on the silicon nitride layer until the bit line dielectric portion is exposed.

13. The method according to claim 12, characterized in that The top of the remaining SiCO layer is completely surrounded by the bit line dielectric portion and the remaining silicon nitride layer that is not etched by the nitride etching process.

14. The method according to claim 8, characterized in that The bit line dielectric portion is located on top of the bit line conductive portion.

15. The method according to claim 8, characterized in that The bit line conductive portion includes a tungsten portion, a polysilicon portion, and a diffusion barrier layer located between the tungsten portion and the polysilicon portion.

16. A semiconductor memory device, characterized in that: include: A bit line structure is located on the substrate, wherein the bit line structure includes a bit line conductive portion and a bit line dielectric portion; a silicon oxycarbide (SiCO) layer on the sidewalls of the bit line structure; and A silicon nitride layer is located on the sidewall of the bit line structure, wherein a top of the SiCO layer is completely surrounded by the bit line dielectric portion and the silicon nitride layer.

17. The semiconductor memory device according to claim 16, wherein A top portion of the bit line dielectric is not covered by the SiCO layer.

18. The semiconductor memory device according to claim 16, wherein The SiCO layer is composed of 37% silicon, 48% oxygen and 15% carbon.

19. The semiconductor memory device according to claim 16, wherein The bit line dielectric portion is located on top of the bit line conductive portion.

20. The semiconductor memory device according to claim 16, wherein The bit line conductive portion includes a tungsten portion, a polysilicon portion, and a diffusion barrier layer located between the tungsten portion and the polysilicon portion.

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