Multi-threshold voltage integration scheme for semiconductor devices

Abstract

Embodiments of the present invention advantageously provide a method of manufacturing a semiconductor device having multiple threshold voltage capability in a scaled space between nanosheets in an advanced GAA node. One or more embodiments provide an integration scheme to advantageously reduce gate resistance by incorporating n- / p-dipoles with an intermediate bandgap metal with low resistance to achieve a desired work function and low resistance metal gate. In one or more embodiments, the intermediate bandgap metal is used to fill the nanosheets and as a liner for subsequent filling with the low resistance metal. After dipole processing, instead of filling surrounding gate nanosheets with conventional n or p metals, in one or more embodiments, the nanosheets are advantageously filled with a single work function intermediate energy gap metal to achieve n and p work functions. If the work function is shifted in either of the band edges of the P-dipole or the N-dipole after dipole processing, the intermediate bandgap material may also shift the band edges in the opposite manner.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor device fabrication, and in particular, to transistors. More particularly, embodiments of the present invention relate to gate-all-around (GAA) devices and methods of fabricating GAA devices with reduced metal gate resistance. Background Art

[0002] Integrated circuits have evolved into complex devices that can include millions of transistors, capacitors, and resistors on a single chip. During the evolution of integrated circuits, functional density (i.e., the number of interconnected devices per chip area) has gradually increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased.

[0003] A transistor is a circuit component or element typically formed on a semiconductor device. Depending on the circuit design, many transistors may be formed on a semiconductor device, in addition to capacitors, inductors, resistors, diodes, wires, or other components. Integrated circuits incorporate planar field-effect transistors (FETs), in which current flows through a semiconductor channel between a source and a drain in response to a voltage applied to a control gate.

[0004] As device dimensions have shrunk, device geometries and materials have struggled to maintain switching speeds without triggering failures. Several new technologies have emerged that allow chip designers to continue reducing gate lengths. Controlling the dimensions of device structures is a key challenge for current and future technology generations.

[0005] A key challenge in transistor technology is to reduce metal gate resistance while shrinking transistors, especially in GAA structures. Current approaches using existing n- or p-metal layers in combination with dipoles result in high gate resistance. This high gate resistance can lead to degradation in device performance. Due to changes in fundamental properties such as threshold voltage (V t ), the scaling of currently used materials for N- and P-MOS has become a challenge. In addition, the migration of transistor technology from planar to FinFET to GAA devices requires conformal work function layers for multi-threshold voltages (multi-Vt). t The adjustment range will be limited by the variation of film thickness as the device size is further reduced.

[0006] In FINFETs and earlier GAA architectures, multiple threshold voltages are achieved by scaling the thickness of the PMOS and NMOS work function materials, including but not limited to titanium nitride (TiN), titanium aluminum carbide (TiAlC), tungsten carbonitride (WCN), and / or titanium silicon nitride (TiSiN). As GAA structures scale further, the distance between nanosheets decreases to less than 4nm. Therefore, further reductions in film thickness are no longer feasible for achieving multiple threshold voltages in advanced GAA nodes.

[0007] Therefore, there is a need for a semiconductor device and method of fabricating such a semiconductor device having multi-threshold voltage capability in a scaling space between nanosheets in advanced GAA nodes. Summary of the Invention

[0008] One or more embodiments relate to a method for fabricating a semiconductor device. In some embodiments, the method includes forming a P-dipole stack and an N-dipole stack on a semiconductor substrate, each of the P-dipole stack and the N-dipole stack being formed on a top surface of a channel, the channel being located between a source and a drain on the semiconductor substrate; and depositing a fill layer comprising a mid-gap fill material on each of the P-dipole stack and the N-dipole stack.

[0009] Additional embodiments relate to methods for fabricating semiconductor devices. In some embodiments, the method includes forming a P-dipole stack on a substrate by depositing an interfacial layer on a top surface of a channel, the channel being located between a source and a drain on the substrate; depositing a high-κ dielectric layer on the interfacial layer; and depositing a dipole film on the high-κ dielectric layer; and forming an N-dipole stack on the substrate by depositing an interfacial layer on a top surface of the channel, the channel being located between a source and a drain on the substrate; depositing a high-K dielectric layer on the interfacial layer; and depositing a dipole film on the high-κ dielectric layer. In some embodiments, the method further includes annealing the P-dipole stack and the N-dipole stack to drive metal atoms from the dipole film; etching the P-dipole stack and the N-dipole stack to expose the high-κ dielectric layer; and depositing a mid-gap material on the exposed high-κ dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] A more detailed description of the invention, briefly summarized above, can be obtained by reference to the embodiments of the invention, some of which are illustrated in the accompanying drawings, so that the above-mentioned features of the invention can be understood in detail. However, it will be noted that the accompanying drawings illustrate only exemplary embodiments of the invention and are therefore not to be considered limiting of the scope of the invention, as the invention may admit to other equally effective embodiments. The embodiments described herein are illustrated by way of example and are not limited to the illustrations in the accompanying drawings, in which like reference numerals indicate similar elements.

[0011] Figure 1AA process flow diagram illustrating a method according to one or more embodiments is shown;

[0012] Figure 1B A process flow diagram illustrating a method according to one or more embodiments is shown;

[0013] Figure 2A illustrates a cross-sectional view of a semiconductor substrate according to one or more embodiments;

[0014] Figure 2B illustrates a cross-sectional view of a semiconductor substrate according to one or more embodiments;

[0015] Figure 3A illustrates a cross-sectional view of a semiconductor substrate according to one or more embodiments;

[0016] Figure 3B illustrates a cross-sectional view of a semiconductor substrate according to one or more embodiments;

[0017] Figure 4A illustrates a cross-sectional view of a semiconductor substrate according to one or more embodiments;

[0018] Figure 4B depicts a cross-sectional view of a semiconductor substrate according to one or more embodiments; and

[0019] Figure 5 A cluster tool is depicted in accordance with one or more embodiments. DETAILED DESCRIPTION

[0020] Before describing several exemplary embodiments of the present invention, it should be understood that the present invention is not limited to the details of the architecture or processing steps described in the following description, and that the present invention is capable of other embodiments and of being practiced or carried out in various ways.

[0021] As used herein, the term "about" means approximately or nearly, and in the context of a stated value or range, means a variation of ±15% or less of that value. For example, a difference of ±14%, ±10%, ±5%, ±2%, or ±1% would meet the definition of about.

[0022] As used in this specification and the appended claims, the terms "substrate" or "wafer" refer to a surface or portion of a surface on which processing is performed. Unless the context clearly indicates otherwise, one of ordinary skill in the art will also understand that reference to a substrate may refer to only a portion of the substrate. Furthermore, reference to deposition on a substrate may refer to both a bare substrate and a substrate having one or more films or features deposited or formed thereon.

[0023] As used herein, "substrate" refers to any substrate or material surface formed on a substrate upon which film processing is performed during a manufacturing process. For example, substrate surfaces upon which processing may be performed include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other material, such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, without limitation, semiconductor wafers. Substrates may be exposed to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In addition to film processing directly on the surface of the substrate itself, any of the disclosed film processing steps may also be performed on underlying layers formed on the substrate, as described in greater detail below, and the term "substrate surface" is intended to include such underlying layers as indicated by the context. Thus, for example, where a film / layer or portion of a film / layer has been deposited onto a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0024] As used in this specification and the appended claims, the terms "precursor," "reactant," "reactant gas," and the like are used interchangeably to refer to any gaseous species that can react with a substrate surface.

[0025] The term “on” indicates that there is direct contact between elements. The term “directly on” indicates that there is direct contact between elements with no intervening elements.

[0026] As used herein, "atomic layer deposition" or "cyclic deposition" refers to the sequential exposure of two or more reactive compounds to deposit a layer of material on a substrate surface. The substrate or portions of the substrate are separately exposed to the two or more reactive compounds introduced into a reaction zone of a processing chamber. In a time-domain ALD process, the exposure to each reactive compound is separated by a time delay to allow each compound to adhere and / or react on the substrate surface and then be purged from the processing chamber. The reactive compounds are said to be exposed to the substrate sequentially. In a spatial ALD process, different portions of the substrate surface or materials on the substrate surface are simultaneously exposed to the two or more reactive compounds, such that any given point on the substrate is not substantially simultaneously exposed to more than one reactive compound. As used in this specification and the appended claims, as will be understood by one of ordinary skill in the art to which the invention pertains, the term "substantially" as used in this context means that there is a possibility that a small portion of the substrate may be exposed to multiple reactive gases simultaneously due to diffusion, and that such simultaneous exposure is not intentional.

[0027] In one aspect of a time-domain ALD process, a first reactant gas (i.e., a first precursor or compound A) is pulsed into the reaction region, followed by a first time delay. Next, a second precursor or compound B is pulsed into the reaction region, followed by a second delay. During each time delay, a purge gas, such as argon, is introduced into the process chamber to purge the reaction region or remove any residual reactant compounds or reaction byproducts from the reaction region. Alternatively, the purge gas may flow continuously during the entire deposition process, such that only the purge gas flows during the time delay between pulses of the reactant compounds. The reactant compounds are either pulsed until a desired film or film thickness is formed on the substrate surface. In either scenario, the pulsing compound A, purge gas, compound B, and purge gas of the ALD process is a cycle. A cycle can begin with either compound A or compound B, and continue in that order until a film having a predetermined thickness is achieved.

[0028] In one embodiment of a spatial ALD process, a first reactant gas and a second reactant gas (e.g., nitrogen) are delivered simultaneously to the reaction region but separated by an inert gas curtain and / or a vacuum curtain. The substrate is moved relative to the gas delivery apparatus such that any given point on the substrate is exposed to both the first and second reactant gases.

[0029] As used herein, the term "conformal" means a layer that adapts to the contours of a feature or layer. The conformality of a layer is typically quantified by the ratio of the average thickness of the layer deposited on the sidewalls of the feature to the average thickness of the same deposited layer on an area or upper surface of the substrate. A transistor is a circuit component or element typically formed on a semiconductor device. Depending on the circuit design, a transistor is formed on a semiconductor device in addition to capacitors, inductors, resistors, diodes, wires, or other components. Generally, a transistor includes a gate formed between a source region and a drain region. In one or more embodiments, the source region and the drain region include doped regions of the substrate and exhibit a doping profile suitable for a particular application. The gate is positioned above the channel region and includes a gate dielectric interposed between the gate electrode and the channel region in the substrate.

[0030] As used herein, the term "field effect transistor" or "FET" refers to a transistor that uses an electric field to control the electrical behavior of the device. A field effect transistor is a voltage controlled device in which the current carrying capability of the field effect transistor is varied by applying an electric field. Field effect transistors typically exhibit very high input impedance at low temperatures. The conductivity between the drain and source terminals is controlled by the electric field in the device, which is generated by the voltage difference between the body of the device and the gate. The three terminals of a FET are the source (S), through which carriers enter the channel; the drain (D), through which carriers leave the channel; and the gate (G), which regulates the conductivity of the channel. Conventionally, the current entering the channel at the source (S) is denoted as I S and the current entering the channel at the drain (D) is labeled I D The drain-to-source voltage is denoted as V DS By applying a voltage to the gate (G), the current entering the channel at the drain (i.e., I D ).

[0031] A metal oxide semiconductor field-effect transistor (MOSFET) is a type of field-effect transistor (FET) used in integrated circuits and high-speed switching applications. A MOSFET has an insulated gate, the voltage across which determines the device's conductivity. The ability to vary conductivity with the amount of applied voltage is used to amplify or switch electronic signals. A MOSFET is based on the modulation of charge concentration across a metal oxide semiconductor (MOS) capacitor between a bulk electrode and a gate electrode, which is located above the bulk and insulated from all other device regions by a gate dielectric layer. Compared to a MOS capacitor, a MOSFET includes two additional terminals (source and drain), each connected to a separate, highly doped region separated by a bulk region. These regions can be either p-type or n-type, but they are all of the same type, opposite to the bulk region. The source and drain (unlike the bulk) are highly doped and are designated by a "+" sign after the doping type.

[0032] If the MOSFET is an n-channel, or nMOS FET, the source and drain are n+ regions, and the bulk is the p-type substrate region. If the MOSFET is a p-channel, or pMOS FET, the source and drain are p+ regions, and the bulk is the n-type substrate region. The source is so named because it is the source of charge carriers (electrons for n-channel and holes for p-channel) that flow through the channel; similarly, the drain is where the charge carriers leave the channel.

[0033] An nMOS FET is made of n-type source and drain and a p-type substrate. When voltage is applied to the gate, holes in the bulk (p-type substrate) are driven away from the gate. This allows an n-type channel to form between the source and drain, and current is carried through the induced n-type channel by electrons from the source to the drain. Logic gates and other digital devices implemented using NMOS are said to have NMOS logic. There are three operating modes in NMOS, called cutoff, triode, and saturation. Circuits with NMOS logic gates dissipate static power when the circuit is idle because DC current flows through the logic gate when the output is low.

[0034] A pMOS FET is made of p-type source and drain electrodes and an n-type substrate. When a positive voltage is applied between the source and gate (negative voltage between the gate and source), a p-type channel forms between the source and drain electrodes, with opposite polarity to the channel. Current is carried through the induced p-type channel by holes from the source to the drain. A high voltage on the gate causes the PMOS to not conduct, while a low voltage on the gate causes it to conduct. Logic gates and other digital devices implemented using PMOS are said to have PMOS logic. PMOS technology is low-cost and has good noise immunity.

[0035] In NMOS, the carriers are electrons, while in PMOS, the carriers are holes. When a high voltage is applied to the gate, NMOS will turn on, while PMOS will not. In addition, when a low voltage is applied to the gate, NMOS will not turn on, while PMOS will turn on. NMOS is considered faster than PMOS because the carriers in NMOS are electrons, and electrons travel twice as fast as holes, which are carriers in PMOS. However, PMOS devices are more immune to interference than NMOS devices. Furthermore, NMOS ICs will be smaller than PMOS ICs (giving the same functionality) because NMOS can provide half the impedance provided by PMOS (which has the same geometry and operating conditions).

[0036] As used herein, the term "fin field-effect transistor (FinFET)" refers to a MOSFET transistor constructed on a substrate in which the gate is placed on two, three, or four sides of the channel or wrapped around the channel, forming a dual-gate structure. FinFET devices have been given the generic name FinFET because the source / drain regions form a "fin" on the substrate. FinFET devices have fast switching times and high current density.

[0037] As used herein, the term "gate-all-around (GAA)" refers to electronic devices, such as transistors, in which gate material surrounds a channel region on all sides. The channel region of a GAA transistor may include nanowires, nanoslabs, nanosheets, strip-shaped channels, or other suitable channel configurations known to those of ordinary skill in the art. In one or more embodiments, the channel region of a GAA device has multiple vertically spaced horizontal nanowires or strips, making the GAA transistor a stacked horizontal gate-all-around (hGAA) transistor.

[0038] As used herein, the term "nanowire" refers to a nanostructure with a diameter of less than one nanometer (10 -9 Nanowires can also be defined as having a length to width ratio greater than 1000. Alternatively, nanowires can be defined as structures having a thickness or diameter limited to tens of nanometers or less and an unlimited length. Nanowires are used in transistors and some laser applications, and in one or more embodiments, the nanowires are made of semiconductor materials, metallic materials, insulating materials, superconducting materials, or molecular materials. In one or more embodiments, nanowires are used in transistors for logic CPUs, GPUs, MPUs, and volatile (e.g., DRAM) and non-volatile (e.g., NAND) devices. As used herein, the term "nanosheet" refers to a two-dimensional nanostructure having a thickness in the range of from about 0.1 nm to about 1000 nm, or from 0.5 nm to 500 nm, or from 0.5 nm to 100 nm, or from 1 nm to 500 nm, or from 1 nm to 100 nm, or from 1 nm to 50 nm.

[0039] One or more embodiments advantageously relate to a dipole process for a GAA structure that improves V t In some embodiments, the V t Set to ±300mV.

[0040] Embodiments of the present invention advantageously provide methods for fabricating semiconductor devices with multi-threshold voltage capabilities in the scaled space between nanosheets in advanced GAA nodes. The space between the nanosheets can be filled with a single material, such as a mid-gap work function material. If the work function is shifted to either the band edge of the P-dipole or the N-dipole outside of dipole processing, the mid-gap material can also be selected to shift the band edge in the opposite manner. For example, the methods described herein can shift the band edge from a very low V t (ULV t ), which are the majority of P-dipole and / or N-dipole band edges, shifted to low V t (LV t ) or standard Vt (SV t ), or mid-gap: high V t (HV t ).

[0041] One or more embodiments provide an integrated solution to advantageously reduce gate resistance by combining n- / p-dipoles with a mid-gap metal with low resistance to achieve a desired work function and a low-resistance metal gate. In one or more embodiments, the mid-gap metal is used to fill the nanosheets and act as a liner for subsequent filling with a low-resistance metal. After dipole processing, instead of filling the wraparound gate nanosheets with traditional n- or p-metal, in one or more embodiments, the nanosheets are advantageously filled with a mid-gap metal to achieve both n and p work functions. In one or more embodiments, the fill layer is deposited by atomic layer deposition (ALD), comprising exposing each of a p-dipole stack and an n-dipole stack to a metal precursor and a reactant to form a mid-gap fill material that conformally wraps around the nanosheets. In one or more embodiments, the metal precursor comprises one or more of a metal halide precursor or an organometallic precursor.

[0042] It has been advantageously discovered that, depending on the metal precursor selected, the methods described herein can reduce or increase the effective work function (eWF) of a film stack in a semiconductor device. Thus, by using different mid-gap fill materials, tuning of the effective work function can be accomplished. t Having been configured via dipole processing, embodiments of the present invention advantageously provide methods for using a single work function material with a mid-gap work function on both P- and N-FET structures.

[0043] Embodiments of the present invention are illustrated by the accompanying drawings, which depict devices (e.g., transistors) and processes for forming the transistors according to one or more embodiments of the present invention. The processes shown are merely illustrative of possible uses for the disclosed processes, and one of ordinary skill in the art will recognize that the disclosed processes are not limited to the applications shown.

[0044] FIG1 illustrates a flow chart of a method 10 for fabricating a semiconductor device according to one or more embodiments of the present invention. Method 10 begins at operation 12 by forming a P-dipole stack and an N-dipole stack on a semiconductor substrate. The P-dipole stack and the N-dipole stack may be formed by operations 22 through 26 of method 20 shown in FIG2 , as further described below. In some embodiments, at operation 12, each of the P-dipole stack and the N-dipole stack is formed on a top surface of a channel located between a source and a drain on the semiconductor substrate. At operation 14, method 10 includes depositing a fill layer comprising an inter-gap filler material on each of the P-dipole stack and the N-dipole stack. In one or more embodiments, operation 14 of method 10 includes depositing the fill layer by an atomic layer deposition (ALD) process, comprising exposing each of the P-dipole stack and the N-dipole stack to a metal precursor and a reactant to form the inter-gap filler material. In some embodiments, the metal precursor comprises one or more of an organometallic precursor or a metal halide precursor. In one or more embodiments, the mid-gap fill material is deposited at a temperature in the range of 300° C. to 500° C., including all subranges and values ​​therebetween. In one or more embodiments, the mid-gap fill material is deposited at a pressure in the range of 1 Torr to 50 Torr, including all subranges and values ​​therebetween.

[0045] In some embodiments, the mid-gap filler material comprises a metal or metal alloy having an eWF in the range of from 4.5 to 4.8. In some embodiments, the mid-gap filler material comprises one or more of magnesium (Mg), lanthanum (La), yttrium (Y), aluminum (Al), manganese (Mn), zirconium (Zr), tantalum (Ta), vanadium (V), zinc (Zn), titanium (Ti), niobium (Nb), tin (Sn), tungsten (W), molybdenum (Mo), ruthenium (Ru), or antimony (Sb), or alloys thereof, and the reactant comprises hydrogen (H2), 1-methyl-3,6-bis(trimethylsilyl)-1,4-cyclohexadiene (CHD), or 1,4-bis(trimethylsilyl)-1,4-dihydropyridine (DHP) one or more.

[0046] In some embodiments, the mid-gap filler material comprises a silicide of one or more of hafnium (Hf), zirconium (Zr), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), niobium (Nb), vanadium (V), cobalt (Co), manganese (Mn), nickel (Ni), tungsten (W), magnesium (Mg), palladium (Pd), ruthenium (Ru), or rhenium (Re), and the reactant comprises silane (SiH4), disilane (Si2H6), trisilane (Si3H8), or tetrasilane (Si4H 10 )

[0047] In some embodiments, the mid-gap filler material comprises a nitride, carbide, sulfide, or germanide of one or more of hafnium (Hf), magnesium (Mg), lanthanum (La), yttrium (Y), aluminum (Al), manganese (Mn), zirconium (Zr), tantalum (Ta), vanadium (V), zinc (Zn), titanium (Ti), niobium (Nb), tin (Sn), tungsten (W), molybdenum (Mo), ruthenium (Ru), or antimony (Sb). In some embodiments, the nitride reactant comprises any suitable nitrogen-containing compound, including but not limited to one or more of ammonia (NH3), hydrazine (N2H4), nitrogen (N2) plasma, nitrogen (N2) radicals, a mixture of nitrogen (N2) plasma and hydrogen (H2) plasma, or a mixture of nitrogen (N2) radicals and hydrogen (H2) radicals. In some embodiments, the carbide reactant comprises any suitable carbon-containing compound, including but not limited to one or more of methane (CH4) or ethylene (C2H4). In some embodiments, the sulfide reactant comprises any suitable sulfur-containing compound, including but not limited to hydrogen sulfide (H2S). In some embodiments, the germanide reactant comprises any suitable germanium-containing compound, including but not limited to one or more of germanium tetrachloride (GeCl4) or germanium tetrahydride (GeH4).

[0048] FIG2 illustrates a flow chart of a method 20 for fabricating a semiconductor device according to one or more embodiments of the present invention. Method 20 includes forming a P-dipole stack and forming an N-dipole stack on a semiconductor substrate. In some embodiments, each of the P-dipole stack and the N-dipole stack is independently formed through operations 22 through 28. As used herein, operations 22 through 28 may be referred to as "dipole processing operations." In operation 22, an interfacial layer is deposited on a top surface of a channel located between a source and a drain on the semiconductor substrate. In operation 24, a high-κ dielectric layer is deposited on the interfacial layer. In operation 26, a dipole film is deposited on the high-κ dielectric layer to form a dipole region. Each of the P-dipole stack and the N-dipole stack may be independently referred to as a "film stack." In some embodiments, the film stack includes an interfacial layer deposited on a top surface of a channel located between a source and a drain on the substrate, a high-κ dielectric layer deposited on the interfacial layer, and a dipole film deposited on the high-κ dielectric layer to form a dipole region.

[0049] In some embodiments, an interfacial layer is deposited using a deposition technique such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin coating, or other insulating layer deposition techniques known to those of ordinary skill in the art at operation 22. In one or more embodiments, the interfacial layer is formed by etching and forming an oxide on the surface.

[0050] In some embodiments, at operation 22, a wet chemical technique is performed to form the interface layer. The wet chemical technique may be any technique known to one of ordinary skill in the art. In some embodiments, the wet chemical technique includes a pre-cleaning process. In some embodiments, the pre-cleaning process includes using an SC-1 solution containing one or more of ozone, ammonium hydroxide, or hydrogen peroxide. In some embodiments, the pre-cleaning process includes using an SC-1 solution without ozone, ammonium hydroxide, or hydrogen peroxide. In some embodiments, after using the SC-1 solution, the pre-cleaning process includes using diluted hydrofluoric acid (diluted HF) containing a dilute HF greater than 100:1, such as 130:1, to etch away native oxide on the substrate to form a hydrophobic surface (i.e., the interface layer).

[0051] In some embodiments, a high-κ dielectric layer is deposited on the interfacial layer using a deposition technique such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin coating, or other insulating layer deposition techniques known to one of ordinary skill in the art at operation 24. In some embodiments, the high-κ dielectric layer is conformally deposited by ALD at operation 24.

[0052] In some embodiments, at operation 26 , a dipole film is deposited on the high-κ dielectric layer using a deposition technique such as, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin coating, or other insulating layer deposition techniques known to one of ordinary skill in the art.

[0053] In some embodiments, at operation 26, a dipole film is deposited on the high-κ dielectric layer by ALD. In some embodiments, the ALD cycle includes exposing the substrate to a pulse of a metal precursor to form the dipole film on the surface of the semiconductor substrate. The metal precursor is then purged from the processing chamber or removed from a reaction zone adjacent to the substrate surface. The substrate with the dipole film thereon is then exposed to a pulse of a reactant to form a metal-containing layer on the substrate surface. The reactant is then purged from the processing chamber or removed from a reaction zone adjacent to the substrate surface.

[0054] In some embodiments, at operation 26, a dipole film is deposited on the high-κ dielectric layer by ALD at a temperature of 500° C. or less and a pressure of 50 Torr or less. In some embodiments, the temperature is in the range of 100° C. to 500° C., or in the range of 150° C. to 450° C., or in the range of 200° C. to 400° C., or in the range of 250° C. to 350° C. In some embodiments, the pressure is in the range of 0 mTorr to 50 Torr, or in the range of 100 mTorr to 50 Torr, or in the range of 1 Torr to 40 Torr, or in the range of 10 Torr to about 35 Torr, or in the range of 20 Torr to 30 Torr. Without wishing to be bound by theory, it is believed that when the dipole film is deposited on the high-κ dielectric layer by ALD at a temperature of, for example, 450° C. or 500° C., metal atoms from the dipole film are driven into the high-κ dielectric layer.

[0055] In some embodiments, methods 10, 20 optionally include, at operation 28, annealing the substrate at a temperature less than or equal to 1100° C. to drive atoms from the dipole film into the high-κ dielectric layer. In some embodiments, methods 10, 20 optionally include annealing the substrate at a temperature less than or equal to 1050° C. to drive atoms from the dipole film into the high-κ dielectric layer. In some embodiments, the temperature is in the range of 500° C. to 1100° C., including in the range of 500° C. to 1050° C., including in the range of 600° C. to 1025° C., in the range of 700° C. to 1000° C., in the range of 750° C. to 950° C., or in the range of 800° C. to 900° C.

[0056] Without wishing to be bound by theory, it is contemplated that annealing the substrate at operation 28 drives an increased number of atoms from the dipole film into one or more of the interfacial layer or the high-κ dielectric layer, compared to processes in which no annealing occurs. In one or more embodiments, annealing the substrate comprises rapid thermal processing (RTP). The RTP can be any suitable process known to one of ordinary skill in the art. Without wishing to be bound by theory, the RTP is believed to densify and improve the physical properties of the deposited dipole film.

[0057] Without wishing to be bound by theory, it is contemplated that a dipole region comprising a channel having an n-type material or a p-type material and a dipole film as described above simplifies existing integration processes and reduces integration costs. Furthermore, when atoms from the dipole film (such as metal atoms) are embedded in the interfacial layer and / or the high-κ dielectric layer, a dipole region is formed and oxidation is contemplated to be reduced, potentially lowering the required annealing temperature.

[0058] Method 20 includes, at operation 30, etching the film stack (each of the P-dipole stack and the N-dipole stack) to expose the high-κ dielectric layer. At operation 28, the dipole film is removed to expose the high-κ dielectric layer. The etching process can be any suitable etching process known to one of ordinary skill in the art. In some embodiments, the etching process includes a wet etching process or a dry etching process. In some embodiments, the etching process includes a wet etching process.

[0059] Without wishing to be bound by theory, when methods 10 and 20 include annealing the substrate at a temperature of 1050° C. or less to drive atoms from the dipole film into the high-κ dielectric layer, the high-κ dielectric layer exhibits properties of the dipole film. In other words, after performing an etching process to remove the dipole film and expose the high-κ dielectric layer, the high-κ dielectric layer exhibits dipole properties due to the annealing process.

[0060] At operation 32, method 20 includes depositing an inter-gap-filling material on the exposed high-κ dielectric layer of each of the film stack (the P-dipole stack and the N-dipole stack). In some embodiments, operation 32 of method 20 includes a process identical to operation 14 of method 10, including an atomic layer deposition (ALD) process, including exposing each of the P-dipole stack and the N-dipole stack to a metal precursor and a reactant to form the inter-gap-filling material. In some embodiments, the metal precursor includes one or more of an organometallic metal precursor or a metal halide precursor. In one or more embodiments, the inter-gap-filling material is deposited at a temperature in the range of 300° C. to 500° C. and a pressure in the range of 1 Torr to 50 Torr, including all subranges and values ​​therebetween.

[0061] In some embodiments, the mid-gap filler material comprises one or more of magnesium (Mg), lanthanum (La), yttrium (Y), aluminum (Al), manganese (Mn), zirconium (Zr), tantalum (Ta), vanadium (V), zinc (Zn), titanium (Ti), niobium (Nb), tin (Sn), tungsten (W), molybdenum (Mo), ruthenium (Ru), or antimony (Sb), or alloys thereof, and the reactant comprises hydrogen (H2), 1-methyl-3,6-bis(trimethylsilyl)-1,4-cyclohexadiene (CHD), or 1,4-bis(trimethylsilyl)-1,4-dihydropyridine (DHP) one or more.

[0062] In some embodiments, the mid-gap filler material comprises a silicide of one or more of hafnium (Hf), zirconium (Zr), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), niobium (Nb), vanadium (V), cobalt (Co), manganese (Mn), nickel (Ni), tungsten (W), magnesium (Mg), palladium (Pd), ruthenium (Ru), or rhenium (Re), and the reactant comprises silane (SiH4), disilane (Si2H6), trisilane (Si3H8), or tetrasilane (Si4H 10 )

[0063] In some embodiments, the mid-gap filler material comprises a nitride, carbide, sulfide, or germanide of one or more of hafnium (Hf), magnesium (Mg), lanthanum (La), yttrium (Y), aluminum (Al), manganese (Mn), zirconium (Zr), tantalum (Ta), vanadium (V), zinc (Zn), titanium (Ti), niobium (Nb), tin (Sn), tungsten (W), molybdenum (Mo), ruthenium (Ru), or antimony (Sb). In some embodiments, the nitride reactant comprises any suitable nitrogen-containing compound, including but not limited to one or more of ammonia (NH3), hydrazine (N2H4), nitrogen (N2) plasma, nitrogen (N2) radicals, a mixture of nitrogen (N2) plasma and hydrogen (H2) plasma, or a mixture of nitrogen (N2) radicals and hydrogen (H2) radicals. In some embodiments, the carbide reactant comprises any suitable carbon-containing compound, including but not limited to one or more of methane (CH4) or ethylene (C2H4). In some embodiments, the sulfide reactant comprises any suitable sulfur-containing compound, including but not limited to hydrogen sulfide (H2S). In some embodiments, the germanide reactant comprises any suitable germanium-containing compound, including but not limited to one or more of germanium tetrachloride (GeCl4) or germanium tetrahydride (GeH4).

[0064] Figure 2A 、 2B , 3A, 3B, 4A, and 4B are cross-sectional views of a semiconductor device (eg, transistor) 100 according to one or more embodiments. Figure 2A 、 2B , 3A, 3B, 4A, and 4B can be shown in FIG. Figure 1A and 1B The method 10, 20 is used to manufacture.

[0065] In one or more embodiments, the semiconductor device 100 includes a semiconductor substrate 102 having a top surface. The semiconductor substrate 102 can be any suitable substrate material. In one or more embodiments, the semiconductor substrate 102 includes a semiconductor material such as silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium phosphide (InP), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), germanium (Ge), silicon germanium (SiGe), copper indium gallium selenide (CIGS), other semiconductor materials, or any combination thereof. In one or more embodiments, the semiconductor substrate 102 includes one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), indium (In), phosphorus (P), copper (Cu), or selenium (Se). Although a few examples of materials from which semiconductor substrate 102 may be formed are described herein, any material upon which passive and active electronic devices (e.g., transistors, memory, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic device) may be constructed falls within the spirit and scope of the present invention.

[0066] In one or more embodiments, semiconductor substrate 102 is a p-type or n-type substrate. As used herein, the term "n-type" refers to a semiconductor created by doping an intrinsic semiconductor with an electron-donating element during fabrication. The term n-type comes from the negative charge of electrons. In n-type semiconductors, electrons are the majority carriers and holes are the minority carriers. As used herein, the term "p-type" refers to the positive charge of the wells (or holes). In contrast to n-type semiconductors, p-type semiconductors have a greater concentration of holes than electrons. In p-type semiconductors, holes are the majority carriers and electrons are the minority carriers.

[0067] In some embodiments, the source region 104a is on the top surface of the semiconductor substrate 102. In one or more embodiments, the source region 104a has a source electrode and a source contact (not shown). The drain region 104b is on the top surface of the semiconductor substrate 102, opposite to the source region 104a. In one or more embodiments, the drain region 104b has a drain electrode and a drain contact (not shown).

[0068] In one or more embodiments, the source region 104a and / or the drain region 104b can be any suitable material known to one of ordinary skill in the art. In one or more embodiments, the source region 104a and / or the drain region 104b can have more than one layer. For example, the source region 104a and / or the drain region 104b can independently include three layers. In one or more embodiments, the source region 104a and the drain region 104b can independently include one or more of copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), platinum (Pt), phosphorus (P), germanium (Ge), silicon (Si), aluminum (Al), or zirconium (Zr). In some embodiments, the source region 104a and the drain region 104b may independently include a bottom layer having doped epitaxial silicon (e.g., SiGe, SiP, and the like), a second layer of silicide, which may contain nickel (Ni), titanium (Ti), aluminum (Al), and the like, and a third or top layer, which may be a metal such as, but not limited to, cobalt, tungsten, ruthenium, and the like.

[0069] In some embodiments, the source region 104a and the drain region 104b may be elevated source / drain regions formed by epitaxial growth. In one or more embodiments, the source contact and / or the drain contact may be independently selected from one or more of nitrogen (N), copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), or platinum (Pt). In one or more embodiments, the source contact and / or the drain contact are formed by any suitable process known to one of ordinary skill in the art, including but not limited to ALD, CVD, PVD, MBE, MOCVD, spin coating, or other isolation layer deposition techniques known to one of ordinary skill in the art.

[0070] In one or more embodiments, the channel 106 is located between the source region 104a and the drain region 104b. In one or more embodiments, the dipole region 108 covers the channel 106 and is in contact with one or more of the channel 106, the source region 104a, and the drain region 104b. In one or more embodiments, the dipole region 108 has a thickness in the range of 2 nm to 6 nm, including in the range of 2.5 nm to 5.5 nm, in the range of 3 nm to 5 nm, or in the range of 3.5 nm to 4.5 nm.

[0071] Reference Figure 2A and Figure 2B In some embodiments, the dipole region 108 includes one or more of an interface layer 110 , a high-K dielectric layer 112 , and a dipole film 214 .

[0072] In one or more embodiments, the interfacial layer 110 is deposited on the top surface of the channel 106. In some embodiments, the interfacial layer 110 is deposited on the top surface of the channel 106 according to operation 22 of method 20. In some embodiments, the interfacial layer 110 comprises a dielectric material selected from one or more of silicon (Si), silicon oxide (SiOx), doped silicon, doped silicon oxide, or a spin-on dielectric.

[0073] The interface layer 110 can have any suitable thickness. In some embodiments, the interface layer 110 has a thickness in a range of 0.2 nm to 0.8 nm, including in a range of 0.3 nm to 0.7 nm, or in a range of 0.4 nm to 0.6 nm.

[0074] In one or more embodiments, a high-κ dielectric layer 112 is deposited on the top surface of the interface layer 110. In some embodiments, the high-κ dielectric layer 112 is deposited on the top surface of the interface layer 110 according to operation 24 of method 20. The high-κ dielectric layer 112 can be any suitable high-κ dielectric material known to one of ordinary skill in the art. In one or more embodiments, the high-κ dielectric layer 212 includes one or more of hafnium oxide (HfOx), zirconium oxide (ZrOx), or hafnium zirconium (HfZr).

[0075] The high-κ dielectric layer 112 can have any suitable thickness. In some embodiments, the high-κ dielectric layer 112 has a thickness in a range of 1 nm to 3 nm, including in a range of 1.1 nm to 2.9 nm, in a range of 1.2 nm to 2.8 nm, in a range of 1.3 nm to 2.7 nm, in a range of 1.4 nm to 2.6 nm, in a range of 1.5 nm to 2.5 nm, in a range of 1.6 nm to 2.4 nm, in a range of 1.7 nm to 2.3 nm, or in a range of 1.8 nm to 2.2 nm.

[0076] In one or more embodiments, the dipole film 114 is deposited on the top surface of the high-κ dielectric layer 112. In some embodiments, the dipole film 114 is deposited on the top surface of the high-κ dielectric layer 212 according to operation 26 of method 20. In one or more embodiments, the dipole film 114 includes one or more of a metal, a metal carbide, a metal nitride, or a metal oxide.

[0077] The dipole film 114 can have any suitable thickness. In some embodiments, the dipole film 114 has a thickness in a range of 0.3 nm to 1.5 nm, including in a range of 0.4 nm to 1.4 nm, in a range of 0.5 nm to 1.3 nm, in a range of 0.6 nm to 1.2 nm, in a range of 0.7 nm to 1.1 nm, or in a range of 0.8 nm to 1.0 nm.

[0078] In one or more embodiments, the channel 106 comprises an n-type material and the dipole film 114 comprises one or more of lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), magnesium (Mg), scandium (Sc), strontium (Sr), yttrium (Y), zirconium (Zr), or cesium (Cs). In some embodiments, the channel 106 comprises a p-type material and the dipole film 114 comprises one or more of aluminum (Al), titanium (Ti), gallium (Ga), germanium (Ge), selenium (Se), indium (In), tin (Sn), antimony (Sb), tellurium (Te), tantalum (Ta), tungsten (W), or molybdenum (Mo).

[0079] In one or more specific embodiments, when the dipole film 114 comprises one or more of a metal carbide, a metal nitride, or a metal oxide, the method 20 further comprises performing a free radical treatment (not shown) to remove carbides, nitrides, and oxides from each of the metal carbide, the metal nitride, or the metal oxide. The free radical treatment process may include any treatment known to one of ordinary skill in the art for removing carbides, nitrides, and oxides. In one or more embodiments, the free radical treatment comprises introducing a molecule comprising H * OH * , O * 、N2 * NH3 * or H2O * In some embodiments, the free radicals are generated by forming a plasma from a free radical gas. In some embodiments, the plasma is generated by a remote plasma source.

[0080] In some embodiments, the free radical treatment is performed once after the dipole film 114 deposition cycle has been completed to form the dipole film 114 having a predetermined thickness. In some embodiments, the free radical treatment is performed during the dipole film 114 deposition cycle. In some embodiments, the free radical treatment is performed multiple times during the dipole film 114 deposition cycle. In some embodiments, the free radical treatment is performed up to five times during the dipole film 114 deposition cycle. For example, a thin dipole film (e.g., a dipole film having a thickness of 0.3 nm) is deposited and then followed by the free radical treatment. In some embodiments, method 20 includes the following sequence: depositing a first thin dipole film (e.g., a dipole film having a thickness of 0.3 nm), performing a free radical treatment, depositing a second thin dipole film (e.g., a dipole film having a thickness of 0.3 nm), performing a free radical treatment, depositing a third thin dipole film (e.g., a dipole layer having a thickness of 0.3 nm), performing a free radical treatment, depositing a fourth thin dipole film (e.g., a dipole film having a thickness of 0.3 nm), performing a free radical treatment, and depositing a fifth thin dipole film (e.g., a dipole film having a thickness of 0.3 nm), and performing a free radical treatment.

[0081] Reference Figure 3A and 3B In one or more embodiments, the dipole film 114 is removed from the P-dipole stack and the N-dipole stack to expose the high-κ dielectric layer 112. In one or more embodiments, the dipole film 114 is removed from the P-dipole stack and the N-dipole stack to expose the high-κ dielectric layer 112, by operation 30 of method 20. In one or more specific embodiments, the semiconductor substrate is annealed at a temperature of less than or equal to 1050° C. (operation 28 of method 20) to drive atoms from the dipole film 114 into the high-κ dielectric layer 112, such that the high-κ dielectric layer 112 includes properties of the dipole film 114. In other words, after performing an etching process to remove the dipole film 114 and expose the high-κ dielectric layer 112 (operation 30 of method 20), the exposed high-κ dielectric layer 112 has a dipole property due to the annealing process (operation 28 of method 20).

[0082] Reference Figure 4A and 4B , the inter-gap filling material 120 is deposited on the exposed high-κ dielectric layer 112. In some embodiments, the inter-gap filling material 120 is deposited on the exposed high-κ dielectric layer 112 by operation 32 of method 20. In some embodiments, operation 32 of method 20 is the same process as operation 14 of method 10, which includes an atomic layer deposition (ALD) process, including exposing each of the P-dipole stack and the N-dipole stack to a metal precursor and a reactant to form the inter-gap filling material 120. In some embodiments, the metal precursor includes one or more of an organometallic metal precursor or a metal halide precursor.

[0083] In some embodiments, the ALD cycle includes exposing the surface of the exposed high-κ dielectric layer 112 to a pulse of a metal precursor to form a film comprising the inter-gap filler material 120. The metal precursor is then purged from the processing chamber or removed from a reaction zone adjacent to the substrate surface. The exposed high-κ dielectric layer 112 with the film thereon is exposed to a pulse of a reactant to form a metal-containing layer (e.g., a metal-containing layer comprising the inter-gap filler material 120) on the exposed high-κ dielectric layer 112. The reactant is then purged from the processing chamber or removed from the reaction zone adjacent to the substrate surface.

[0084] In one or more embodiments, the mid-gap fill material 120 is deposited at a temperature in the range of 300° C. to 500° C. and a pressure in the range of 1 Torr to 50 Torr, including all subranges and values ​​therebetween.

[0085] In some embodiments, the exposed high-κ dielectric layer 112 is exposed to a pulse of a metal precursor comprising one or more of magnesium (Mg), lanthanum (La), yttrium (Y), aluminum (Al), manganese (Mn), zirconium (Zr), tantalum (Ta), vanadium (V), zinc (Zn), titanium (Ti), niobium (Nb), tin (Sn), tungsten (W), molybdenum (Mo), ruthenium (Ru), or antimony (Sb), or alloys thereof, purged, exposed to a metal precursor comprising hydrogen (H2), 1-methyl-3,6-bis(trimethylsilyl)-1,4-cyclohexadiene (CHD), or 1,4-bis(trimethylsilyl)-1,4-dihydropyridine The inter-gap fill material 120 is formed by pulsing the reactants of one or more of the DHPs, and purging.

[0086] In some embodiments, the exposed high-κ dielectric layer 112 is exposed to a metal precursor comprising one or more of hafnium (Hf), zirconium (Zr), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), niobium (Nb), vanadium (V), cobalt (Co), manganese (Mn), nickel (Ni), tungsten (W), magnesium (Mg), palladium (Pd), ruthenium (Ru), or rhenium (Re) by pulsing, purging, exposing to a metal precursor comprising silane (SiH4), disilane (Si2H6), trisilane (Si3H8), or tetrasilane (Si4H 10 ) by pulsing one or more reactants and purging to form the intermediate energy gap filling material 120.

[0087] In some embodiments, the inter-gap fill material 120 is formed by exposing the exposed high-κ dielectric layer 112 to a pulse of a metal precursor comprising one or more of hafnium (Hf), magnesium (Mg), lanthanum (La), yttrium (Y), aluminum (Al), manganese (Mn), zirconium (Zr), tantalum (Ta), vanadium (V), zinc (Zn), titanium (Ti), niobium (Nb), tin (Sn), tungsten (W), molybdenum (Mo), ruthenium (Ru), or antimony (Sb), purging, exposing to a pulse of a reactant (e.g., a nitride reactant, a carbide reactant, a sulfide reactant, and / or a germanide reactant), and purging. In some embodiments, the nitride reactant comprises any suitable nitrogen-containing compound, including but not limited to one or more of ammonia (NH3), hydrazine (N2H4), nitrogen (N2) plasma, nitrogen (N2) radicals, a mixture of nitrogen (N2) plasma and hydrogen (H2) plasma, or a mixture of nitrogen (N2) radicals and hydrogen (H2) radicals. In some embodiments, the carbide reactant comprises any suitable carbon-containing compound, including but not limited to one or more of methane (CH4) or ethylene (C2H4). In some embodiments, the sulfide reactant comprises any suitable sulfur-containing compound, including but not limited to hydrogen sulfide (H2S). In some embodiments, the germanide reactant comprises any suitable germanium-containing compound, including but not limited to one or more of germanium tetrachloride (GeCl4) or germanium tetrahydride (GeH4).

[0088] Additional embodiments of the present invention relate to a processing tool 900 for forming an electronic device and the methods described herein, such as Figure 5 shown.

[0089] The cluster tool 900 includes at least one central transfer station 921, 931 with multiple sides. Robots 925, 935 are positioned within the central transfer station 921, 931 and are configured to move robot blades and wafers to each of the multiple sides.

[0090] The cluster tool 900 includes a plurality of processing chambers 902, 904, 906, 908, 910, 912, 914, 916, and 918, also referred to as processing stations, connected to a central transfer station. Each processing chamber provides a separate processing area isolated from adjacent processing stations. The processing chambers can be any suitable chamber, including but not limited to a pre-clean chamber, a buffer chamber, a transfer space, a wafer orienter / degas chamber, a cryogenic cooling chamber, a deposition chamber, an annealing chamber, an etch chamber, a thermal treatment (RTP) chamber, a plasma oxidation chamber, a plasma nitridation chamber, and an atomic layer deposition (ALD) chamber. The specific arrangement of the processing chambers and components may vary depending on the cluster tool and should not be considered to limit the scope of the present invention.

[0091] 4 , a factory interface 950 is coupled to the front of the cluster tool 900. The factory interface 950 includes a loading chamber 954 and an unloading chamber 956 on the front 951 of the factory interface 950. Although the loading chamber 954 is shown on the left and the unloading chamber 956 is shown on the right, one of ordinary skill will understand that this is representative of only one possible configuration.

[0092] The size and shape of the loading chamber 954 and the unloading chamber 956 may vary depending, for example, on the substrates being processed in the cluster tool 900. In the illustrated embodiment, the loading chamber 954 and the unloading chamber 956 are sized to hold a wafer cassette with a plurality of wafers positioned therein.

[0093] A robot 952 is within the factory interface 950 and can move between a loading chamber 954 and an unloading chamber 956. The robot 952 can transfer wafers from a cassette in the loading chamber 954 through the factory interface 950 to a load lock chamber 960. The robot 952 can also transfer wafers from a load lock chamber 962 through the factory interface 950 to a cassette in the unloading chamber 956. As one of ordinary skill will appreciate, the factory interface 950 can have more than one robot 952. For example, the factory interface 950 can have a first robot that transfers wafers between the loading chamber 954 and the load lock chamber 960, and a second robot that transfers wafers between the load lock 962 and the unloading chamber 956.

[0094] The illustrated cluster tool 900 has a first section 920 and a second section 930. The first section 920 is connected to the factory interface 950 via load lock chambers 960 and 962. The first section 920 includes a first transfer chamber 921 with at least one robot 925 positioned therein. The robot 925 is also referred to as a robotic wafer transfer mechanism. The first transfer chamber 921 is centrally located relative to the load lock chambers 960 and 962, the processing chambers 902, 904, 916, and 918, and the buffer chambers 922 and 924. In some embodiments, the robot 925 is a multi-arm robot capable of independently moving more than one wafer at a time. In one or more embodiments, the first transfer chamber 921 includes more than one robotic wafer transfer mechanism. The robots 925 in the first transfer chamber 921 are configured to move wafers between chambers surrounding the first transfer chamber 921. Individual wafers are carried on a wafer transfer blade located at the distal end of the first robotic mechanism.

[0095] After processing the wafers in the first section 920, the wafers may be transferred through a transfer chamber to the second section 930. For example, the chambers 922, 924 may be one-way or two-way transfer chambers. The transfer chambers 922, 924 may be used, for example, to cryogenically cool the wafers prior to processing in the second section 930 or to allow the wafers to cool or post-process before being moved back to the first section 920.

[0096] The system controller 990 communicates with the first robot 925, the second robot 935, the first plurality of processing chambers 902, 904, 916, 918, and the second plurality of processing chambers 906, 908, 910, 912, 914. The system controller 990 can be any suitable component capable of controlling the processing chambers and the robots. For example, the system controller 990 can be a computer including a central processing unit, memory, appropriate circuitry, and storage.

[0097] The processes may typically be stored in the memory of the system controller 990 as software routines that, when executed by the processor, cause the processing chamber to perform the processes of the present invention. The software routines may also be stored and / or executed by a second processor (not shown) that is remote from the hardware controlled by the processor. Some or all of the methods of the present invention may also be implemented in hardware. Thus, the processes may be implemented in software and implemented in hardware using a computer system as, for example, an application-specific integrated circuit or other type of hardware implementation, or as a combination of software and hardware. When executed by the processor, the software routines transform a general-purpose computer into a specialized computer (controller) that controls chamber operations so that the processes are performed.

[0098] In one or more embodiments, the cluster tool 900 includes a central transfer station 921, 931, which includes at least one robot 925, 935, which is configured to: deposit an interfacial layer on the top surface of a channel between a source and a drain located on a semiconductor substrate; deposit a high-κ dielectric layer on the interfacial layer; deposit a dipole film on the high-κ dielectric layer by exposing the semiconductor substrate to alternating cycles of a metal precursor and a reactant; anneal the semiconductor substrate; etch the film stack to remove the dipole film and expose the high-κ dielectric layer; and deposit an intermediate energy gap fill material on the exposed high-κ dielectric layer.

[0099] One or more embodiments of the present invention relate to a non-transitory computer-readable medium comprising instructions that, when executed by a controller of a processing chamber, cause the processing chamber to perform the operations of method 10 and / or method 20. In some embodiments, the non-transitory computer-readable medium comprises instructions that, when executed by a controller of the processing chamber, cause the processing chamber to: deposit an interfacial layer on a top surface of a channel between a source and a drain on a semiconductor substrate (operation 22); deposit a high-κ dielectric layer on the interfacial layer (operation 24); deposit a dipole film on the high-κ dielectric layer by exposing the semiconductor substrate to alternating cycles of a metal precursor and a reactant (operation 26); optionally anneal the semiconductor substrate (operation 28); etch the film stack to remove the dipole film and expose the high-κ dielectric layer (operation 30); and deposit an inter-gap fill material on the exposed high-κ dielectric layer (operation 32).

[0100] Spatially relative terms such as "below," "beneath," "lower," "above," "over," and the like may be used herein to simplify descriptions of the relationship of one element or feature relative to another element or feature as depicted in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the drawings were turned upside down, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the example term "below" can encompass both orientations of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein are to be interpreted accordingly.

[0101] The use of the terms "a," "an," "the," and similar designators in the context of describing the materials and methods discussed herein (especially in the context of the claims above) is intended to construct and cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. Numerical ranges recited herein are intended merely as a shorthand method of referring individually to each separate value falling within the range, and unless otherwise indicated herein, each separate value is incorporated into this specification as if it were individually recited herein. All methods described herein can be performed in any suitable order, unless otherwise indicated herein or clearly contradicted by context. The use of any and all examples or exemplary language (e.g., "such as") provided herein is intended merely to better illustrate the materials and methods and does not impose a limitation on scope unless otherwise stated. No language in this specification should be construed to indicate that any non-claimed element is essential to the practice of the disclosed materials and methods.

[0102] References throughout this specification to "one embodiment," "some embodiments," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. Thus, the appearance of phrases such as "in one or more embodiments," "in some embodiments," "in one embodiment," or "in an embodiment" in various places throughout this specification are not necessarily referring to the same embodiment of the invention. In one or more embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner.

[0103] Although the present invention has been described herein with reference to specific embodiments, it will be understood that these embodiments are merely illustrative of the principles and applications of the present invention. Various modifications and variations of the methods and apparatus of the present invention may be made without departing from the spirit and scope of the present invention, as will be apparent to those skilled in the art. Therefore, it is intended that the present invention include modifications and variations that come within the scope of the appended claims and their equivalents.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: forming a P-dipole stack and an N-dipole stack on a semiconductor substrate, each of the P-dipole stack and the N-dipole stack being formed on a top surface of a channel, the channel being located between a source and a drain on the semiconductor substrate; and A fill layer comprising a mid-gap fill material is deposited on each of the P-dipole stack and the N-dipole stack. 2 . The method of claim 1 , wherein depositing the fill layer comprises exposing each of the P-dipole stack and the N-dipole stack to a metal precursor and a reactant to form the mid-gap fill material.

3. The method of claim 2, wherein the metal precursor comprises one or more of a metal halide precursor or an organometallic precursor.

4. The method of claim 1 , wherein the mid-gap filling material comprises one or more of magnesium (Mg), lanthanum (La), yttrium (Y), aluminum (Al), manganese (Mn), zirconium (Zr), tantalum (Ta), vanadium (V), zinc (Zn), titanium (Ti), niobium (Nb), tin (Sn), tungsten (W), molybdenum (Mo), ruthenium (Ru), or antimony (Sb), or alloys thereof.

5. The method of claim 4, wherein the reactant comprises hydrogen (H2), 1-methyl-3,6-bis(trimethylsilyl)-1,4-cyclohexadiene (CHD), or 1,4-bis(trimethylsilyl)-1,4-dihydropyridine (DHP) one or more.

6. The method of claim 1 , wherein the mid-gap fill material comprises a silicide of one or more of hafnium (Hf), zirconium (Zr), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), niobium (Nb), vanadium (V), cobalt (Co), manganese (Mn), nickel (Ni), tungsten (W), magnesium (Mg), palladium (Pd), ruthenium (Ru), or rhenium (Re).

7. The method of claim 6, wherein the reactant comprises silane (SiH4), disilane (Si2H6), trisilane (Si3H8), or tetrasilane (Si4H 10 ) 8. The method of claim 1 , wherein the mid-gap filler material comprises a nitride, carbide, sulfide, or germanide of one or more of hafnium (Hf), magnesium (Mg), lanthanum (La), yttrium (Y), aluminum (Al), manganese (Mn), zirconium (Zr), tantalum (Ta), vanadium (V), zinc (Zn), titanium (Ti), niobium (Nb), tin (Sn), tungsten (W), molybdenum (Mo), ruthenium (Ru), or antimony (Sb).

9. The method of claim 1, wherein each of the P-dipole stack and the N-dipole stack comprises one or more of an interface layer; a high-K dielectric layer on the interface layer; and a dipole film on the high-K dielectric layer.

10. The method of claim 9, wherein the interface layer comprises a dielectric material.

11. The method of claim 10, wherein the dielectric material is selected from silicon (Si), silicon oxide (SiO x ), one or more of doped silicon, doped silicon oxide, or spin-on dielectric.

12. The method of claim 1, wherein the channel comprises n-type material.

13. The method of claim 1, wherein the channel comprises p-type material.

14. The method of claim 9, wherein the dipole film comprises one or more of a metal, a metal carbide, a metal nitride, or a metal oxide.

15. The method of claim 9, wherein the high-K dielectric layer comprises one or more of hafnium oxide (HfOx), zirconium oxide (ZrOx), or hafnium zirconium (HfZr).

16. A method of manufacturing a semiconductor device, the method comprising: A P-dipole stack is formed on the substrate by the following steps: depositing an interfacial layer on a top surface of a channel, the channel being located between a source electrode and a drain electrode on the substrate; depositing a high-K dielectric layer on the interface layer; and depositing a dipole film on the high-K dielectric layer; An N-dipole stack is formed on the substrate by the following steps: depositing an interfacial layer on a top surface of a channel, the channel being located between a source electrode and a drain electrode on the substrate; depositing a high-K dielectric layer on the interface layer; and depositing a dipole film on the high-K dielectric layer; annealing the P-dipole stack and the N-dipole stack to drive metal atoms from the dipole film; etching the P-dipole stack and the N-dipole stack to expose the high-K dielectric layer; and A mid-gap material is deposited on the exposed high-K dielectric layer.

17. The method of claim 16, wherein depositing the mid-gap material comprises exposing each of the P-dipole stack and the N-dipole stack to one or more of a metal halide precursor or an organometallic precursor and a reactant.

18. The method of claim 16, wherein the mid-gap material comprises one or more of magnesium (Mg), lanthanum (La), yttrium (Y), aluminum (Al), manganese (Mn), zirconium (Zr), tantalum (Ta), vanadium (V), zinc (Zn), titanium (Ti), niobium (Nb), tin (Sn), tungsten (W), molybdenum (Mo), ruthenium (Ru), or antimony (Sb), or alloys thereof.

19. The method of claim 16, wherein the mid-gap material comprises a silicide of one or more of hafnium (Hf), zirconium (Zr), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), niobium (Nb), vanadium (V), cobalt (Co), manganese (Mn), nickel (Ni), tungsten (W), magnesium (Mg), palladium (Pd), ruthenium (Ru), or rhenium (Re).

20. The method of claim 16, wherein the mid-gap material comprises a nitride, carbide, sulfide, or germanide of one or more of hafnium (Hf), magnesium (Mg), lanthanum (La), yttrium (Y), aluminum (Al), manganese (Mn), zirconium (Zr), tantalum (Ta), vanadium (V), zinc (Zn), titanium (Ti), niobium (Nb), tin (Sn), tungsten (W), molybdenum (Mo), ruthenium (Ru), or antimony (Sb).

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