Semiconductor device

Abstract

The invention provides a semiconductor device, and relates to the technical field of semiconductors, the semiconductor device comprises a silicon substrate, a cavity is formed in the silicon substrate, a structural layer is laminated on the silicon substrate and the cavity, the structural layer forms a thin film area corresponding to the cavity, and the structural layer forms a routing area corresponding to the silicon substrate outside the thin film area; the wire bonding area comprises a first wire bonding area and a second wire bonding area, in the overlook direction, the first wire bonding area is formed in the mode that the thin film area shrinks inwards towards the center of the semiconductor device, so that the first wire bonding area surrounds part of the thin film area, and the second wire bonding area is formed in the mode that the thin film area shrinks inwards towards the center of the semiconductor device. The second wire bonding area surrounds the thin film area and the first wire bonding area. By optimizing the cutting of the vibration unit in the thin film area, the distribution of the original silicon-based area is changed, so that the overall size of the device is reduced, and the development requirement of miniaturization is met.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device. Background Art

[0002] The general structure of the MEMS (micro-electromechanical system) chip is based on the deposition of various functional layer materials on the silicon wafer, and finally the MEMS chip film is formed by back etching (DRIE). This process is the deep silicon etching process, which retains the various functional layers originally deposited on the silicon and etches away the silicon substrate underneath. Generally speaking, the etched silicon is above the formed thin film structure, but a part of the silicon base layer will not be etched, because this part also bears the silicon substrate in the package for gluing, and part of the silicon base also needs to bear the functions of bonding points, metal wire connections, etc. These functions cannot be completed in the thin film area. For example, the bonding points need to withstand the power welding process during the packaging process. If designed in the thin film structure area, it will break at the touch and it is impossible to achieve. Take the common MEMS microphone cantilever beam chip as an example, such as Figure 1 As shown, the silicon below the middle thin film area 11 is etched, but the silicon bases 10 on both sides must be retained, and the metal bonding points above must be above the silicon base 10.

[0003] A significant design trend in MEMS chips is miniaturization. For example, MEMS microphones previously featured a typical package size of approximately 37mm long, 29mm wide, and 1.1mm high. In the current industrial landscape of highly integrated intelligent devices, the market has shifted to a 27mm long and 18mm wide package to accommodate highly integrated electronic devices such as miniature glasses and headphones. In addition to MEMS microphone chips, other MEMS chip industrial products are also showing this miniaturization trend. Therefore, to further reduce package size, the primary goal is to reduce the space available for the package's internal structure. As the most critical design component determining package size, MEMS chips are experiencing a significant trend toward miniaturization. However, some basic functional designs inevitably occupy a certain amount of space, necessitating further solutions to the inherent limitations of miniaturized MEMS chips. Summary of the Invention

[0004] An object of the present invention is to provide a semiconductor device that can further reduce the chip size.

[0005] In one aspect of the present invention, a semiconductor device is provided, comprising a silicon substrate, wherein a cavity is formed on the silicon substrate, a structural layer is stacked on the silicon substrate and the cavity, the structural layer forms a thin film region corresponding to the cavity, and the structural layer forms a bonding region on the silicon substrate outside the thin film region; The bonding area includes a first bonding area and a second bonding area. In a top view, the first bonding area is formed by the thin film area being retracted toward the center of the semiconductor device, so that the first bonding area is surrounded by part of the thin film area, and the second bonding area is surrounded by the thin film area and the first bonding area.

[0006] Optionally, in the top-view direction, the first bonding area is located at a portion of the periphery of the thin film area, the first bonding area and the thin film area together form a preset pattern, and the second bonding area surrounds the preset pattern.

[0007] Optionally, the projection of the semiconductor device in the top-view direction is a square, there is at least one first bonding area, and at least one first bonding area is arranged at the corner of the thin film area, so that the first bonding area and the thin film area together form a square figure, and the second bonding area forms a ring square figure surrounding the thin film area and the first bonding area.

[0008] Optionally, the thin film area is divided by slits, and the slits are arranged along diagonal corners of the square figure and extend to a common edge line of the first wiring area and the thin film area.

[0009] Optionally, the first bonding area is used to set bonding point locations.

[0010] Optionally, the preset graphic includes any one of a circle, an arbitrary polygon or a special-shaped graphic.

[0011] Optionally, the shape of the first bonding area includes any one of a circle, an arbitrary polygon or a special-shaped figure.

[0012] The semiconductor device provided by the present invention includes: a silicon substrate having a cavity formed therein; a structural layer stacked on the silicon substrate and the cavity; the structural layer forming a thin film region corresponding to the cavity; and the silicon substrate outside the thin film region forming a bonding region corresponding to the structural layer; the bonding region including a first bonding region and a second bonding region. In a top view, the first bonding region is formed by the thin film region being inwardly contracted toward the center of the semiconductor device, so that the first bonding region surrounds a portion of the thin film region, and the second bonding region surrounds the thin film region and the first bonding region. By optimizing the cutting of the vibration unit in the thin film region, the distribution of the original silicon base region is changed, thereby reducing the overall size of the device to meet the development needs of miniaturization. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solution of the present invention, the following is a brief introduction to the drawings required for use in the present invention. It should be understood that the following drawings only show certain examples of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0014] Figure 1 This is a schematic diagram of the conventional MEMS microphone cantilever beam chip structure; Figure 2 This is one of the top views of a conventional MEMS microphone cantilever chip; Figure 3 This is one of the schematic diagrams of the semiconductor device structure provided by the present invention; Figure 4 It is a thin film region optimization diagram of the semiconductor device provided by the present invention; Figure 5 This is the second schematic diagram of the semiconductor device structure provided by the present invention; Figure 6 It is a schematic diagram of the local structure of the semiconductor device provided by the present invention; Figure 7 This is one of the stress cloud diagrams of the cantilever beam chip of a conventional MEMS microphone; Figure 8 This is the second stress cloud diagram of the conventional MEMS microphone cantilever beam chip; Figure 9 This is a stress cloud map of a semiconductor device provided by the present invention; Figure 10 This is the second top view of a conventional MEMS microphone cantilever beam chip.

[0015] Icon: 10-silicon base; 11-thin film area; 12-wire bonding plate; 13-first slit; 100-thin film area; 101-first wire bonding area; 102-second wire bonding area; 103-soldering point; 104-second slit; L-electrode dividing line. DETAILED DESCRIPTION

[0016] The technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the present invention.

[0017] In the description of the present invention, it should be noted that the terms "inner" and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, or the orientations or positional relationships in which the inventive product is typically placed when in use. These terms are intended solely to facilitate the description of the present invention and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present invention. Furthermore, the terms "first" and "second," etc., are used solely for distinction and should not be construed as indicating or implying relative importance.

[0018] It should also be noted that, unless otherwise expressly specified or limited, the terms "disposed" and "connected" should be understood broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to direct connections, indirect connections through an intermediate medium, or internal connections between two components. Those skilled in the art will understand the specific meanings of these terms in the present invention based on the specific circumstances.

[0019] Figure 2 A top view of a conventional MEMS microphone chip, combined with Figure 1 As shown, Figure 2 Below the square area in the middle dark blue part is the deep silicon etching area, which is the thin film area 11, and is the actual sensing function implementation area of ​​the MEMS sensing unit. The entire MEMS range area, except for the dark blue thin film area 11, is the orange area above the silicon base 10. The silicon below this area has been retained. Obviously, there is at least our pink wire bonding board 12 above this area. The outline of the cross in the middle is the first slit 13, which divides the middle film into four triangular cantilever beams. In this way, if the size of the MEMS chip needs to be miniaturized, it is necessary to consider reducing the thin film area 11 and the area above the silicon base 10.

[0020] Obviously, if the outer dimensions of the MEMS chip are determined, for example Figure 2 Taking the MEMS microphone chip as an example, the side length of the square of the MEMS chip with the smallest package size is 1mm, and the smallest can be 0.7mm, etc. Also note that the outer edge contour of the MEMS chip must be square. This is because after the wafer leaves the factory, it needs to be laser-cleaved, basically slicing the entire wafer horizontally and vertically like cutting a cake. For an 8-inch wafer, if the side length of the MEMS chip is 1mm, then the number of MEMS chips after slicing will be tens of thousands.

[0021] For a square chip, if the back cavity size of the thin film area remains consistent, the square back cavity profile will make the area occupied by the thin film area 11 the largest. For the cantilever beam design, the larger the area of ​​the thin film area 11, the lower the frequency it will eventually design. Because after the thin film area 11 is miniaturized, for the microphone chip of the cantilever beam, when the information in the thickness direction remains consistent, its frequency will increase. In other words, as the area of ​​the thin film area 11 becomes smaller and smaller, the frequency of the microphone chip will be forced to soar. Obviously, this does not conform to the design ideas of commonly used MEMS microphones, because very high frequencies will reduce the sensitivity of the microphone, and ultimately the signal-to-noise ratio will also be greatly reduced. Therefore, the correct idea is to reduce the area of ​​the silicon base 10 area. When the overall area of ​​the microphone chip becomes smaller, the smaller area of ​​the silicon base 10 area will not cause reliability problems at the wafer level.

[0022] However, some areas above the silicon substrate 10 cannot be reduced in size, such as the wire bonding pad 12. The automatic wire bonding machines currently used in mass-produced packaging require that the characteristic size of the spherical solder joints be at least 60μm. Furthermore, the silicon substrate 10 must be located below this area to withstand the downward pressure of the solder joints. Beyond these solder joints, the yellow area at the edge of the top view above represents the scribe line area, occupying at least 35μm on one side. The solder joints should not be too close to the edge of the film, otherwise the downward pressure of the wire bonding pads could damage the film structure. They should be at least 20μm away from the solder joints. The remaining metal connection traces can be arranged more flexibly in the area above the silicon substrate.

[0023] From the above analysis, it can be seen that the silicon base 10 is limited by the current design. The length of one side is at least 120um, and the length of both sides is 0.24mm. When designing a MEMS chip with a length of 0.8mm, the maximum characteristic size of the thin film area 11 is only 0.56mm. It is difficult to design a MEMS cantilever microphone chip with performance that meets market requirements with this space.

[0024] In view of this, in order to solve the above technical problems, the semiconductor device provided by the present invention can further reduce the size of the MEMS silicon substrate based on the shape of the MEMS chip back cavity. Figure 3 As shown, the semiconductor device provided by the present invention includes: a silicon substrate, a cavity formed on the silicon substrate, a structural layer stacked on the silicon substrate and the cavity, the structural layer forming a thin film area 100 corresponding to the cavity, and the structural layer forming a bonding area on the silicon substrate outside the thin film area 100.

[0025] Among them, the wiring area includes a first wiring area 101 and a second wiring area 102. In the top view direction, the first wiring area 101 is formed by shrinking the thin film area 100 toward the center of the semiconductor device, so that the first wiring area 101 surrounds part of the thin film area 100, and the second wiring area 102 surrounds the thin film area 100 and the first wiring area 101.

[0026] The semiconductor device of the present invention forms a thin film region 100, a first bonding region 101, and a second bonding region 102 when viewed from above. The thin film region 100 corresponds to the cavity, and the first and second bonding regions 101 and 102 jointly correspond to the silicon substrate. Thin film region 100 forms an indented structure to reduce its area. The indented area serves as the first bonding region 101, for arranging bonding pads 103. The second bonding region 102 surrounds the thin film region 100 and the first bonding region 101. The positioning of the first bonding region 101 optimizes the cutting of the thin film region vibration unit, changes the distribution of the original silicon substrate area, and reduces the overall size of the device.

[0027] by Figure 3 Taking the MEMS chip as an example, in the top view, the first bonding area 101 is located at a portion of the periphery of the thin film area 100, the first bonding area 101 and the thin film area 100 together form a preset pattern, and the second bonding area 102 surrounds the preset pattern.

[0028] Figure 3 The projection of the semiconductor device in the top view is a square, the first bonding area 101 is a small square, and there is at least one first bonding area 101. For example, the present invention has four first bonding areas 101, and at least one first bonding area 101 is arranged at the corner of the thin film area 100, so that the preset pattern formed by the first bonding area 101 and the thin film area 100 is a square pattern, and the second bonding area 102 forms a ring square pattern surrounding the thin film area 100 and the first bonding area 101.

[0029] The first bonding area 101, i.e. the bonding soldering point 103, is moved to the corner of the square outline and is divided by special electrodes and a second slit 104, so that the size of the MEMS chip can be further reduced, while the performance level of the MEMS microphone chip can still be maintained.

[0030] like Figure 4 As shown, the present invention is based on a triangular cantilever beam film design above the original square back cavity (as previously explained, under a certain back cavity size, a square back cavity has the highest chip utilization rate), or a cantilever beam film structure similar to the triangular design. The main feature is that the suspension wires supporting the cantilever beam are fixed at the edge of the square back cavity. The present invention reserves the four corners of the square as part of the silicon base below. The typical retention method is as follows: Figure 4 The left picture shows a conventional square cavity release, where the dark blue is the cavity outline. Figure 4 The right picture shows an improved method of the present invention, in which the silicon bases similar to four small squares in the four corners are retained.

[0031] Figure 4 The four corners of the back cavity shown on the right are compared with the original Figure 4 As for the back cavity in the left image, this feature clearly has four additional small square mesas, namely the first wiring area 101. Moreover, these four square first wiring areas 101 can also be triangles, quadrilaterals, other polygons, circles, special shapes, and other graphic designs. The squares mentioned above are just one example.

[0032] Similarly, the preset pattern formed by the thin film area 100 and the first bonding area 101 includes any one of a circle, an arbitrary polygon or an irregular shape, which is set according to actual needs. Its purpose is to cut out a part of the original thin film area 100 as the first bonding area 101 to reduce the overall size of the device.

[0033] Figure 6 The red circle is the two starting points of the back cavity busbar in the present invention. The first wiring area 101 is located to the lower right of the two points. The line connecting the two points is the arc contour line of the film area 100 of the present invention. It can be seen that the first wiring area 101 can be Figure 3 In addition to the small square in Figure 6 The other three first bonding areas 101 may form similar irregular patterns, or may not be provided, depending on the designer's needs.

[0034] The back cavity profile of the MEMS chip of the present invention has been significantly changed compared to the original conventional square design. This change increases the area of ​​the silicon-based mesa (first bonding area 101) at the corner of the square pattern during the miniaturization of the MEMS chip.

[0035] In the present invention, the area of ​​the first bonding area 101 is increased, wherein the increased first bonding area 101 is the area of ​​the reduced portion of the thin film area 100. For the cantilever beam structure released by the square back cavity in the present invention, the back cavity design of the present invention is indeed the optimal solution.

[0036] For example, when a triangular cantilever beam is used as a microphone sensor chip, the outline of the back cavity is a square. In this way, we can obtain the sound pressure and mechanical deformation characteristics of the working cavity through simulation calculation: Under 1kHz / 1Pa sound pressure, the Mises stress cloud diagram of the triangular cantilever beam is obtained: like Figure 7As shown, it should be noted that the stress concentration area is in the middle deep red-orange area, and the color becomes bluer as it gets closer to the free end. In order to ensure the sensitivity of the signal output, the effective electrode should cover the area with greater mises stress as much as possible. Therefore, there is an electrode dividing line L parallel to the boundary. The electrode area below the electrode dividing line L is the effective electrode area, that is, the thin film area 11.

[0037] Figure 7 Some geometric information is annotated in the figure. In the simulation model, especially when MEMS is stacked in the longitudinal direction using a commonly used material in current processes, such as aluminum nitride piezoelectric film, the side length of the back cavity is 700μm. This size is very extreme compared to the MEMS chip package size, which must be controlled at 900μm. As mentioned earlier, this 700μm is only the film area 11, and the film requires a 120μm area on a single side as the silicon substrate 10. At this time, the MEMS chip size reaches 940μm. However, it is obvious that the frequency of the MEMS cantilever beam is already very high at this time, exceeding 16kHz, which exceeds the requirements of the microphone system (typical microphone systems pursue flatness of 1kHz to 10kHz signals).

[0038] Note that the stress levels at the left and right triangle corners of the mises cloud are very low. Suppose we mark these two sides, such as Figure 8 As shown, aside from the free end, the stress at the red circles on either side of the triangle is virtually nonexistent. Note that the two right-angled sides of the triangle in the red circles were calculated as 60 μm. As the cloud chart shows, extending to 100 μm has minimal impact on overall system performance.

[0039] Therefore, at this time, if the two sides of the cantilever beam are cut perpendicular to the fixed edge of the cantilever beam, a triangular cantilever beam will be obtained. Obviously, its characteristic frequency will drop slightly, and the stress concentration in the piezoelectric layer area covered by the effective electrode will be more obvious. At this time, the signal output of the MEMS microphone chip will be improved.

[0040] The simulation calculation mises stress cloud diagram after cutting is as follows Figure 9 As shown, the electrode division method of the effective electrode can be fine-tuned according to the stress cloud map.

[0041] However, the reduced thin film area 100 may not be etched away by deep silicon etching, thereby creating four additional first bonding areas 101. The first bonding areas 101 are four squares of no less than 60um. At this time, the bonding pads (pins) originally deployed in the area above the silicon base can be deployed in the first bonding areas 101 at the four corners (generally, there are at least two bonding pads, positive and negative, and sometimes there are one or even two more). In this way, the original size range of the non-thin film area 100 is at least 120um. Now, due to the optimization of the pad position, only 60um is needed to meet the MEMS design. In the end, the external size of this MEMS chip is only 820um, which meets the packaging requirements. At the same time, the performance level of the MEMS microphone chip has not only not declined, but has improved.

[0042] The original MEMS chip design, such as Figure 10 As shown, the blue area is the thin film area 11, which is divided into four triangles by two vertical first slits 13 of a certain width. The effective electrode area of ​​the four triangular cantilever beams is the small square inside the blue square in the figure. Obviously, the blue area is the back cavity release design outline. According to the aforementioned design, it is a square with a side length of 700um. The 60um wire bonding pad is placed above the silicon substrate 10. The orange area above the silicon substrate 10 has a single side width of 120um. The marking boxes in the four corners are corresponding marks of the four corners of the MEMS and can be omitted. Therefore, the original design size of the MEMS chip is at least 940um in side length.

[0043] The optimized MEMS back cavity design of the present invention is applied, such as Figure 5 As shown, the internal triangular thin film area 100 has been optimized, and the four bonding pads originally above the silicon substrate have been moved to the four first bonding areas 101 of the square. This means that the silicon substrate below the first bonding areas 101 is retained, thereby reducing the side lengths of the original four borders from 120μm to 60μm. Obviously, the size of the entire MEMS chip has been reduced to 820μm due to the back cavity release optimization. Compared with the original 940μm, the size is significantly reduced, meeting the requirements for further reducing the size of MEMS chips and providing the possibility of further miniaturization of MEMS system packaging size.

[0044] At the same time, it is noted that the structure of the cantilever beam is no longer a triangle, and the characteristics of the busbar of the cantilever beam with a side length of 100 in the cutting film area are different from the original Figure 10The design is no longer two mutually perpendicular first slits 13 with a certain width. Instead, two mutually perpendicular straight second slits 104 are formed in the middle area. At the edge of the square, the second slits 104 are formed along the silicon base edges of the four first bonding areas 101, running through the front and back. In other words, the thin film area 100 is divided by the second slits 104. The second slits 104 are set along the diagonals of the square figure and extend to the common edge line of the first bonding area 101 and the thin film area 100 ( Figure 5 The red line in the middle is the second slit 104), so that the new cantilever beam formed will not interfere with the silicon base below during working vibration. The outline of the new cantilever beam is also shown in Figure 5 It is indicated that the cutting line of the priority electrode can also be clearly seen, and the MISE stress cloud diagram of the new cantilever beam under the working state is as follows Figure 9 Obviously, under the back cavity profile of the present invention, the output signal capability of the system is slightly improved, but the size of the MEMS system is further reduced.

[0045] It is worth noting that the above description is to stack four small squares at the four corners of the square with the back cavity outline as the first bonding area 101. The first bonding area 101 is not necessarily a square and can be of various shapes, which will not be described here. The first bonding area 101 can be used to place bonding pads, where the two sides of the first bonding area 101 near the second bonding area 102 are perpendicular to each other, but the sides of the first bonding area 101 near the film area 100 are relatively random, for example Figure 6 The line connecting the two points in the two red circles is a broken line, which can achieve the effect of the present invention. However, when forming a new cantilever beam, the edge contour of the first bonding area 101 and the curve of the second slit 104 that divides the thin film area 100 to form the cantilever beam should be similar. This ensures that the cantilever beam does not interfere with the silicon base below the first bonding area 101 during working vibration, thereby affecting the system operation.

[0046] In summary, when the present invention adopts a square back cavity release profile, the square back cavity profile is optimized, thereby reducing the area of ​​the original silicon base region and reducing the size of the entire MEMS chip.

[0047] The foregoing description is merely illustrative of the present invention and is not intended to limit the scope of protection of the present invention. Those skilled in the art will readily appreciate that the present invention is susceptible to various modifications and variations. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A silicon substrate, wherein a cavity is formed on the silicon substrate, a structural layer is stacked on the silicon substrate and the cavity, the structural layer forms a thin film area corresponding to the cavity, and the structural layer forms a bonding area on the silicon substrate outside the thin film area; The bonding area includes a first bonding area and a second bonding area. In a top view, the first bonding area is formed by the thin film area being retracted toward the center of the semiconductor device, so that the first bonding area is surrounded by part of the thin film area, and the second bonding area is surrounded by the thin film area and the first bonding area.

2. The semiconductor device according to claim 1, wherein In the top view direction, the first bonding area is located at a portion of the periphery of the thin film area. The first bonding area and the thin film area together form a preset pattern, and the second bonding area surrounds the preset pattern.

3. The semiconductor device according to claim 2, wherein The projection of the semiconductor device in the top view direction is a square, there is at least one first bonding area, and at least one first bonding area is arranged at the corner of the thin film area, so that the first bonding area and the thin film area together form a square figure, and the second bonding area forms a ring square figure surrounding the thin film area and the first bonding area.

4. The semiconductor device according to claim 3, wherein The thin film area is divided by slits, and the slits are arranged along the diagonals of the square figure and extend to the common edge line of the first wiring area and the thin film area.

5. The semiconductor device according to any one of claims 1 to 4, wherein: The first bonding area is used to set bonding point locations.

6. The semiconductor device according to any one of claims 2 to 4, characterized in that The preset graphics include any one of a circle, an arbitrary polygon or a special-shaped graphics.

7. The semiconductor device according to any one of claims 1 to 4, characterized in that The shape of the first bonding area includes any one of a circle, an arbitrary polygon or a special-shaped figure.

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