Logic separation type multi-servo-motor electric control system

Abstract

The invention provides a logic separation type multi-servo-motor electric control system. According to the logic separation type multi-servo-motor electric control system, collaborative operation of high-precision control and data transmission is achieved through three independent loops. The system comprises a PC end computer, a control unit, an industrial bus, a servo driving unit, a logic unit and a controlled object. Wherein the first loop is formed by a PC end computer through a control unit, an industrial bus and a servo driving unit, and is responsible for transmitting a real-time control signal and position updating data; the second loop is returned to the PC end computer by the servo driving unit through the logic unit and is used for feeding back execution state data of the servo driver; and in the third loop, the controlled object is transmitted to the PC end computer through the logic unit, and real-time position signals and mechanical state data of the controlled object are transmitted. Through the logic layering and loop separation design, the control real-time performance, the data transmission reliability and the system expansibility of the system are remarkably improved, meanwhile, the signal interference during multi-task processing is reduced, and the system is suitable for a high-precision industrial automation scene.

Description

Technical Field

[0001] The present invention relates to the technical field of motor electronic control, and in particular to a logic-separated multi-servo motor electronic control system. Background Art

[0002] Existing multi-servo motor control systems typically use a single bus (such as EtherCAT, Profinet) or an integrated control architecture to transmit a variety of signals such as control instructions, status feedback, and position data in a mixed manner. During high-load operation, priority conflicts between different types of signals (such as real-time control instructions and periodic status data) can easily lead to communication delays or packet loss. Especially in multi-axis linkage scenarios, slight delays may cause mechanical vibration or positioning errors. For example, in a five-axis machining center, if the servo feedback signal of a certain axis is delayed due to bus congestion, it may cause chain control errors and reduce machining accuracy. In addition, traditional systems lack fine-grained control of signal transmission timing, making it difficult to meet the millisecond-level response requirements of the Industry 4.0 environment. Existing systems typically use a single-route communication link. Once the bus or control unit fails, such as a communication interruption caused by electromagnetic interference, the entire control system may be paralyzed. Although some high-end systems use redundant bus designs, they are expensive and mainly target key equipment, making it difficult to cover all servo motors and sensors. For example, on an automotive welding production line, if a servo motor's current loop experiences an anomaly, traditional systems can only shut down the machine to prevent damage. They are unable to quickly isolate the fault and switch to an alternate control path, resulting in extended production downtime. Furthermore, the program can also experience numerous dead loops and thread contention issues. Summary of the Invention

[0003] In order to solve the problem that the multi-servo motor control system in the prior art adopts a single communication architecture, there are a large number of blocking dead loops and thread competition problems in the program, which makes it difficult to meet the control requirements of high-precision and high-reliability industrial scenarios, this application provides a logically separated multi-servo motor electronic control system, including: PC

[0004] The PC-end computer comprises a control unit, an industrial bus, a servo drive unit, a logic unit and a controlled object, wherein the PC-end computer is connected to the control unit, the industrial bus and the servo drive unit in sequence to form a control instruction downlink channel, forming a first loop, and the first loop is used to transmit real-time control signals and position update data; the servo drive unit is electrically connected to the logic unit and the PC-end computer in sequence to form a drive status upload channel, forming a second loop, and the second loop is used to transmit execution status data of the servo drive; the controlled object is electrically connected to the logic unit and the PC-end computer in sequence to form a controlled object status channel, forming a third loop, and the third loop is used to transmit the real-time position signal and mechanical status data of the controlled object.

[0005] In one embodiment, the industrial bus in the first loop is configured as a unidirectional data flow transmission channel, allowing data to be transmitted only from the control unit to the servo drive unit.

[0006] In one embodiment, the interrupt response mechanism of the logic unit is specifically as follows: when it is detected that the status signal of the servo drive unit or the controlled object reaches a preset threshold, a priority interrupt signal is immediately triggered and uploaded to the PC computer. The interrupt triggering mode includes rising edge triggering and high level continuous triggering mode.

[0007] In one embodiment, the logic unit includes a signal type separation module, and the mechanical state data transmitted in the controlled object state channel is further divided into an analog signal transmission channel and a digital signal transmission channel, wherein the analog signal adopts a differential signal transmission method, and the digital signal adopts an optocoupler isolation transmission method.

[0008] In one embodiment, a data synchronization verification module is provided between the control unit and the servo drive unit. The module generates a timestamp mark after each position update data transmission, and feeds back the actual action timestamp to the PC computer through the controlled object status channel of the third loop, thereby realizing closed-loop time synchronization of the control instructions and the execution action.

[0009] In one embodiment, the servo drive unit includes a status cache queue. When it is detected that the industrial bus bandwidth occupancy rate exceeds 70%, non-emergency status data is automatically temporarily stored in the status cache queue and uploaded to the PC computer in batches through the second loop.

[0010] In one embodiment, the logic unit uses an FPGA chip to implement signal acquisition and protocol conversion functions, and its hardware circuit includes at least two sets of independent physical interfaces, which respectively establish point-to-point connections with the servo drive unit and the controlled object.

[0011] Furthermore, the physical isolation of the system is achieved in the following manner: the control unit and the logic unit are respectively deployed on independent circuit boards, and there is no direct electrical connection between the two; the industrial bus uses a shielded twisted pair cable with a grounding impedance of less than 1Ω; and the signal transmission paths of the second loop and the third loop use carrier communications in different frequency bands.

[0012] In one embodiment, the PC computer is provided with a dynamic bandwidth allocation module, which monitors the bandwidth occupancy of the three data channels in real time. When the demand for real-time control signal transmission of the first loop surges, the interrupt response frequency of the second loop and the third loop is automatically reduced, and the priority is guaranteed to ensure the integrity of the control instruction transmission.

[0013] In one embodiment, the logic unit includes a signal preprocessing module that performs real-time filtering and analog-to-digital conversion on the mechanical state data of the controlled object, specifically including: setting a low-pass filter in the analog signal transmission channel with a cutoff frequency of 3 times the motion frequency of the controlled object; configuring a hysteresis comparator in the digital signal transmission channel to eliminate signal jitter interference; and uploading the processed data to a PC computer through the controlled object state channel of the third loop.

[0014] Furthermore, redundant communication channels are provided in both the second and third loops. The triggering conditions of the redundant communication channels include: when the signal packet loss rate of the main channel exceeds 5%, it automatically switches to the redundant channel; when the electromagnetic interference intensity is detected to exceed 50dBμV / m, the redundant channel is enabled in parallel to transmit encrypted verification data; the redundant channel adopts a different communication protocol from the main channel, and the physical path spacing is greater than 20cm.

[0015] Furthermore, the FPGA chip has an embedded dynamic protocol configuration engine, which allows the following operations to be performed remotely via a PC: automatically matching the communication protocol type according to the model of the servo drive unit; dynamically adjusting the digital signal sampling frequency during operation, with an adjustment range of 1kHz to 10kHz; and adaptively calibrating the gain value of the analog signal transmission channel based on the standard deviation of historical signal fluctuations. When the data synchronization verification module works in conjunction with the status cache queue, the following timing optimization method is executed: the timestamp tag is associated and mapped with the batch number of the status cache queue; when the actual action timestamp deviates from the preset instruction timestamp by more than 2ms, the status cache queue of the servo drive unit is automatically cleared; and a timing abnormality interrupt signal is sent to the PC via a second loop, along with recommended parameters for the deviation compensation algorithm.

[0016] Beneficial effects

[0017] This solution provides a logically separated multi-servo motor electronic control system. Through its innovative logic layering and multi-loop architecture, it achieves breakthrough improvements in real-time performance, reliability, scalability, and interference immunity. Its core innovation lies in decoupling the traditional integrated architecture into three independent functional loops, implementing signal classification processing and dynamic isolation through logic units. This logically separated multi-servo motor electronic control system's communication structure offers significant benefits. By separating data streams by response speed, position update data from the control card is transmitted at high speed via the first loop, ensuring efficient transmission of master control data. The position and status data of the controlled object are transmitted directly via the third loop, while the servo drive's execution status is transmitted via the second loop. This eliminates the need for the computer to occupy the industrial bus on the first loop while identifying the controlled object's status and reading the servo drive's status, effectively preventing bus congestion. This design optimizes the blocking / time-sharing polling process for reading the drive's status. Compared with the conventional dead loop reading or independent thread timed reading, which results in a large number of status reading commands in the first loop and reduces response efficiency, this solution enables the drive status to be transmitted through the second loop, and the computer code can respond in an interrupt manner. This not only avoids congestion of the first loop bus, but also simplifies the program execution process, reduces a large number of blocking dead loops and thread competition problems, and greatly improves the program execution efficiency, thereby ensuring stable and efficient operation of the entire electronic control system.

[0018] In summary, this solution solves the long-standing real-time, reliability, and scalability challenges in the field of multi-servo collaborative control through revolutionary innovations at the architectural level. Its three-loop logic separation mechanism and dynamic fault-tolerant strategy provide a new technical paradigm for the field of industrial automation, especially in demanding scenarios such as high-precision CNC machine tools and collaborative robots. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0020] Figure 1 This is a module connection diagram of a logic-separated multi-servo motor electronic control system provided by the first embodiment of the present invention. DETAILED DESCRIPTION

[0021] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0022] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture. If the specific posture changes, the directional indications will also change accordingly.

[0023] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only for descriptive purposes and cannot be understood as indicating or suggesting their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features limited to "first" and "second" may explicitly or implicitly include at least one of such features. In addition, if "and / or" or "and / or" appears in the full text, its meaning includes three parallel solutions. Taking "A and / or B" as an example, it includes solution A, solution B, or solutions that satisfy both A and B. In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the ability of ordinary technicians in this field to implement. When the combination of technical solutions is mutually contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0024] Example 1

[0025] With the continuous improvement of industrial automation, the demand for coordinated control of multiple servo motors is growing. This logic-separated multi-servo motor electronic control system aims to provide an efficient, stable, and reliable control solution. By logically separating the various parts of the system and adopting advanced communication and control technologies, it achieves precise control and real-time monitoring of multiple servo motors and their controlled objects.

[0026] refer to Figure 1The present invention provides a PC-end computer (1), a control unit (2), an industrial bus (3), a servo drive unit (4), a logic unit (5) and a controlled object (6), wherein the PC-end computer (1) is electrically connected to the control unit (2), the industrial bus (3) and the servo drive unit (4) in sequence to form a first loop, and the first loop is used to transmit real-time control signals and position update data; the servo drive unit (4) is electrically connected to the logic unit (5) and the PC-end computer (1) in sequence to form a second loop, and the second loop is used to transmit execution status data of the servo drive; the controlled object (6) is electrically connected to the logic unit (5) and the PC-end computer (1) in sequence to form a third loop, and the third loop is used to transmit the real-time position signal and mechanical status data of the controlled object.

[0027] PC computer (1) can be a high-performance industrial-grade computer with strong data processing capabilities and rich interface resources. Its configuration should be able to process a large number of control instructions, status data and execute complex algorithms in real time. For example, an Intel Core i7 series processor can be used, with more than 16GB of memory and a solid-state drive of more than 512GB to ensure the smooth operation of the system. In terms of software, a customized control software is installed, which integrates a user interface, a control algorithm library, a data storage and analysis module, etc. The user interface is used by operators to set system parameters, monitor system status and issue control instructions; the control algorithm library contains a variety of advanced control algorithms, such as PID control, adaptive control, etc., and appropriate algorithms can be selected according to different application scenarios; the data storage and analysis module is used to store a large amount of data generated during the operation of the system and perform data analysis to provide a basis for system optimization.

[0028] The control unit (2) is generally designed as an independent control unit circuit board, which uses a high-performance microcontroller as the core processor, such as TI's C2000 series DSP chip. The control unit is responsible for receiving control instructions from the PC computer and parsing and preprocessing the instructions. It also has an interface circuit for communicating with the industrial bus, through which the processed control instructions are sent to the industrial bus. In terms of hardware design, the control unit needs to be strictly designed for electromagnetic compatibility (EMC) to ensure that it can operate stably in a complex industrial environment. For example, in the circuit board layout, the sensitive circuit is separated from the power circuit, a multi-layer circuit board design is used, and the grounding and shielding layers are reasonably arranged.

[0029] Industrial Bus (3) Use a high-speed, reliable industrial bus that complies with industrial standards, such as the EtherCAT bus. As a key part of the control command downlink channel, the industrial bus is responsible for quickly and accurately transmitting the real-time control signals and position update data of the control unit to the servo drive unit. To ensure the reliability of data transmission, the industrial bus uses shielded twisted pair as the transmission medium and ensures that the ground impedance is less than 1Ω. During the actual wiring process, the bus should not be laid in parallel with other high-voltage lines to reduce electromagnetic interference. At the same time, the connection nodes of the bus are strictly waterproofed and dustproofed to ensure normal operation in harsh industrial environments.

[0030] The servo drive unit (4) selects a suitable servo drive according to the requirements of the controlled object. Each servo drive unit corresponds to a servo motor. The servo drive unit receives control instructions from the industrial bus, drives the servo motor to operate, and monitors the motor's operating status in real time. In terms of hardware design, the servo drive unit has multiple protection functions such as overcurrent, overvoltage, and overheating to ensure the safe operation of the motor and drive, and can meet the complex signal acquisition and protocol conversion functional requirements of the logic unit.

[0031] The hardware circuit of the logic unit (5) includes at least two sets of independent physical interfaces, which respectively establish point-to-point connections with the servo drive unit and the controlled object. In the interface circuit connected to the servo drive unit, a special signal conditioning circuit is designed to filter, amplify, and process the signal output by the servo drive unit to meet the input requirements of the FPGA chip. In the interface circuit connected to the controlled object, corresponding interface circuits are designed according to the type of output signal of the controlled object. For analog signals, a differential signal transmission method is adopted, and a low-pass filter is set for filtering; for digital signals, an optical coupler isolation transmission method is adopted to improve the anti-interference ability of the system.

[0032] The controlled object (6) depends on the specific application scenario. In this embodiment, the controlled object is generally used to drive a mechanical load. The controlled object and the logic unit are connected through sensors and actuators. The sensors are used to collect the real-time position signals and mechanical status data of the controlled object, and the actuators are used to receive the control signals of the logic unit and drive the controlled object to operate. When selecting sensors and actuators, they should be reasonably selected based on the characteristics of the controlled object and the control accuracy requirements.

[0033] In some embodiments, the control software of the PC computer generates corresponding control instructions based on the control parameters and task requirements set by the user. These instructions are encrypted and sent to the control unit through the network communication interface. After receiving the instructions, the control unit decrypts and parses them, and sorts them according to the type and priority of the instructions. Then, the control unit packages the processed control instructions according to the communication protocol format of the industrial bus and sends them to the industrial bus. During the industrial bus transmission process, CRC check and other methods are used to verify the data to ensure the integrity and accuracy of the data. After receiving the control instruction package transmitted by the industrial bus, the servo drive unit unpacks and verifies it. If the verification passes, the servo motor is driven to operate according to the instruction content.

[0034] The servo drive unit monitors its own execution status data, such as motor current, voltage, speed, and temperature, in real time. This status data is collected at regular intervals and uploaded to the PC through the logic unit. After receiving the servo drive unit's status data, the logic unit performs protocol conversion and data preprocessing, such as data filtering and normalization. The logic unit then sends the processed data to the PC via a network communication interface. After receiving the data, the PC's control software stores and analyzes it, and displays the servo drive unit's status information in real time on the user interface. If an abnormal state is detected in the servo drive unit, such as overcurrent or overheating, the control software will immediately issue an alarm and take appropriate protective measures, such as stopping the motor.

[0035] The sensors of the controlled object collect real-time position signals and mechanical status data, such as vibration and pressure. This data is uploaded to a PC via a logic unit. After receiving the controlled object's status data, the logic unit first filters and performs analog-to-digital conversion on the analog signals, and performs signal de-jittering and logic level conversion on the digital signals. The logic unit then packages the processed data according to a specific communication protocol format and sends it to the PC via a network communication interface. The PC's control software receives the data, stores and analyzes it, and uses this data to adjust and optimize control instructions to achieve precise control of the controlled object. For example, if the position deviation of the controlled object exceeds a set threshold, the control software automatically adjusts the control instructions to return the controlled object to its correct position.

[0036] In this embodiment, the first loop is configured as a unidirectional data transmission channel. The hardware connection and software configuration of the industrial bus ensure that data is transmitted only from the control unit to the servo drive unit. In terms of hardware connection, a dedicated unidirectional transmission interface chip is used. In terms of software configuration, the industrial bus communication protocol is customized to explicitly specify unidirectional data transmission. In this embodiment, the provision of this unidirectional data transmission channel can avoid data conflicts and interference, improving the reliability and real-time performance of control command transmission.

[0037] To ensure data transmission reliability in a unidirectional data flow transmission channel, the following measures are implemented: First, a CRC check is performed on each data packet during data transmission. The CRC check code is generated and verified using the standard CRC-16 algorithm. When the servo drive unit receives a data packet, it first verifies its CRC check code. If the check fails, the control unit is instructed to resend the packet. Second, in the physical layer design of the industrial bus, a shielded twisted pair cable is used as the transmission medium, and the shield is properly grounded. This effectively reduces the impact of external electromagnetic interference on data transmission and improves data transmission stability.

[0038] In the hardware circuit design of the logic unit, a dedicated interrupt detection circuit is designed based on the status signals of the servo drive unit and the controlled object. This circuit is implemented using digital circuit components such as comparators and triggers. Servo drive status signals, such as motor overcurrent and overheating, are compared with preset thresholds by the comparator. When the status signal exceeds the preset threshold, the comparator outputs a high-level signal, triggering the trigger to generate an interrupt signal. Similarly, comparators and triggers are used to generate interrupt signals for controlled object status signals, such as position signals exceeding a set range or vibration signals exceeding a threshold. In the circuit design, the parameters of the comparator and trigger are carefully selected to ensure accurate and timely interrupt detection.

[0039] Furthermore, the logic unit supports rising edge triggering and high-level continuous triggering modes. In rising edge triggering mode, when the rising edge of the status signal is detected, the priority interrupt signal is immediately triggered and uploaded to the PC computer. In high-level continuous triggering mode, when the status signal continues to be higher than the preset threshold for more than the set time, the priority interrupt signal is triggered and uploaded to the PC computer. In terms of software programming, the interrupt control register of the FPGA chip is configured to set the interrupt triggering mode to rising edge triggering or high-level continuous triggering. At the same time, in the interrupt handling program, the interrupt signal is identified and processed, and corresponding operations are performed according to different interrupt sources, such as sending alarm information to the PC computer, adjusting control instructions, etc.

[0040] A differential signal transmission method is used for analog signals transmitted in the controlled object status channel. A differential signal transmission chip is used in the analog signal transmission line between the logic unit and the controlled object. This differential signal transmission method effectively suppresses common-mode interference and improves the accuracy and reliability of signal transmission. A low-pass filter is set in the analog signal transmission channel, with a cutoff frequency three times the motion frequency of the controlled object. This low-pass filter is designed as a second-order Butterworth filter, with a filter circuit composed of components such as resistors and capacitors. In the hardware design, the parameters of the resistors and capacitors are appropriately selected to meet the cutoff frequency requirements. Simultaneously, the analog signals are converted to digital using a high-precision analog-to-digital converter.

[0041] The second loop in this embodiment is set as a digital signal transmission channel, and an optocoupler isolation transmission method is adopted for the digital signal transmitted in the state channel of the controlled object. An optocoupler isolation chip, such as Toshiba's TLP521, is used on the digital signal transmission line between the logic unit and the controlled object. Optocoupler isolation can effectively isolate the electrical connection between the logic unit and the controlled object, and prevent interference signals from being transmitted from the controlled object side to the logic unit. In the digital signal transmission channel, a hysteresis comparator is configured to eliminate signal jitter interference. The hysteresis comparator is implemented using a comparator chip such as LM339. By setting a suitable hysteresis voltage, the jitter of the digital signal within a certain range will not affect the judgment of its logic level. Inside the FPGA chip, the digital signal is logically processed and protocol converted to a format that meets the communication requirements of the PC computer.

[0042] In this embodiment, the third loop constitutes the controlled object state channel. The controlled object is electrically connected to the logic unit and the PC in sequence. The third loop is used to transmit the controlled object's real-time position signal and mechanical state data. When the controlled object outputs analog mechanical state data, such as vibration amplitude and temperature, these signals first enter the logic unit's analog input channel. In the analog signal transmission channel, differential signal transmission is used. Taking the output signal of a vibration sensor as an example, the sensor's two signal lines are connected to the positive and negative input terminals of the differential signal transmission chip, respectively. Differential signal transmission can effectively suppress common-mode interference and improve the accuracy and reliability of signal transmission. The signal is filtered through a low-pass filter. The low-pass filter adopts a second-order Butterworth filter design and consists of components such as resistors and capacitors. Based on the motion characteristics of the controlled object, the cutoff frequency of the low-pass filter is set to three times the motion frequency of the controlled object. An analog-to-digital converter converts the analog signal into a digital signal, which is then transmitted in parallel or serially to the FPGA chip for subsequent processing.

[0043] In the data synchronization verification module between the control unit and the servo drive unit, the control unit generates a timestamp after each position update data transmission. This timestamp is generated using a high-precision timer, such as the timer module within the control unit. The timer's accuracy must meet the system's time synchronization requirements, typically reaching microseconds. When generating the timestamp, the current count value is used as the timestamp value and is packaged along with the position update data and sent to the servo drive unit. After receiving the position update data and driving the servo motor to execute the action, the servo drive unit transmits the actual action timestamp to the PC via the logic unit and the controlled object status channel of the third loop. The actual action timestamp is obtained using the feedback signal from the servo motor encoder as a reference. When the servo motor rotates to the specified position, the encoder generates a corresponding pulse signal. The logic unit calculates the actual action time of the servo motor based on the encoder pulse signal and generates the actual action timestamp. The actual action timestamp is transmitted to the PC via the network communication interface. Upon receiving the actual action timestamp, the PC compares it with the preset command timestamp to calculate the time deviation. If the time deviation exceeds a set threshold, the PC adjusts the timing of control command transmission to achieve closed-loop time synchronization between the control command and the executed action. During this closed-loop time synchronization process, a PID control algorithm is used to adjust the time deviation. The PID control algorithm parameters are optimized based on the actual system operation to ensure the accuracy and stability of time synchronization. For example, through experimental testing of different PID parameter combinations, the parameter combination that minimizes time deviation and maximizes system response is selected.

[0044] A bandwidth utilization monitoring module is designed for the servo drive unit. This module monitors the bandwidth utilization of the industrial bus in real time. It calculates the bandwidth utilization by statistically analyzing the data flow and rate transmitted on the industrial bus. The bandwidth utilization calculation formula is: Bandwidth utilization = (actual data rate / rated data rate of the industrial bus) × 100%. In the hardware design, a network traffic monitoring chip, such as Microchip's ENC28J60, is used to monitor the data flow on the industrial bus. In the software programming, the bandwidth utilization is calculated and analyzed by periodically reading the data from the traffic monitoring chip.

[0045] When it detects that the industrial bus bandwidth utilization rate exceeds 70%, the servo drive unit automatically temporarily stores non-emergency data in the status cache queue. The status cache queue is implemented using a first-in-first-out (FIFO) data structure and can be constructed using the memory resources within the FPGA chip. When data is temporarily stored in the status cache queue, it is classified and marked so that it can be subsequently uploaded to the PC in batches. When the industrial bus bandwidth utilization rate drops to a certain level, the servo drive unit reads the data from the status cache queue and uploads it to the PC in batches via the second loop. During the data upload process, the upload order is reasonably arranged based on the priority and importance of the data to ensure that emergency data is uploaded first.

[0046] In some embodiments, the logic unit utilizes an FPGA chip to implement signal acquisition and protocol conversion. Its hardware circuitry includes at least two independent physical interfaces, each establishing a point-to-point connection with the servo drive unit and the controlled object. The FPGA chip leverages its extensive I / O interface resources to establish point-to-point connections with the servo drive unit and the controlled object, implementing signal acquisition. The I / O interface connected to the servo drive unit collects the servo drive unit's output status signals and control feedback signals; the I / O interface connected to the controlled object collects the object's real-time position signals and mechanical status data. Regarding protocol conversion, the FPGA chip performs format conversion and encoding on the collected signals according to the requirements of different communication protocols. For example, collected analog signals undergo analog-to-digital conversion and are packaged according to a specific communication protocol format; digital signals undergo logic level conversion and protocol encapsulation. When programming the FPGA chip, a hardware description language (such as Verilog or VHDL) is used to design and develop the signal acquisition and protocol conversion modules.

[0047] The FPGA chip has an embedded dynamic protocol configuration engine, allowing the following operations to be performed remotely via a PC: First, it automatically matches the communication protocol type based on the servo drive unit model. The PC's control software pre-stores the correspondence between various servo drive unit models and communication protocol types. When the system boots up, the PC sends a query command to the logic unit to obtain the model information of the currently connected servo drive unit. The logic unit feeds this model information back to the PC, which selects the appropriate communication protocol type based on the correspondence and sends the protocol configuration parameters to the logic unit. Based on the received protocol configuration parameters, the FPGA chip's dynamic protocol configuration engine automatically adjusts the internal communication protocol module to match the servo drive unit's communication protocol. Second, it dynamically adjusts the digital signal sampling frequency during operation, within a range of 1kHz to 10kHz. The PC's control software provides a digital signal sampling frequency adjustment interface, allowing the operator to enter the sampling frequency value according to actual needs. The PC sends the sampling frequency adjustment command to the logic unit, and the FPGA chip's dynamic protocol configuration engine adjusts the clock frequency of the digital signal sampling module accordingly, achieving dynamic adjustment of the sampling frequency. Third, the gain value of the analog signal transmission channel is adaptively calibrated based on the standard deviation of historical signal fluctuations. During the operation of the logic unit, analog signals are continuously collected and the standard deviation of historical signal fluctuations is calculated. When the standard deviation exceeds the set threshold, the logic unit sends a gain calibration request to the PC. The PC calculates the gain calibration value of the analog signal transmission channel based on the standard deviation of historical signal fluctuations and the preset calibration algorithm, and sends the calibration value to the logic unit. The dynamic protocol configuration engine of the FPGA chip adjusts the gain module of the analog signal transmission channel according to the calibration value to achieve adaptive calibration of the gain value.

[0048] The control unit and logic unit in this embodiment are respectively deployed on independent circuit boards, and there is no direct electrical connection between the two. In the system design, the functions of the control unit and the logic unit are clearly divided, and independent circuit boards are designed for each. The control unit circuit board is mainly responsible for the generation and processing of control instructions, and the logic unit circuit board is mainly responsible for signal acquisition, protocol conversion and logical judgment. In terms of communication between circuit boards, optocoupler isolation or wireless communication is used to avoid interference caused by direct electrical connection. For example, the control signal output by the control unit is transmitted to the logic unit through an optocoupler isolation chip to achieve electrical isolation.

[0049] Industrial buses use shielded twisted pair cables as transmission media, and the grounding impedance is less than 1Ω. During the wiring of the industrial bus, ensure that the shielding layer of the shielded twisted pair cables is reliably grounded throughout the entire process. The grounding method can be single-point grounding or multi-point grounding. Select the appropriate grounding method based on the actual situation. For example, in an industrial field environment that is more complex and has strong electromagnetic interference,

[0050] In summary, the communication architecture of this logically separated multi-servo motor electronic control system offers significant benefits. By separating data streams by response speed, the control card's position update data is transmitted at high speed via the first loop, ensuring efficient transmission of primary control data. The controlled object's position and status data travel directly through the third loop, while the servo driver's execution status is transmitted via the second loop. This prevents the computer from occupying the industrial bus on the first loop when identifying the controlled object's status and reading the servo driver's status, effectively preventing bus congestion. This design optimizes the blocking / time-sharing polling process for driver status reading. Compared to conventional closed-loop reading or independent thread timed reading, which results in a large number of status read commands on the first loop and reduces response efficiency, this solution transmits the driver status via the second loop, enabling computer code to respond via interrupts. This not only avoids congestion on the first loop bus but also simplifies program execution, reducing numerous blocked closed-loops and thread contention issues. This significantly improves program execution efficiency, thereby ensuring stable and efficient operation of the entire electronic control system.

[0051] The above description is only a preferred embodiment of the present invention and does not limit the patent scope of the present invention. All equivalent structural transformations made by using the contents of the present invention description and drawings under the inventive concept of the present invention, or direct / indirect application in other related technical fields are included in the patent protection scope of the present invention.

Claims

1. A logic-separated multi-servo motor electronic control system, characterized in that: include: PC computer, control unit, industrial bus, servo drive unit, logic unit and controlled object, The PC is electrically connected to the control unit, the industrial bus, and the servo drive unit in sequence to form a first loop, which is used to transmit real-time control signals and position update data; The servo drive unit is electrically connected to the logic unit and the PC in sequence to form a second loop, and the second loop is used to transmit the execution status data of the servo drive; The controlled object is electrically connected to the logic unit and the PC computer in sequence to form a third loop, and the third loop is used to transmit the real-time position signal and mechanical state data of the controlled object.

2. The logic separation type multi-servo motor electronic control system according to claim 1, characterized in that: Including, the industrial bus in the first loop is a unidirectional data stream transmission channel, used to transmit data from the control unit to the servo drive unit.

3. The logic separation type multi-servo motor electronic control system according to claim 1, characterized in that: The interrupt response mechanism of the logic unit is specifically as follows: when it is detected that the status signal of the servo drive unit or the controlled object reaches a preset threshold, a priority interrupt signal is immediately triggered and uploaded to the PC computer. The interrupt triggering mode includes rising edge triggering and high level continuous triggering mode.

4. The logic separation type multi-servo motor electronic control system according to claim 1, characterized in that: The logic unit includes a signal type separation module, and the mechanical state data transmitted in the controlled object state channel is divided into an analog signal transmission channel and a digital signal transmission channel, wherein the analog signal adopts a differential signal transmission method, and the digital signal adopts an optical coupler isolation transmission method.

5. The logic separation type multi-servo motor electronic control system according to claim 2, characterized in that: A data synchronization verification module is provided between the control unit and the servo drive unit. The module generates a timestamp mark after each position update data transmission, and feeds back the actual action timestamp to the PC computer through the controlled object status channel of the third loop, thereby realizing closed-loop time synchronization between the control instructions and the execution actions.

6. The logic separation type multi-servo motor electronic control system according to claim 1, characterized in that: The servo drive unit includes a status cache queue. When it detects that the industrial bus bandwidth occupancy rate exceeds 70%, it automatically temporarily stores non-emergency status data in the status cache queue and uploads it to the PC computer in batches through the second loop.

7. The logic separation type multi-servo motor electronic control system according to claim 1, characterized in that: The logic unit uses an FPGA chip to implement signal acquisition and protocol conversion functions, and its hardware circuit includes at least two sets of independent physical interfaces, which respectively establish point-to-point connections with the servo drive unit and the controlled object.

8. The logic separation type multi-servo motor electronic control system according to claim 1, characterized in that: The signal transmission paths of the second loop and the third loop use carriers of different frequency bands for communication.

9. The logic separation type multi-servo motor electronic control system according to claim 1, characterized in that: The PC computer is equipped with a dynamic bandwidth allocation module, which monitors the bandwidth occupancy of the three data channels in real time. When the real-time control signal transmission demand of the first loop surges, the interrupt response frequency of the second and third loops is automatically reduced to prioritize and ensure the integrity of control instruction transmission.

10. The logic separation type multi-servo motor electronic control system according to claim 1, characterized in that: The logic unit includes a signal preprocessing module, which performs data processing according to the mechanical state data of the controlled object. The data processing steps include: setting a low-pass filter in the analog signal transmission channel; configuring a hysteresis comparator in the digital signal transmission channel to eliminate signal jitter interference; and uploading the processed data to a PC computer through the controlled object status channel of the third loop.

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