Voltage trimming circuit and integrated circuit including same

Abstract

The voltage trimming circuit includes a comparator, a code generator, a non-volatile memory device, a switching circuit, and a voltage generator. The comparator compares the reference voltage with the feedback voltage. The code generator generates a plurality of trimming codes for trimming the feedback voltage based on a comparison result of the comparator. If the feedback voltage is less than the reference voltage, the code generator adjusts an up-regulation code for increasing the feedback voltage among the plurality of trimming codes, and maintains a down-regulation code for decreasing the feedback voltage among the plurality of trimming codes at an initial value. If the feedback voltage is greater than the reference voltage, the code generator adjusts the down-regulation code and maintains the up-regulation code at an initial value.

Description

[0001] This application is a divisional application of the Chinese patent application “Voltage fine-tuning circuit and integrated circuit including a voltage fine-tuning circuit” (application number: 201810343039.1) filed on April 17, 2018.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims the benefit of Korean Patent Application No. 10-2017-0062871 filed on May 22, 2017, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0004] Embodiments of the inventive concepts described herein relate to voltage trimming circuits, operating methods thereof, and integrated circuits including the voltage trimming circuits, and more particularly, to voltage trimming circuits including antifuses, operating methods thereof, and integrated circuits including the voltage trimming circuits. Background Art

[0005] Integrated circuits (ICs) can generate internal voltages using a drive voltage (e.g., VDD). These internal voltages may not be accurately set to the desired voltage level and may require trimming or adjusting their levels. To trim the internal voltages, test equipment (external to the IC) can read the internal voltages through pads on the IC. This voltage level trimming time, which includes the time it takes the test equipment to read the internal voltages and the time it takes to control the internal circuitry within the IC to trim the voltages, can increase test time. This increased IC test time can reduce IC yield.

[0006] Furthermore, when test equipment adjusts the internal voltage of an integrated circuit, the internal voltage may not be accurately set to a reference voltage or a target voltage due to the unique resolution of the test equipment. In particular, since the driving voltage decreases as the integrated circuit is finely manufactured, it is important to more accurately set the internal voltage.

[0007] In order to solve the above problem, it is proposed to use a voltage trimming circuit to internally adjust the internal voltage of the integrated circuit. Summary of the Invention

[0008] Embodiments of the inventive concept provide a voltage fine-tuning circuit including an antifuse, an operating method thereof, and an integrated circuit including the voltage fine-tuning circuit.

[0009] According to one aspect of the present invention, a voltage trimming circuit includes a comparator, a code generator, a non-volatile memory device, a switching circuit, and a voltage generator. The comparator is configured to compare a reference voltage with a feedback voltage. The code generator is configured to generate a plurality of trimming codes for trimming the feedback voltage based on a comparison result of the comparator. If the comparison result indicates that the feedback voltage should be increased, the code generator adjusts an up-adjustment code among the plurality of trimming codes to increase the feedback voltage while maintaining a down-adjustment code among the plurality of trimming codes at an initial value. If the comparison result indicates that the feedback voltage should be decreased, the code generator adjusts the down-adjustment code among the plurality of trimming codes while maintaining the up-adjustment code at an initial value. The non-volatile memory device is configured to store a plurality of final trimming codes adjusted by the code generator. The switching circuit is configured to select the plurality of trimming codes during a trimming mode and to select the plurality of final trimming codes after the trimming mode. The voltage generator is configured to generate the feedback voltage based on the plurality of trimming codes selected by the switching circuit.

[0010] According to another aspect of the present invention, a method for operating a voltage trimming circuit includes: comparing a reference voltage with a feedback voltage using a comparator; adjusting an up-adjustment code to increase the feedback voltage and adjusting a down-adjustment code to decrease the feedback voltage; and, after adjusting the up-adjustment code and the down-adjustment code, programming the up-adjustment code and the down-adjustment code into an antifuse array including a plurality of antifuses. The adjusting includes: if the comparison result indicates that the feedback voltage is to be increased, setting a value of the up-adjustment code to increase the feedback voltage, and if the comparison result indicates that the feedback voltage is to be decreased, setting a value of the down-adjustment code to decrease the feedback voltage.

[0011] According to another aspect of the present invention, an integrated circuit includes a first switching circuit, a comparator, a code generator, a nonvolatile memory device, a second switching circuit, and a plurality of voltage generators. The first switching circuit is configured to select a plurality of internal voltages of the integrated circuit. The comparator is configured to compare an internal voltage selected by the first switching circuit from the plurality of internal voltages with a reference voltage. The code generator is configured to adjust a plurality of trimming codes used to fine-tune each of the plurality of internal voltages based on a comparison result of the comparator. The nonvolatile memory device is configured to store a plurality of final trimming codes adjusted by the code generator. The second switching circuit is configured to select the plurality of trimming codes during a trimming mode and select the plurality of final trimming codes after the trimming mode. The plurality of voltage generators are configured to generate a plurality of internal voltages based on the plurality of trimming codes selected by the second switching circuit. Each of the plurality of trimming codes includes an up-tune code for increasing the plurality of internal voltages and a down-tune code for decreasing the plurality of internal voltages. If the code generator adjusts any one of the upward adjustment code and the downward adjustment code, the code generator maintains the other of the upward adjustment code and the downward adjustment code at an initial value. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a block diagram illustrating a voltage fine-tuning circuit according to an embodiment of the inventive concept.

[0013] Figure 2 It shows Figure 1 FIG. 1 is a diagram showing a flow chart of the fine-tuning operation of the code generator.

[0014] Figure 3 It shows Figure 1 Figure 1 shows the timing diagram of the code generator.

[0015] Figure 4 It shows Figure 1 FIG. 1 is a diagram showing a flow chart of the fine-tuning operation of the code generator.

[0016] Figure 5 It shows Figure 1 Figure 1 shows the timing diagram of the code generator.

[0017] Figure 6 It shows Figure 1 A block diagram of a non-volatile memory device is shown.

[0018] Figure 7 It shows Figure 1 The structure of the voltage generator is shown in the figure.

[0019] Figure 8is a block diagram illustrating a voltage fine-tuning circuit according to another embodiment of the inventive concept.

[0020] Figure 9 It shows Figure 8 Figure 1 shows the timing diagram of the accumulation circuit.

[0021] Figure 10 is a block diagram illustrating an integrated circuit according to an embodiment of the inventive concept.

[0022] Figure 11 is a diagram illustrating a flowchart associated with an operation of a voltage fine tuning circuit according to an embodiment of the inventive concept.

[0023] Figure 12 is a diagram showing a flowchart associated with the operation of the trimming circuit after the trimming operation. DETAILED DESCRIPTION

[0024] The embodiments of the present inventive concept may be described in detail and clearly so that those having ordinary skill in the art can easily realize the present inventive concept.

[0025] Figure 1 is a block diagram illustrating a voltage fine-tuning circuit according to an embodiment of the inventive concept. Figure 1 The voltage trimming circuit 100 may include a comparator 110, a code generator 120, a nonvolatile memory device 130, a switch circuit 140, and a voltage generator 150. The voltage trimming circuit 100 may set the feedback voltage VFB as the reference voltage VREF. The elements of the voltage trimming circuit 100 will be described in detail.

[0026] The comparator 110 may compare the reference voltage VREF with the feedback voltage VFB and may generate a comparison result COMP. The reference voltage VREF may be a voltage provided from outside the voltage fine-tuning circuit 100, and the feedback voltage VFB may be a voltage generated by the voltage generator 150 using the driving voltage (eg, VDD) of the voltage fine-tuning circuit 100. The feedback voltage VFB may be provided to Figure 1 Another circuit not shown in FIG. 1 (eg, a circuit in an integrated circuit including the voltage trimming circuit 100 ).

[0027] In an embodiment, the comparator 110 may be an operational amplifier. Before the comparator 110 compares the reference voltage VREF with the feedback voltage VFB, offset cancellation may be performed first.

[0028] Comparator 110 can receive a reference voltage VREF via a non-inverting input terminal (or "positive input terminal") and a feedback voltage VFB via an inverting input terminal (or "negative input terminal"). In an embodiment, if the feedback voltage VFB is higher than the reference voltage VREF, the comparison result COMP may be low; if the feedback voltage VFB is lower than the reference voltage VREF, the comparison result COMP may be high. The comparison result COMP may be a digital signal.

[0029] The code generator 120 may generate an up-adjustment code UP_CODE[N:1] and a down-adjustment code DN_CODE[N:1] based on the comparison result COMP. Here, "N" is a natural number of 1 or greater. The code generator 120 may adjust the up-adjustment code UP_CODE[N:1] and the down-adjustment code DN_CODE[N:1] so that the feedback voltage VFB is set to the reference voltage VREF. Here, the up-adjustment code UP_CODE[N:1] and the down-adjustment code DN_CODE[N:1] may be a plurality of fine-tuning codes for fine-tuning the feedback voltage VFB. In the fine-tuning mode, the up-adjustment code UP_CODE[N:1] and the down-adjustment code DN_CODE[N:1] adjusted by the code generator 120 may be a plurality of final fine-tuning codes.

[0030] Specifically, as the up-code UP_CODE[N:1] increases, the feedback voltage VFB may also increase, and as the down-code DN_CODE[N:1] decreases, the feedback voltage VFB may also decrease. The amount of the increment of the feedback voltage VFB for each of the up-codes UP_CODE[N:1] may be different. The amount of the decrement of the feedback voltage VFB for each of the down-codes DN_CODE[N:1] may be different. When the most significant bit UP_CODE[N] of the up-code changes, the increment of the feedback voltage VFB may be the largest, and when the least significant bit UP_CODE[1] of the up-code changes, the increment of the feedback voltage VFB may be the smallest. Similarly, the decrement of the feedback voltage VFB by the down-code DN_CODE[N] as the most significant bit may be the largest, and the decrement of the feedback voltage VFB by the down-code DN_CODE[1] as the least significant bit may be the smallest.

[0031] In an embodiment, regarding the feedback voltage VFB, the code generator 120 may adjust the up-code UP_CODE[N:1] in order from the most significant bit to the least significant bit, and may adjust the down-code DN_CODE[N:1] in order from the most significant bit to the least significant bit. Figures 2 to 5 The operation of code generator 120 is described more fully.

[0032] The nonvolatile memory device 130 can store the adjustment code UP_CODE[N:1] and the adjustment code DN_CODE[N:1] adjusted by the code generator 120, wherein the feedback voltage VFB is set to the reference voltage VREF. Since the nonvolatile memory device 130 stores the adjustment result of the feedback voltage VFB, the value of the feedback voltage VFB can be maintained after the system including the nonvolatile memory device is powered off, and the value of the feedback voltage VFB can be reused immediately after the system is powered on.

[0033] After fine-tuning, the nonvolatile memory device 130 may provide the stored up-tuning code UP_CODE[N: 1] and the stored down-tuning code DN_CODE[N: 1] to the voltage generator 150 through the switch circuit 140 .

[0034] In one embodiment, the non-volatile memory device 130 may include an antifuse array. The antifuses can be electrically programmed to change from a high resistance state to a low resistance state. In another embodiment, the non-volatile memory device 130 may include any of the following: NAND flash memory, NOR flash memory, magnetic random access memory (MRAM), phase change random access memory (PRAM), resistive random access memory (RRAM), ferroelectric random access memory (FRAM), and thyristor random access memory (TRAM).

[0035] The switch circuit 140 may select the up-adjustment code UP_CODE[N:1] and the down-adjustment code DN_CODE[N:1] adjusted by the code generator 120 or the up-adjustment code UP_CODE[N:1] and the down-adjustment code DN_CODE[N:1] stored in the non-volatile memory device 130, and may provide the selected code to the voltage generator 150. The switch circuit 140 may select the up-adjustment code UP_CODE[N:1] and the down-adjustment code DN_CODE[N:1] of the code generator 120 when the feedback voltage VFB is being adjusted (i.e., in the fine adjustment mode). In this case, the up-adjustment code UP_CODE[N:1] and the down-adjustment code DN_CODE[N:1] from the code generator 120 may continuously change until the feedback voltage VFB is set to the reference voltage VREF (refer to a method to be described later). Figure 2 and Figure 3 ).

[0036] After the fine-tuning mode, the switch circuit 140 may select the up-tuning code UP_CODE[N:1] and the down-tuning code DN_CODE[N:1] stored in the non-volatile memory device 130. In this case, the up-tuning code UP_CODE[N:1] and the down-tuning code DN_CODE[N:1] may have specific values. In an embodiment, the switch circuit 140 may perform a multiplexer function.

[0037] The voltage generator 150 can generate the feedback voltage VFB based on the multiple trimming codes selected by the switch circuit 140. In the trimming mode, the voltage generator 150 can adjust the feedback voltage VFB based on the multiple trimming codes being changed. After the trimming mode, the voltage generator 150 can generate a feedback voltage VFB similar to the reference voltage VREF based on the multiple trimming codes having specific values ​​stored in the non-volatile memory device 130. Figure 7 The structure of the voltage generator 150 is described more fully.

[0038] Figure 2 It shows Figure 1 The flowchart of the fine-tuning operation of the code generator is shown in FIG. Figure 1 describe Figure 2 .exist Figure 2 In the example, it is assumed that the initial values ​​of the up-code UP_CODE[N:1] and the down-code DN_CODE[N:1] are “0000000” respectively. b ”.

[0039] In operation S110 , the code generator 120 may receive a comparison result COMP from the comparator 110 .

[0040] In operation S120, the code generator 120 determines whether the feedback voltage VFB is less than the reference voltage VREF. If the feedback voltage VFB is less than the reference voltage VREF in operation S120 (Yes), the code generator 120 may perform operation S131. If the feedback voltage VFB is greater than the reference voltage VREF in operation S120 (No), the code generator 120 may perform operation S132.

[0041] If the feedback voltage VFB is less than the reference voltage VREF, the code generator 120 may set the up-code UP_CODE[N] to “1” in operation S131. If the feedback voltage VFB is greater than the reference voltage VREF, the code generator 120 may set the down-code DN_CODE[N] to “1” in operation S132.

[0042] Since the Nth up-adjustment code UP_CODE[N] or the Nth down-adjustment code DN_CODE[N] is set in operation S131 or operation S132, the code generator 120 may prepare to set the (N-1)th up-adjustment code UP_CODE[N-1] or the (N-1)th down-adjustment code DN_CODE[N-1] in operation S140.

[0043] In operation S150, the code generator 120 may determine whether all the up-adjustment codes UP_CODE[N:1] or down-adjustment codes DN_CODE[N:1] have been used (i.e., N='0'). If it is determined that all the up-adjustment codes UP_CODE[N:1] or down-adjustment codes DN_CODE[N:1] have been used (Yes), the fine-tuning operation may end after the up-adjustment codes UP_CODE[N:1] and down-adjustment codes DN_CODE[N:1] have been stored in the non-volatile memory device 130. If it is determined in operation S150 that all the up-adjustment codes UP_CODE[N:1] or down-adjustment codes DN_CODE[N:1] have not been used (No), the fine-tuning operation may be repeated. In other words, the code generator 120 may repeatedly perform operations S110 to S150.

[0044] Figure 2 The flowchart of the code generator 120 shown may refer to a case where the code generator 120 operates according to a binary search algorithm or a case where the code generator 120 operates in a manner similar to a successive approximation analog-to-digital converter (SAR ADC). Figure 2 1 is a timing diagram of the flow chart of the code generator 120.

[0045] Figure 3 It shows Figure 1 The timing diagram of the code generator is shown in Figure 1. Figure 1 and Figure 2 To describe Figure 3 .exist Figure 3 In FIG. 1 , the horizontal axis indicates time. Assume that “N” of each of the up-code UP_CODE[N:1] and the down-code DN_CODE[N:1] is “7”. Also, assume that each of the increments of the up-code UP_CODE[N:1] for increasing the feedback voltage VFB is equal to 2 N and similarly, assuming that each of the decrements of the down-regulation code DN_CODE[N:1] for decreasing the feedback voltage VFB is proportional to 2 N Directly proportional.

[0046] From time point T1 to time point T2, the initial voltage level of the feedback voltage VFB is the first voltage level V1. The feedback voltage VFB is less than the reference voltage VREF. Therefore, the comparison result COMP of the comparator 110 can be higher. The code generator 120 can adjust the up-code UP_CODE[7:1] to increase the feedback voltage VFB. The code generator 120 can first control the up-code UP_CODE[7] as the most significant bit. As described above, the increment of the up-code UP_CODE[7] is the largest. Before time point T2, the code generator 120 can set the MSB up-code UP_CODE[7] in the up-code UP_CODE[7:1] to "1" (operation S131). The feedback voltage VFB can increase from the first voltage level V1 to the second voltage level V2.

[0047] From time point T2 to time point T3, by adjusting the code generator 120, the feedback voltage VFB can be greater than the reference voltage VREF. Therefore, the comparison result COMP of the comparator 110 can be lower. The code generator 120 can adjust the down-adjustment code DN_CODE[7:1] to reduce the feedback voltage VFB. In this case, if the MSB down-adjustment code DN_CODE[7] is set to "1", the feedback voltage VFB can return to a voltage level similar to the first voltage level V1 between time point T1 and time point T2. To this end, the code generator 120 may not set the MSB down-adjustment code DN_CODE[7] to "1", but may set the down-adjustment code DN_CODE[6] to "1" (operation S132). The feedback voltage VFB can be reduced from the second voltage level V2 to the third voltage level V3.

[0048] From time point T3 to time point T4, despite the adjustment of code generator 120, feedback voltage VFB may still be greater than reference voltage VREF. Therefore, comparison result COMP of comparator 110 may continue to be low. Code generator 120 may again adjust down-regulation code DN_CODE[7:1] to reduce feedback voltage VFB. In an embodiment, code generator 120 may set down-regulation code DN_CODE[5] to "1" (operation S132). Feedback voltage VFB may decrease from third voltage level V3 to fourth voltage level V4.

[0049] From time point T4 to time point T5, by adjusting code generator 120, feedback voltage VFB can be lower than reference voltage VREF. Therefore, comparison result COMP of comparator 110 can be higher. Code generator 120 can again adjust up-code UP_CODE[7:1] to increase feedback voltage VFB. In an embodiment, code generator 120 can set up-code UP_CODE[4] to "1" (operation S131). Feedback voltage VFB can increase from fourth voltage level V4 to fifth voltage level V5.

[0050] From time point T5 to time point T6, by adjusting code generator 120, feedback voltage VFB can be greater than reference voltage VREF. Therefore, comparison result COMP of comparator 110 can be lower. Code generator 120 can again adjust down-regulation code DN_CODE[7:1] to reduce feedback voltage VFB. In an embodiment, code generator 120 can set down-regulation code DN_CODE[3] to "1" (operation S132). Feedback voltage VFB can be reduced from fifth voltage level V5 to sixth voltage level V6.

[0051] From time point T6 to time point T7, by adjusting code generator 120, feedback voltage VFB can be lower than reference voltage VREF. Therefore, comparison result COMP of comparator 110 can be higher. Code generator 120 can again adjust up-code UP_CODE[7:1] to increase feedback voltage VFB. In an embodiment, code generator 120 can set up-code UP_CODE[2] to "1" (operation S131). Feedback voltage VFB can increase from sixth voltage level V6 to seventh voltage level V7.

[0052] From time point T7 to time point T8, by adjusting code generator 120, feedback voltage VFB can be greater than reference voltage VREF. Therefore, comparison result COMP of comparator 110 can be lower. Code generator 120 can again adjust down-regulation code DN_CODE[7:1] to reduce feedback voltage VFB. In an embodiment, code generator 120 can set down-regulation code DN_CODE[1] to "1" (operation S132). Feedback voltage VFB can be reduced from seventh voltage level V7 to the reference voltage level.

[0053] From time point T1 to time point T8, the code generator 120 may adjust the up-code UP_CODE[7:1] and the down-code DN_CODE[7:1]. After time point T8, the up-code UP_CODE[7:1] becomes "1001010 b " and down-regulate code DN_CODE[7:1] "0110101 b” may be stored in the non-volatile storage device 130.

[0054] As described above, the nonvolatile memory device 130 may include an antifuse array. The up-code UP_CODE[7:1] and the down-code DN_CODE[7:1] may be programmed into the antifuse array. Here, the programming operation may include a rupture operation in which the antifuse changes from a high resistance state to a low resistance state.

[0055] Specifically, the antifuse corresponding to each code with "1" in the up-code UP_CODE[7:1] and the down-code DN_CODE[7:1] may be broken, and the antifuse corresponding to each code with "0" in the up-code UP_CODE[7:1] and the down-code DN_CODE[7:1] may not be broken. After the time point T8, the seven antifuses corresponding to the up-codes UP_CODE[7], UP_CODE[4], and UP_CODE[2] and the down-codes DN_CODE[6], DN_CODE[5], DN_CODE[3], and DN_CODE[1] may be broken to change the up-code DN_CODE[7:1] to "1001010". b " and down-regulate code DN_CODE[7:1] "0110101 b " is programmed into the antifuse array. Figure 4 and Figure 5 The operation of the code generator 120 to reduce the number of broken antifuses is described.

[0056] Figure 4 It shows Figure 1 The flowchart of the fine-tuning operation of the code generator is shown in FIG. Figure 1 describe Figure 4 .exist Figure 4 In the example, it is assumed that the initial value of each of the up-code UP_CODE[N:1] and the down-code DN_CODE[N:1] is “0000000 b ”.

[0057] In operation S210 , the code generator 120 may receive a comparison result COMP from the comparator 110 .

[0058] In operation S220, the code generator 120 determines whether the feedback voltage VFB is less than the reference voltage VREF. If the feedback voltage VFB is less than the reference voltage VREF in operation S220 (Yes), the code generator 120 may perform operation S231. If the feedback voltage VFB is greater than the reference voltage VREF in operation S220 (No), the code generator 120 may perform operation S241.

[0059] In operation S231, the code generator 120 may set the up-adjustment code UP_CODE[N] to "1." If the feedback voltage VFB is less than the reference voltage VREF in operation S232 (Yes), the value of the up-adjustment code UP_CODE[N] set in operation S231 may remain unchanged at "1." However, if the feedback voltage VFB is greater than the reference voltage VREF in operation S232 (No), the code generator 120 may set the up-adjustment code UP_CODE[N] to "0" in operation S233. That is, after adjusting one of the up-adjustment codes UP_CODE[N:1] in operation S231, if the feedback voltage VFB is greater than the reference voltage VREF, the code generator 120 may change the value of the adjusted up-adjustment code to the value before adjustment (i.e., the initial value "0").

[0060] Since the Nth up-up code UP_CODE[N] is set in operations S231 and S233 , the code generator 120 may prepare to set the (N−1)th up-up code UP_CODE[N−1] in operation S234 .

[0061] In operation S235, the code generator 120 may determine whether all the up-adjustment codes UP_CODE[N:1] are used (i.e., N = "0"). If it is determined that all the up-adjustment codes UP_CODE[N:1] are used (Yes), the fine-tuning operation may end after the up-adjustment codes UP_CODE[N:1] and the down-adjustment codes DN_CODE[N:1] are stored in the non-volatile memory device 130. If it is determined that at least one of the up-adjustment codes UP_CODE[N:1] is not used (No), the fine-tuning operation may be repeated. In other words, the code generator 120 may repeatedly perform operations S231 to S235.

[0062] In operation S241, the code generator 120 may set the down-adjustment code DN_CODE[N] to "1." If the feedback voltage VFB is greater than the reference voltage VREF in operation S242 (Yes), the value of the down-adjustment code DN_CODE[N] set in operation S241 may remain unchanged at "1." However, if the feedback voltage VFB is less than the reference voltage VREF in operation S241 (No), the code generator 120 may set the down-adjustment code DN_CODE[N] to "0" in operation S243. That is, after adjusting one of the down-adjustment codes DN_CODE[N:1] in operation S241, if the feedback voltage VFB is less than the reference voltage VREF, the code generator 120 may change the value of the adjusted down-adjustment code to a value (e.g., the initial value "0"), that is, the value before the adjustment.

[0063] Since the Nth down-regulation code DN_CODE[N] is set in operations S241 and S243 , the code generator 120 may prepare to set the (N−1)th down-regulation code DN_CODE[N−1] in operation S244 .

[0064] In operation S245, the code generator 120 may determine whether all the down-adjustment codes DN_CODE[N:1] are used (i.e., N = "0"). If it is determined that all the down-adjustment codes DN_CODE[N:1] are used (Yes), the fine-tuning operation may end after the up-adjustment codes UP_CODE[N:1] and the down-adjustment codes DN_CODE[N:1] are stored in the non-volatile memory device 130. If it is determined in operation S245 that at least one of the down-adjustment codes DN_CODE[N:1] is not used (No), the fine-tuning operation may be repeated. In other words, the code generator 120 may repeatedly perform operations S241 to S245.

[0065] Figure 4 The flowchart may refer to a case where the code generator 120 according to an embodiment of the present invention operates according to the minimum fusion algorithm. If the feedback voltage VFB is less than the reference voltage VREF, the code generator 120 may adjust the up-code UP_CODE[N:1] and may maintain the initial value of the down-code DN_CODE[N:1] so that the antifuse corresponding to the down-code DN_CODE[N:1] is not broken. If the feedback voltage VFB is greater than the reference voltage VREF, the code generator 120 may adjust the down-code DN_CODE[N:1] and may maintain the initial value of the up-code UP_CODE[N:1] so that the antifuse corresponding to the up-code UP_CODE[N:1] is not broken. The following will describe the operation according to Figure 4 1 is a timing diagram of the flow chart of the code generator 120.

[0066] Figure 5 It shows Figure 1 The timing diagram of the code generator is shown in Figure 1. Figure 1 and Figure 4 To describe Figure 5 Here, the horizontal axis indicates time. Assume that "N" of each of the up-code UP_CODE[N:1] and the down-code DN_CODE[N:1] is "7". Also, assume that each of the increments of the up-code UP_CODE[N:1] for increasing the feedback voltage VFB is equal to 2 N and similarly, assuming that each of the decrements of the down-regulation code DN_CODE[N:1] for decreasing the feedback voltage VFB is proportional to 2 N Directly proportional.

[0067] From time point T1 to time point T2, the initial voltage level of the feedback voltage VFB is the first voltage level V1. The feedback voltage VFB is lower than the reference voltage VREF. Therefore, the comparison result COMP of the comparator 110 can be high. The code generator 120 can set the MSB up-code UP_CODE[7] corresponding to the most significant bit to "1" (operation S231). The feedback voltage VFB can increase from the first voltage level V1 to the second voltage level V2.

[0068] From time point T2 to time point T3, by adjusting the code generator 120, the feedback voltage VFB can be greater than the reference voltage VREF. Therefore, the comparison result COMP of the comparator 110 can be lower. The code generator 120 can set the previously adjusted up-code UP_CODE[7] to "0" (operation S233) instead of adjusting the down-code DN_CODE[7:1] and can set the next up-code UP_CODE[6] to "1" (operation S234, operation S235 and operation S231). The feedback voltage VFB can be directly reduced from the second voltage level V2 to the third voltage level V3, or can be increased to the third voltage level V3 after being reset to the first voltage level V1.

[0069] From time point T3 to time point T4, the feedback voltage VFB may still be greater than the reference voltage VREF. Therefore, the comparison result COMP of the comparator 110 may be lower. The code generator 120 may set the previously adjusted up-code UP_CODE[7] to "0" (operation S233) instead of adjusting the down-code DN_CODE[6:1] and may set the next up-code UP_CODE[5] to "1" (operations S234, S235, and S231). The feedback voltage VFB may decrease directly from the third voltage level V3 to the fourth voltage level V4 or may increase to the fourth voltage level V4 after being reset to the first voltage level V1.

[0070] From time point T4 to time point T5, by adjusting the code generator 120, the feedback voltage VFB can be lower than the reference voltage VREF. Therefore, the comparison result COMP of the comparator 110 can be higher. The code generator 120 can maintain the previously adjusted up-code UP_CODE[5] at "1" and can set the next up-code UP_CODE[4] to "1" (operation S234, operation S235, and operation S231). The feedback voltage VFB can increase from the fourth voltage level V4 to the fifth voltage level V5.

[0071] From time point T5 to time point T6, by adjusting the code generator 120, the feedback voltage VFB can be greater than the reference voltage VREF. Therefore, the comparison result COMP of the comparator 110 can be lower. The code generator 120 can set the previously adjusted up-code UP_CODE[7] to "0" (operation S233) instead of adjusting the down-code DN_CODE[4:1] and can set the next up-code UP_CODE[3] to "1" (operation S234, operation S235 and operation S231). The feedback voltage VFB can be directly reduced from the fifth voltage level V5 to the sixth voltage level V6, or can be increased to the sixth voltage level V6 after being reset to the fourth voltage level V4.

[0072] From time point T6 to time point T7, by adjusting the code generator 120, the feedback voltage VFB can be lower than the reference voltage VREF. Therefore, the comparison result COMP of the comparator 110 can be higher. The code generator 120 can maintain the previously adjusted up-code UP_CODE[3] at "1" and can set the next up-code UP_CODE[2] to "1" (operation S234, operation S235, and operation S231). The feedback voltage VFB can increase from the sixth voltage level V6 to the seventh voltage level V7.

[0073] From time point T7 to time point T8, by adjusting the code generator 120, the feedback voltage VFB can be greater than the reference voltage VREF. Therefore, the comparison result COMP of the comparator 110 can be lower. The code generator 120 can set the previously adjusted up-code UP_CODE[7] to "0" (operation S233) instead of adjusting the down-code DN_CODE[2:1] and can set the next up-code UP_CODE[1] to "1" (operation S234, operation S235 and operation S231). The feedback voltage VFB can be directly reduced from the seventh voltage level V7 to the reference voltage level, or can be increased to the reference voltage level after being reset to the sixth voltage level V6.

[0074] From the time point T1 to the time point T8, the code generator 120 may adjust only the up-code UP_CODE[7:1]. After the time point T8, the up-code UP_CODE[7:1] is "0010101 b " and down-regulate code DN_CODE[7:1] "0000000 b " can be stored in the non-volatile memory device 130. The three antifuses corresponding to the up-codes UP_CODE[5], UP_CODE[3], and UP_CODE[1] can be Figure 5If the code generator 120 operates according to a minimum fusion algorithm instead of a binary search algorithm, the number of antifuses to be broken can be reduced.

[0075] exist Figures 2 to 5 The initial value of the up-code UP_CODE[N:1] or down-code DN_CODE[N:1] is “0000000 b If the code generator 120 adjusts the up-code UP_CODE[N:1] or the down-code DN_CODE[N:1], the antifuse corresponding to each code having "1" in the up-code UP_CODE[7:1] and the down-code DN_CODE[7:1] may be broken. However, the above values ​​correspond to one example. In another embodiment, the initial value of the up-code UP_CODE[7:1] or the down-code DN_CODE[7:1] may be "1111111 b In this case, the antifuse corresponding to each code having “0” among the up-code UP_CODE[7:1] and the down-code DN_CODE[7:1] may be broken.

[0076] As described above, the code generator 120 may adjust only some of the up-code UP_CODE[N:1] or down-code DN_CODE[N:1] and maintain the other codes at their initial values. If the up-code UP_CODE[N:1] or down-code DN_CODE[N:1] maintains its initial value, the corresponding antifuse may not be broken.

[0077] When the code generator 120 operates according to the minimum-fusion algorithm, the number of antifuses that are broken can be smaller than when the code generator 120 operates according to the binary search algorithm. Therefore, the time required to program the antifuse array can be reduced. Furthermore, if the code generator 120 operates according to the minimum-fusion algorithm, the voltage fine-tuning circuit 100 can perform a fine-tuning operation again even after performing a fine-tuning operation.

[0078] According to an embodiment, if the voltage fine-tuning circuit 100 has previously been used to adjust the feedback voltage VFB by fine-tuning the up-adjustment code UP_CODE[N:1], the voltage fine-tuning circuit 100 can readjust the feedback voltage VFB by using a code not previously used. The previously unused code can be accessed by selecting an unbroken antifuse to adjust the feedback voltage included in the up-adjustment code UP_CODE[N:1] or the down-adjustment code DN_CODE[N:1]. Similarly, if the voltage fine-tuning circuit 100 has previously adjusted the feedback voltage VFB by using the down-adjustment code DN_CODE[N:1], the voltage fine-tuning circuit 100 can readjust the feedback voltage VFB by using any code not previously used. The previously unused code can be accessed by selecting an unbroken antifuse to adjust the feedback voltage included in the up-adjustment code UP_CODE[N:1] or the down-adjustment code DN_CODE[N:1].

[0079] Figure 6 It shows Figure 1 A block diagram of a non-volatile memory device is shown. Figure 6 The nonvolatile memory device 130 may include a plurality of latches 131 , an automatic rupture circuit 132 , and an antifuse array 133 .

[0080] if Figure 1 The operation of the code generator 120 is completed, and the plurality of latches 131 can store the up-code UP_CODE[N:1] and the down-code DN_CODE[N:1]. To this end, the plurality of latches 131 can be from Figure 1 The code generator 120 receives an end-of-conversion (EOC) signal. The code generator 120 may generate the end-of-conversion signal after generating the up-code UP_CODE[N:1] and the down-code DN_CODE[N:1]. The number of latches 131 may be "2N" corresponding to the sum of the number of up-codes UP_CODE[N:1] and the number of down-codes DN_CODE[N:1].

[0081] The automatic rupture circuit 132 may rupture the antifuses of the antifuse array 133 corresponding to the up code UP_CODE[N:1] and the down code DN_CODE[N:1] latched in the plurality of latches 131. Specifically, the automatic rupture circuit 132 may apply a high voltage to the corresponding antifuses.

[0082] The antifuse array 133 may include a plurality of antifuses (not shown) located at the intersection of at least one or more rows (not shown) and at least one or more columns (not shown). The plurality of antifuses may be ruptured by a plurality of trimming codes (i.e., an up-tuning code UP_CODE[N:1] and a down-tuning code DN_CODE[N:1]) to adjust the feedback voltage VFB. The antifuse array 133 may be configured to provide a plurality of antifuses. Figure 1 The switch circuit 140 provides the programmed up-code UP_CODE[N:1] and the programmed down-code DN_CODE[N:1].

[0083] Figure 7 It shows Figure 1 The structure of the voltage generator is shown in FIG. Figure 7 , the voltage generator 150 may include a first resistor R1 , a second resistor R2 , a comparator 151 , a driver 152 , an up-regulating resistor string 153 , and a down-regulating resistor string 154 .

[0084] The first resistor R1 and the second resistor R2 may generate an internal reference voltage INT_VREF. Here, the reference voltage INT_VREF may be calculated by (VDD×(R2 / (R1+R2))). Here, “VDD” refers to a power supply voltage.

[0085] The comparator 151 can receive an internal reference voltage INT_VREF and a node voltage VN. Specifically, the comparator 151 can receive the internal reference voltage INT_VREF through an inverting input terminal and can receive the node voltage VN through a non-inverting input terminal. The comparator 151 can compare the internal reference voltage INT_VREF with the node voltage VN and can output a comparison signal VC. In an embodiment, the comparator 151 can be an operational amplifier, and the comparison signal VC can be an analog signal.

[0086] Driver 152 can supply current to the upward-regulating resistor string 153, the downward-regulating resistor string 154, and a load (not shown) connected to the feedback voltage VFB. The amount of current supplied by driver 152 can be determined by comparison signal VC. In an embodiment, driver 152 can include a p-channel metal oxide semiconductor (PMOS). Driver 152 can stably control the feedback voltage VFB by adjusting the current.

[0087] The up-regulation resistor string 153 may include resistors RUP1 to RUPN connected in series with each other, and the down-regulation resistor string 154 may include resistors RDN1 to RDNN connected in series with each other. The value of the up-regulation resistor string 153 may be determined by the up-regulation code UP_CODE[N:1], and the value of the down-regulation resistor string 154 may be determined by the down-regulation code DN_CODE[N:1].

[0088] refer to Figure 7 The described structure of the voltage generator 150 is only one example. Other structures capable of increasing the feedback voltage VFB in response to the up-code UP_CODE[N:1] and decreasing the feedback voltage VFB in response to the down-code DN_CODE[N:1] may be applied to the present inventive concept.

[0089] Figure 8 is a block diagram illustrating a voltage fine-tuning circuit according to another embodiment of the present inventive concept. Figure 8 The voltage fine-tuning circuit 200 may include a comparator 210 , a code generator 220 , a nonvolatile memory device 230 , a switch circuit 240 , a voltage generator 250 , and an accumulation circuit 260 . Figure 8 The voltage fine-tuning circuit 200 may further include an accumulation circuit 260. If the voltage fine-tuning circuit 200 includes the accumulation circuit 260, the code generator 220 may adjust the up-code UP_CODE[N:1] and the down-code DN_CODE[N:1] based on the comparison result COMP2 of the accumulation circuit 260 instead of the comparison result COMP1 of the comparator 210.

[0090] The accumulation circuit 260 can accumulate the comparison result COMP1 of the comparator 210. Based on the accumulated comparison results, the accumulation circuit 260 can determine whether the feedback voltage VFB is greater than or less than the reference voltage VREF. Without the accumulation circuit 260, the comparator 210 may output an abnormal comparison result COMP1 due to the following: noise that may be caused by changes in the operating voltage, inconsistent power consumption of peripheral circuits, etc. If the code generator 220 operates based on the abnormal comparison result COMP1, the feedback voltage VFB may not be accurately set to the reference voltage VREF. The accumulation circuit 260 can prevent this problem. The operation of the voltage fine-tuning circuit 200 will be described in more detail below.

[0091] Figure 9 It shows Figure 8 The operation timing diagram of the accumulation circuit is shown in FIG. Figure 9 In FIG, the horizontal axis indicates time. Assume that the comparator 210 performs the comparison operation at the rising edge of the clock CK. In another embodiment, the comparator 210 can perform the comparison operation at the falling edge of the clock CK.

[0092] Because the feedback voltage VFB is less than the reference voltage VREF at time points T1, T3, and T4, the comparator 210 may output a comparison result COMP1 corresponding to a high level. In contrast, at time point T2, the comparator 210 may output an abnormal comparison result COMP1 due to noise.

[0093] The accumulation circuit 260 may not immediately transmit the comparison result COMP1 of the comparator 210 to the code generator 220, but may instead accumulate the comparison result COMP1. In an embodiment, for example, after checking (i.e., confirming) that the comparison result COMP1 has the same value four or more times, the accumulation circuit 260 may change the comparison result COMP2 of the accumulation circuit 260. Therefore, an abnormal comparison result COMP1 generated due to noise may not be transmitted to the code generator 220 by the accumulation circuit 260.

[0094] Figure 10 1 is a block diagram illustrating an integrated circuit according to an embodiment of the present invention. The integrated circuit 1000 may include a comparator 1100, a code generator 1200, a nonvolatile memory device 1300, switch circuits 1410 to 1430, voltage generators 1510 to 1530, an accumulation circuit 1600, a switch circuit 1700, an input pad 1810, an output pad 1820, and a monitoring circuit 1900. Here, the comparator 1100, the code generator 1200, the nonvolatile memory device 1300, the switch circuits 1410 to 1430, the voltage generators 1510 to 1530, and the accumulation circuit 1600 may perform operations with reference to a reference signal. Figure 1 and Figure 8 The functions described are basically the same functions.

[0095] The integrated circuit 1000 may be various memory devices (e.g., dynamic random access memory (DRAM), static random access memory (SRAM), NAND flash memory, NOR flash memory, MRAM, PRAM, RRAM, FRAM, TRAM, solid-state drive (SSD), hard disk drive (HDD), etc.), a central processing unit (CPU), a graphics processing unit (GPU), an application-specific integrated circuit (ASIC), a system on chip (SoC), etc. In other words, the integrated circuit 1000 may generate at least one internal voltage by using a driving voltage. In the embodiment, Figure 10 In the example, the integrated circuit 1000 generates three internal voltages VINTA, VINTB and VINTC. Figure 8 In addition to the voltage fine-tuning circuit 200, the integrated circuit 1000 may further include switch circuits 1420 and 1430, voltage generators 1520 and 1530, and a switch circuit 1700. Figure 10 , the number of internal voltages, the number of switching circuits 1410 to 1430, and the number of voltage generators 1510 to 1530 are merely examples.

[0096] In an embodiment, the switch circuit 1700 can select the internal voltage VINTA as the feedback voltage VFB. If the operation of fine-tuning the selected internal voltage VINTA is completed, the increase code UP_CODE[N:1] and the decrease code DN_CODE[N:1] for adjusting the internal voltage VINTA can be stored in the non-volatile memory device 1300. Thereafter, the switch circuit 1700 can select the selected internal voltage VINTB as the feedback voltage VFB. If the operation of fine-tuning the internal voltage VINTB is completed, the increase code UP_CODE[N:1] and the decrease code DN_CODE[N:1] for adjusting the internal voltage VINTB can be stored in the non-volatile memory device 1300. The integrated circuit 1000 can fine-tune the internal voltage VINTC in the same manner.

[0097] Input pad 1810 may receive a reference voltage VREF. Reference voltage VREF may have different values ​​depending on internal voltages VINTA, VINTB, and VINTC.

[0098] Output pad 1820 may be used to output reference voltage VREF or internal voltages VINTA, VINTB, and VINTC in integrated circuit 1000 to the outside of integrated circuit 1000. Monitoring circuit 1900 may select any one of reference voltage VREF or internal voltages VINTA, VINTB, and VINTC.

[0099] In an embodiment, an external test device (not shown) of integrated circuit 1000 may receive internal voltages VINTA, VINTB, and VINTC or reference voltage VREF from output pad 1820. The test device may monitor whether the level of reference voltage VREF applied to integrated circuit 1000 is appropriate or whether the regulated internal voltages VINTA, VINTB, and VINTC are appropriate (monitoring).

[0100] Figure 11 FIG is a diagram illustrating a flow chart associated with the operation of a voltage fine-tuning circuit according to an embodiment of the inventive concept. Figure 8 describe Figure 11 .

[0101] In operation S310, an offset cancellation operation of the comparator 210 may be performed. If the offset cancellation operation is not performed, an error may occur during the operation of the comparator 210.

[0102] In operation S320 , the comparator 210 may compare the feedback voltage VFB with the reference voltage VREF.

[0103] In operation S330, the accumulation circuit 260 may accumulate the comparison result COMP1 of the comparator 210. In operation S330, abnormal comparison results of the comparator 210 caused by noise may be removed. The accumulation circuit 260 may determine whether the feedback voltage VFB is greater than or less than the reference voltage VREF based on the accumulated comparison results of the comparator 210.

[0104] In operation S340, the code generator 220 may adjust the up-adjustment code UP_CODE[N:1] and the down-adjustment code DN_CODE[N:1]. According to an embodiment of the present invention, the code generator 220 may operate according to a minimum fusion algorithm. In this case, if the up-adjustment code UP_CODE[N:1] is adjusted, the initial value of the down-adjustment code DN_CODE[N:1] may be maintained; conversely, if the down-adjustment code DN_CODE[N:1] is adjusted, the initial value of the up-adjustment code DN_CODE[N:1] may be maintained. Here, in operation S350, the antifuse corresponding to the up-adjustment code UP_CODE[N:1] maintained at the initial value or the antifuse corresponding to the down-adjustment code DN_CODE[N:1] maintained at the initial value may not be broken.

[0105] In operation S350, the nonvolatile memory device 230 may store an up-code UP_CODE[N:1] and a down-code DN_CODE[N:1]. Specifically, the nonvolatile memory device 230 may program the antifuse array according to the up-code UP_CODE[N:1] and the down-code DN_CODE[N:1]. Specifically, if the antifuse corresponding to the up-code UP_CODE[N:1] is broken when the feedback voltage VFB is less than the reference voltage VREF, the antifuse corresponding to the down-code DN_CODE[N:1] may not be broken. Conversely, if the antifuse corresponding to the down-code DN_CODE[N:1] is broken when the feedback voltage VFB is greater than the reference voltage VREF, the antifuse corresponding to the up-code UP_CODE[N:1] may not be broken.

[0106] Figure 12 FIG is a diagram showing a flowchart associated with the operation of the voltage trimming circuit after the trimming operation. Figure 8 describe Figure 12 .

[0107] In operation S410 , trimming information (ie, an up-tuning code UP_CODE[N:1] and a down-tuning code DN_CODE[N:1]) may be read from an antifuse array.

[0108] In operation S420 , the switch circuit 240 may transfer the up code UP_CODE[N:1] and the down code DN_CODE[N:1] read from the antifuse array to the voltage generator 250 .

[0109] In operation S430 , the voltage generator 250 may generate a feedback voltage VFB according to the transmitted up-code UP_CODE[N: 1] and the transmitted down-code DN_CODE[N: 1].

[0110] A voltage fine-tuning circuit and an operating method thereof according to an embodiment of the inventive concept can accurately adjust a feedback voltage to a reference voltage while using a small number of antifuses.

[0111] Integrated circuits according to embodiments of the inventive concept can shorten test time by reducing the time required to fine-tune internal voltages.

[0112] Although the present invention has been described with reference to the embodiments, it is obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the present invention. Therefore, it should be understood that the above embodiments are not limitative, but illustrative.

Claims

1. A voltage fine-tuning circuit, comprising: a comparator configured to compare a reference voltage with a feedback voltage; a code generator configured to generate a plurality of fine-tuning codes for fine-tuning the feedback voltage based on a comparison result of the comparator, wherein when the comparison result indicates that the feedback voltage is to be increased, the code generator adjusts an up-adjusting code among the plurality of fine-tuning codes to increase the feedback voltage and maintains a down-adjusting code among the plurality of fine-tuning codes at an initial value, and when the comparison result indicates that the feedback voltage is to be decreased, the code generator adjusts the down-adjusting code among the plurality of fine-tuning codes and maintains the up-adjusting code at the initial value; a non-volatile memory device configured to store a plurality of final fine-tuning codes adjusted by the code generator; a switching circuit configured to select the plurality of trim codes during a trim mode and to select the plurality of final trim codes after the trim mode; and a voltage generator configured to generate the feedback voltage based on the plurality of trim codes selected by the switching circuit, wherein, after adjusting one of the upward adjustment codes, the code generator changes the one of the upward adjustment codes to a value before the adjustment when the feedback voltage is greater than the reference voltage; wherein the increment of the feedback voltage for each adjustment of the increase code is different from one another, The increment is equal to 2 N proportional, and The code generator adjusts the upward adjustment code in order from the largest increment to the smallest increment.

2. The voltage fine-tuning circuit according to claim 1, wherein: The code generator is configured to, after adjusting one of the up-adjustment codes, When the comparison result continues to indicate that the feedback voltage is to be increased, adjusting the subsequent increase code, and When the comparison result indicates that the feedback voltage is to be decreased, the subsequent increase code is not adjusted.

3. The voltage fine-tuning circuit according to claim 1, wherein: The amount of decrement of the feedback voltage for each adjustment of the down-regulation code is different from each other, Wherein, the amount of the reduction is equal to 2 N proportional, and The code generator adjusts the down-regulation code in order from the largest decrement to the smallest decrement.

4. The voltage fine-tuning circuit according to claim 3, wherein: The code generator is configured to, after adjusting one of the down-regulated codes, When the comparison result continues to indicate that the feedback voltage is to be reduced, adjusting the subsequent downward adjustment code, and When the comparison result indicates that the feedback voltage is to be increased, the subsequent downward adjustment code is not adjusted.

5. The voltage fine-tuning circuit according to claim 1, wherein: The nonvolatile memory device includes an antifuse array including a plurality of antifuses, and the plurality of final trimming codes are programmed into the antifuse array.

6. The voltage fine-tuning circuit according to claim 5, wherein: When the feedback voltage is greater than the reference voltage, the antifuse corresponding to the upward code maintained at the initial value is not broken, and When the feedback voltage is less than the reference voltage, the antifuse corresponding to the trimmed-down code maintained at the initial value is not ruptured.

7. The voltage fine-tuning circuit according to claim 1, wherein: The comparator performs offset cancellation before comparing the reference voltage to the feedback voltage.

8. The voltage fine-tuning circuit according to claim 1 , further comprising: an accumulation circuit configured to accumulate comparison results of the comparator and determine whether the feedback voltage is greater than or less than the reference voltage based on the accumulated comparison results, The code generator adjusts the plurality of fine-tuning codes based on a comparison result of the accumulation circuit.

9. A method for operating a voltage fine-tuning circuit, the method comprising: By using a comparator to compare the reference voltage with the feedback voltage; adjusting an upward adjustment code to increase the feedback voltage, and adjusting a downward adjustment code to decrease the feedback voltage; as well as After adjusting the up-code and the down-code, programming the up-code and the down-code into an antifuse array including a plurality of antifuses, The adjustments include: When the comparison result indicates that the feedback voltage is to be increased, the value of the up-regulation code is set to increase the feedback voltage, and when the comparison result indicates that the feedback voltage is to be decreased, the value of the down-regulation code is set to decrease the feedback voltage, wherein, after adjusting one of the upward adjustment codes, when the feedback voltage is greater than the reference voltage, the one of the upward adjustment codes is changed to a value before the adjustment, wherein the increment of the feedback voltage for each adjustment of the increase code is different from one another, The increment is equal to 2 N proportional, and The code generator adjusts the upward adjustment code in order from the largest increment to the smallest increment.

10. The method according to claim 9, wherein: The comparison includes: performing offset cancellation of the comparator; accumulating comparison results of the comparator; and Based on the accumulated comparison results, it is determined whether the feedback voltage is greater than or less than the reference voltage.

11. The method according to claim 9, The code generator is further configured to When the comparison result continues to indicate that the feedback voltage is to be increased, adjusting the subsequent increase code, and When the comparison result indicates that the feedback voltage is to be decreased, the subsequent increase code is not adjusted.

12. The method according to claim 9, wherein The amount of decrement of the feedback voltage for each adjustment of the down-regulation code is different from each other, Wherein, the amount of the reduction is equal to 2 N proportional, and The code generator adjusts the down-regulation code in the order from the largest decrement to the smallest decrement, and the code generator is further configured to When the comparison result continues to indicate that the feedback voltage is to be reduced, adjusting the subsequent downward adjustment code, and When the comparison result indicates that the feedback voltage is to be increased, the subsequent downward adjustment code is not adjusted.

13. The method according to claim 9, wherein: The programming includes: latching the upward adjustment code and the downward adjustment code; and Based on the values ​​of the latched up code and the latched down code, antifuses corresponding to the latched up code and the latched down code are ruptured.

14. The method according to claim 9, further comprising: The feedback voltage is generated according to an up code and a down code stored in the antifuse array.

15. An integrated circuit comprising: a first switching circuit configured to select an internal voltage from a plurality of internal voltages of the integrated circuit; a comparator configured to compare the selected internal voltage with a reference voltage; a code generator configured to adjust a plurality of trimming codes for trimming each of the plurality of internal voltages based on a comparison result of the comparator; a non-volatile memory device configured to store a plurality of final fine-tuning codes adjusted by the code generator; a second switching circuit configured to select the plurality of trimming codes during a trimming mode and to select the plurality of final trimming codes after the trimming mode; as well as a plurality of voltage generators configured to generate the plurality of internal voltages based on a plurality of trimming codes selected by the second switching circuit, wherein each of the plurality of fine-tuning codes includes an up-tuning code for increasing the plurality of internal voltages and a down-tuning code for decreasing the plurality of internal voltages; When the code generator adjusts any one of the upward adjustment code and the downward adjustment code, the code generator maintains the other of the upward adjustment code and the downward adjustment code at an initial value. The code generator adjusts an upward adjustment code in a fine-tuning code for fine-tuning the selected internal voltage when the selected internal voltage is less than the reference voltage, and adjusts a downward adjustment code in the fine-tuning code for fine-tuning the selected internal voltage when the selected internal voltage is greater than the reference voltage. wherein, after adjusting one of the upward adjustment codes, the code generator changes the one of the upward adjustment codes to a value before the adjustment when the selected internal voltage is greater than the reference voltage, wherein the amount of the internal voltage increment for each adjustment of the up-code is different from one another, The increment is equal to 2 N proportional, and The code generator adjusts the upward adjustment code in order from the largest increment to the smallest increment.

16. The integrated circuit of claim 15, wherein: After adjusting one of the down-regulation codes, the code generator changes the one of the down-regulation codes to a value before the adjustment when the selected internal voltage is less than the reference voltage.

17. The integrated circuit of claim 15, wherein: The nonvolatile memory device includes an antifuse array including a plurality of antifuses, and the antifuse array is programmed according to the plurality of final trimming codes.

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