UVM verification method based on digital down converter and synchronization method thereof
By obtaining the output frequency division clock in the digital downconverter and establishing the filter phase relationship, the phase error problem caused by the uncertainty of filter decimation in UVM verification is solved, and the synchronization of data input and verification efficiency are improved.
Patent Information
- Application Number
- CN202510683653.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-26
- Publication Date
- 2025-08-29
AI Technical Summary
In UVM verification of traditional digital downconverters, the uncertainty of filter decimation leads to phase errors, requiring manual adjustment of the phase of the reference model, which is inefficient and poor portability.
By acquiring the input data and clocking in the circuit to be tested, an output frequency division clock is obtained, and the data input node is delayed based on the clock, and the phase relationship between filters at each stage is established to realize the synchronization of the input data.
The data input synchronization at any time is realized, which improves the efficiency and portability of UVM verification, and solves the problem of manually adjusting phase in traditional methods.
Smart Images
Figure CN120562348A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of circuit function verification, and in particular to a UVM verification method based on a digital down converter and a synchronization method thereof. Background Art
[0002] In the UVM (Universal Verification Methodology) verification of traditional digital down-converter (Digital Downconverter, DDC) module, due to the uncertainty of filter extraction, under the UVM environment of DDC module, reference model (Reference Model, RM) generally adopts manual adjustment phase relationship, thereby reaches the purpose of aligning with circuit under test (Design Under Test, DUT). In the UVM verification process, under simulation environment, because the time point of simulation data extraction of circuit under test is different, phase error is caused between circuit under test and reference model; The data phase of reference model can be manually adjusted directly on UVM platform according to circuit under test, but each data extraction time point changes like this, and the data phase of reference model needs to be adjusted, making the efficiency of UVM verification low. Moreover, in actual applications, the data input time node of circuit under test and the data input time point under simulation environment have different situations. At present, after this situation occurs, the phase of reference model can only be readjusted in actual applications, and portability is poor.
[0003] Therefore, how to provide a technical solution for synchronizing and transplanting the input data of DUM verification is a technical problem that urgently needs to be solved. Summary of the Invention
[0004] In view of the above-mentioned shortcomings of the prior art, the present invention provides a technical solution for data input synchronization based on UVM verification of a digital down converter to solve at least one of the above-mentioned technical problems.
[0005] In order to achieve the above-mentioned objectives and other related objectives, the technical solutions provided in this application are as follows.
[0006] According to a first aspect of an embodiment of the present application, a UVM verification synchronization method based on a digital down converter is provided, wherein the UVM verification verifies the function of the circuit under test according to a reference model, and the synchronization method includes:
[0007] Get input data;
[0008] Inputting the input data into the last filter stage in the circuit under test for clock sampling to obtain an output frequency-divided clock of the circuit under test, wherein the output frequency-divided clock is the slowest clock signal in the circuit under test;
[0009] The data input node of the circuit to be tested is delayed based on the output frequency-divided clock, and a phase relationship between filters of various levels in the circuit to be tested is established to achieve synchronization of input data during the UVM verification.
[0010] In one embodiment of the present invention, the input data is input into the last filter stage in the circuit under test for clock sampling to obtain the output frequency-divided clock of the circuit under test; including: inputting the input data into the last filter stage in the circuit under test for filtering processing to obtain the last intermediate data; and extracting the clock signal from the last intermediate data to obtain the output frequency-divided clock.
[0011] In one embodiment of the present invention, the data input node of the circuit under test is delayed based on the output divided clock, and the phase relationship of the filters at each level in the circuit under test is established, including: taking a certain node of the output divided clock as the adjustment starting point; performing clock delay on the data input node of the circuit under test based on the adjustment starting point to determine the data starting node; and determining the phase relationship according to the data starting node and the input data.
[0012] In one embodiment of the present invention, a clock delay is performed on the data input node of the circuit under test based on the adjustment starting point to determine the data starting node, including: obtaining the input initial clock of the circuit under test; combining the input node of the input data with the input initial clock to obtain the data input node; determining a time delay interval based on the clock period of the input initial clock and the adjustment starting point; and delaying the data input node by the time delay interval to obtain the data starting node.
[0013] In one embodiment of the present invention, the phase relationship is determined based on the data starting node and the input data, including: at the data starting node, the input data is input into the filters of each stage in the circuit to be tested in sequence to obtain N intermediate data; the clock signals of the N intermediate data are extracted to obtain N clock signals; and the phase relationship between the filters of each stage is determined based on the N clock signals; wherein N is an integer, and N is greater than or equal to 2.
[0014] In an embodiment of the present invention, the synchronization method further includes: adjusting a data start node in the reference model based on the phase relationship.
[0015] According to a second aspect of an embodiment of the present application, a UVM verification method based on a digital down converter is provided, including:
[0016] Get verification data;
[0017] Inputting the verification data into the circuit to be tested for data processing to obtain test data;
[0018] Inputting the verification data into a reference model for data processing to obtain reference data;
[0019] Synchronizing the input data of the circuit under test based on the UVM verification synchronization method based on the digital down converter as described above;
[0020] A UVM verification result is determined according to the test data and the reference data.
[0021] In one embodiment of the present invention, determining a UVM verification result according to the test data and the reference data includes: when the test data is equal to the reference data, determining that the UVM verification result is that the function of the circuit to be tested satisfies a preset circuit function; when the test data is not equal to the reference data, determining that the UVM verification result is that the function of the circuit to be tested does not satisfy the preset circuit function.
[0022] In one embodiment of the present invention, the verification method further includes: when performing UVM verification on other circuits to be tested with the same function, inputting the verification data into the corresponding circuit to be tested and the reference model respectively to obtain corresponding test data and reference data to achieve UVM verification.
[0023] The present application provides a UVM verification method based on a digital down-converter and a synchronization method thereof. The UVM verification synchronization method comprises: obtaining input data, inputting the input data into the last filter of the circuit under test for clock sampling, and obtaining an output frequency-divided clock in the circuit under test; delaying the data input node of the circuit under test based on the output frequency-divided clock, and establishing a phase relationship between the filters of each level in the circuit under test, thereby achieving synchronization of the input data during UVM verification. The synchronization method provided by the present application is based on the slowest frequency-divided time inside the circuit under test, and the data input node of the circuit under test is clocked to the fastest clock to achieve phase synchronization of the input data. This not only retains the advantages of traditional circuits, but also solves the problem that the traditional circuit needs to manually adjust the phase when inputting data at different times. This ensures that the UVM data comparison of data input at any time is normal, effectively improving the UVM verification efficiency of the DDC circuit.
[0024] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present invention, and together with the specification, are used to explain the principles of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and it is clear that a person skilled in the art can derive other drawings based on these drawings without inventive effort. In the drawings:
[0026] Figure 1 is a schematic diagram of a three-stage half-band filter shown in an exemplary embodiment of the present invention;
[0027] Figure 2 1. It is a schematic diagram of phase adjustment of a three-stage half-band filter in a circuit to be tested in a UVM verification environment shown in an exemplary embodiment of the present invention;
[0028] Figure 3 1 is a phase diagram of a three-stage half-band filter in actual circuit operation, shown in an exemplary embodiment of the present invention;
[0029] Figure 4 1 is a flow chart of a UVM verification synchronization method based on a digital down converter shown in an exemplary embodiment of the present invention;
[0030] Figure 5 is a schematic diagram of time synchronization of a three-stage half-band filter in a circuit under test, shown in an exemplary embodiment of the present invention;
[0031] Figure 6 is a schematic diagram showing time synchronization of a secondary filter in a circuit under test according to an exemplary embodiment of the present invention;
[0032] Figure 7 The figure is a flow chart of a UVM verification method based on a digital down converter according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION
[0033] The following describes the embodiments of the present invention with reference to the accompanying drawings and preferred embodiments. Those skilled in the art will readily appreciate the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the various details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are intended only to illustrate the present invention and are not intended to limit the scope of protection of the present invention.
[0034] It should be noted that the illustrations provided in the following embodiments are merely schematic illustrations of the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.
[0035] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present invention. However, it will be apparent to those skilled in the art that the embodiments of the present invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring the embodiments of the present invention.
[0036] In integrated circuit (IC) design, UVM (Universal Verification Methodology) is a standardized verification framework based on SystemVerilog, specifically designed to verify the correctness of digital circuit designs. It achieves comprehensive verification of design functionality, timing, and performance by building a highly structured testbench.
[0037] In UVM (Universal Verification Methodology) verification of traditional digital down-conversion (Digital Downconverter, DDC) module, due to filter extraction there is uncertainty, under the UVM environment of DDC module, reference model (Reference Model, RM) generally takes manual adjustment phase relationship, thereby reaches the purpose of aligning with circuit under test (Design Under Test, DUT).In UVM verification process, under simulation environment, because of the time point that circuit under test simulation data is extracted different, thereby cause phase error to exist between circuit under test and reference model, can directly on UVM platform, the data phase of reference model is manually adjusted according to circuit under test, but each data extraction time point changes like this, all need to adjust the data phase of reference model, make the efficiency of UVM verification low.
[0038] As shown in Figure 1, if the filter in the digital down converter is a three-stage half-band filter, where Clk_HB1_out and Clk_HB2_in are at the same frequency and phase, and Clk_HB2_out and Clk_HB3_in are at the same frequency and phase, in the traditional circuit, when performing UVM verification, it is first necessary to adjust the extraction phase of the reference model in the UVM environment according to the phase extracted by HB1 in the circuit to be tested, such as Figure 2 shown.
[0039] like Figure 3 As shown, considering the actual application, Figure 1 The input data Data_in is inconsistent with the simulation environment input time, but the phase of the traditional UVM verification circuit is extracted and adjusted according to the circuit to be tested in the simulation environment, so the phase needs to be readjusted in actual applications, which has poor portability.
[0040] To solve the above problems, Figure 4 As shown, the present application provides a UVM verification synchronization method based on a digital down converter. UVM verification verifies the function of the circuit to be tested according to a reference model. The synchronization method includes at least steps S410 to S430:
[0041] S410, obtaining input data;
[0042] S420, inputting the input data into the last filter stage in the circuit under test for clock sampling to obtain an output frequency-divided clock of the circuit under test, wherein the output frequency-divided clock is the slowest clock signal in the circuit under test;
[0043] S430: Delay processing is performed on the data input node of the circuit under test based on the output frequency-divided clock, and a phase relationship between filters of various levels in the circuit under test is established to achieve synchronization of input data during UVM verification.
[0044] It should be noted that the process of phase synchronization of the input data of the circuit under test includes: first inputting the input data into the last-stage filter of the circuit under test, performing clock sampling, and then receiving the data output from the last stage through the first-stage filter of the circuit under test to achieve delay of the input data and complete synchronization of the input data.
[0045] Specifically, in step S420, inputting the input data into the last filter of the circuit under test for clock sampling to obtain the output frequency-divided clock of the circuit under test includes: inputting the input data into the last filter of the circuit under test for filtering to obtain the last intermediate data; extracting the clock signal of the last intermediate data to obtain the output frequency-divided clock. Specifically, Figure 1 As shown, if the filter in the circuit to be tested is a three-stage half-band filter design, the test data is input into the third-stage filter HB_3 of the three-stage half-band filter to obtain the third-stage intermediate data, that is, the data output by the third-stage filter HB_3. The change pattern of the output data of the third-stage filter HB_3 is marked, and the time signal of the third-stage filter HB_3 is extracted according to the marking pattern to obtain the output divided clock.
[0046] More specifically, the method delays the data input nodes of the circuit under test based on the output frequency-divided clock and establishes the phase relationship of the multi-stage filter in the circuit under test, including: using a node of the output frequency-divided clock as the adjustment starting point; performing clock delay on the data input nodes of the circuit under test based on the adjustment starting point to determine the data starting node; and determining the phase relationship based on the data starting node and the input data. Specifically, Figure 5 As shown, Clk_HB3_out is the output frequency-divided clock of the output data of the third-stage filter, that is, Clk_HB3_out is the output frequency-divided clock corresponding to the longest period. For example, the first rising edge a of Clk_HB3_out is used as the adjustment starting point. With the adjustment starting point as the reference point, the clock input node of the first-stage filter HB_1 in the circuit under test is delayed, thereby determining the data starting node of the first-stage filter HB_1, as shown in FIG. Figure 5 As shown, the input data is input into a three-stage half-band filter to obtain the phase relationship of the input clock between each stage of the filter.
[0047] In more detail, clock delay is performed on the data input node of the circuit under test based on the adjustment starting point to determine the data starting node, including: obtaining the input initial clock of the circuit under test; combining the input node of the input data with the input initial clock to obtain the data input node; determining the time delay interval according to the clock period of the input initial clock and the adjustment starting point; delaying the data input node by the time delay interval to obtain the data starting node. Specifically, Figure 6 As shown, if the circuit under test is a two-stage half-band filter design, CLK_out is the output frequency-divided clock of the second-stage filter, and the input initial clock CLK_in of the circuit under test is obtained. CLK_in is the input clock signal of the first-stage filter, as shown in Figure 6 As shown, if the input data is data_syn (data1, data2, data3, data4), the input data changes to Data (Data1, Data2, Data3, Data4) after being processed by the input initial clock clk_in for two cycles. The input point of the input data is taken as the starting point. At time t1, the data Data is aligned with the input initial clock to obtain the data input node of the first-stage filter. The output clock CLK_out corresponding to time t1 is determined as the adjustment starting point. The time delay interval is determined according to the adjustment starting point and the input initial clock CLK_in. The time delay interval is two cycles of the input initial clock CLK_in. After two cycles, the data starting node is obtained at time t2.
[0048] It should be emphasized that after determining the adjustment starting point based on the output frequency-divided clock of the circuit under test, when determining the time delay interval based on the adjustment starting point and the input initial clock of the circuit under test, the time between the adjustment starting point and a rising edge or falling edge after the input initial clock of the circuit under test can be used as the time delay interval. Figure 5 As shown, the time delay interval can be the time interval between the adjustment start point and the first rising edge of the input initial clock of the circuit under test, such as Figure 6 As shown, if point a is the adjustment starting point, the time delay interval can be two cycles of the input initial clock CLK_in.
[0049] Specifically, determining the phase relationship based on the data starting node and the input data includes: at the data starting node, sequentially inputting the input data into filters of various levels in the circuit to be tested to obtain N intermediate data; extracting clock signals of the N intermediate data to obtain N clock signals; and determining the phase relationship between filters of various levels based on the N clock signals. Specifically, Figure 5 As shown, the time node b of the input initial clock Clk_HB1_in of the first-stage filter of the circuit to be tested is used as the data starting node, and the input data is sequentially input into the filter circuits of each stage in the circuit to be tested, as shown in FIG. Figure 5 As shown, the data flow direction is b→c→d, and the intermediate input data of each level of filter in the test circuit is obtained. According to the data sampling conditions of the multiple intermediate input data, the clock signals of N intermediate input data are extracted to obtain multiple clock signals. Then, according to the number of levels and clock cycles between the multiple clock signals, the phase relationship between the various levels of filters in the circuit under test is determined.
[0050] In detail, the synchronization method further includes: adjusting the data starting node in the reference model based on the phase relationship, so that the data input phase of the circuit to be tested is always consistent with the data input phase of the reference model.
[0051] In a second aspect of the present application, the present application further provides a UVM verification method based on a digital down converter, comprising:
[0052] S710, obtaining verification data;
[0053] S720, inputting the verification data into the circuit to be tested for data processing to obtain test data;
[0054] S730, inputting the verification data into the reference model for data processing to obtain reference data;
[0055] S740, adjusting the phase of the circuit to be tested based on the UVM verification synchronization method based on the digital down converter as described above;
[0056] S750: Determine a UVM verification result according to the test data and the reference data.
[0057] In detail, determining the UVM verification result according to the test data and the reference data includes: when the test data is equal to the reference data, determining that the UVM verification result of the circuit to be tested is that the function of the circuit to be tested meets the preset circuit function; when the test data is not equal to the reference data, determining that the UVM verification result of the circuit to be tested is that the function of the circuit to be tested does not meet the preset circuit function.
[0058] In detail, the verification method also includes: when replacing other circuits to be tested with the same function for UVM verification, inputting test data into the circuit to be tested to obtain test data, inputting the data to be tested into a reference model to obtain reference data, so as to achieve UVM verification without having to adjust the phase relationship of the reference model multiple times.
[0059] The present application provides a UVM verification method based on a digital down-converter and a synchronization method thereof. The UVM verification synchronization method comprises: obtaining input data, inputting the input data into the last filter of the circuit under test for clock sampling, and obtaining an output frequency-divided clock in the circuit under test; delaying the data input node of the circuit under test based on the output frequency-divided clock, and establishing a phase relationship between the filters of each level in the circuit under test, thereby achieving synchronization of the input data during UVM verification. The synchronization method provided by the present application is based on the slowest frequency-divided time inside the circuit under test, and the data input node of the circuit under test is clocked to the fastest clock to achieve phase synchronization of the input data. This method not only retains the advantages of traditional circuits, but also solves the problem that the traditional circuit needs to manually adjust the phase when inputting data at different times. This method ensures that the UVM data input at any time is normal and can be transplanted between the simulation environment and the actual circuit, with high reliability.
[0060] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, any equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.
Claims
1. A UVM verification synchronization method based on a digital down converter, characterized in that: The UVM verification is to verify the function of the circuit to be tested according to the reference model, and the synchronization method includes: Get input data; Inputting the input data into the last filter stage in the circuit under test for clock sampling to obtain an output frequency-divided clock of the circuit under test, wherein the output frequency-divided clock is the slowest clock signal in the circuit under test; The data input node of the circuit to be tested is delayed based on the output frequency-divided clock, and a phase relationship between filters of various levels in the circuit to be tested is established to achieve synchronization of input data during the UVM verification.
2. The UVM verification synchronization method based on a digital down converter according to claim 1, wherein Inputting the input data into the last filter stage of the circuit under test for clock sampling to obtain the output frequency-divided clock of the circuit under test; comprising: Inputting the input data into the last filter in the circuit to be tested for filtering to obtain the last intermediate data; A clock signal is extracted from the intermediate data of the last stage to obtain the output frequency-divided clock.
3. The UVM verification synchronization method based on digital down converter according to claim 2, wherein Delaying the data input node of the circuit under test based on the output frequency-divided clock and establishing the phase relationship of filters at various levels in the circuit under test includes: Taking a certain node of the output frequency-divided clock as a regulation starting point; Performing clock delay on the data input node of the circuit under test based on the adjustment starting point to determine the data starting node; The phase relationship is determined according to the data start node and the input data.
4. The UVM verification synchronization method based on a digital down converter according to claim 3, wherein Performing clock delay on a data input node of the circuit under test based on the adjustment starting point to determine a data starting node, comprising: Obtaining an initial input clock of the circuit under test; Combining the input node of the input data with the input initial clock to obtain a data input node; determining a time delay interval according to a clock cycle of the input initial clock and the adjustment starting point; The data input node is delayed by the time delay interval to obtain a data start node.
5. The UVM verification synchronization method based on digital down converter according to claim 3, wherein Determining the phase relationship according to the data starting node and the input data includes: At the data starting node, the input data is sequentially input into filters of various levels in the circuit to be tested to obtain N intermediate data; Extracting clock signals of the N intermediate data to obtain N clock signals; Determine the phase relationship between the filters at each level according to the N clock signals; Wherein, N is an integer greater than or equal to 2.
6. The UVM verification synchronization method based on a digital down converter according to claim 1, wherein The synchronization method further includes adjusting a data start node in the reference model based on the phase relationship.
7. A UVM verification method based on digital down converter, characterized in that, include; Get verification data; Inputting the verification data into the circuit to be tested for data processing to obtain test data; Inputting the verification data into a reference model for data processing to obtain reference data; Synchronizing the input data of the circuit under test based on the UVM verification synchronization method based on the digital down converter according to claims 1-6; A UVM verification result is determined according to the test data and the reference data.
8. The UVM verification method based on a digital down converter according to claim 7, wherein Determining a UVM verification result according to the test data and the reference data includes: When the test data is equal to the reference data, determining that the UVM verification result is that the function of the circuit to be tested meets a preset circuit function; When the test data is not equal to the reference data, it is determined that the UVM verification result is that the function of the circuit to be tested does not meet the preset circuit function.
9. The UVM verification method based on a digital down converter according to claim 7, wherein The verification method further comprises: When UVM verification is performed on other circuits to be tested with the same function, the verification data are respectively input into the corresponding circuit to be tested and the reference model to obtain corresponding test data and reference data to achieve UVM verification.