Gated clock automatic verification method, electronic device, and medium

Abstract

The application relates to the technical field of chip verification, in particular to a gated clock automatic verification method, electronic equipment and a medium, which comprises the following steps: S1, acquiring gated clock path information G corresponding to a to-be-tested chip design n , G n is path information corresponding to an n-th gated clock in the to-be-tested chip design, G n is generated by splicing G1 n , G2 n and G3 n ; S2, generating a corresponding gated clock signal value reading function A n based on each G n ; S3, acquiring a gated clock actual measurement value B n of G n by calling A n in a simulation process of the to-be-tested chip design; S4, acquiring a prediction value corresponding to each gated clock, comparing B n with the prediction value corresponding to the n-th gated clock, if all B n are consistent with the prediction value corresponding to the n-th gated clock, the verification is passed, otherwise, generating prompt information based on the gated clocks with inconsistent actual measurement values and prediction values. The application improves the verification efficiency of the gated clock.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip verification technical field, and particularly relates to a clock gating automatic verification method, an electronic device and a medium. BACKGROUND

[0002] Clock gating technology is a traditional dynamic low-power technology, which is widely used in the design of digital integrated circuits, thereby significantly reducing the power consumption of chips. When verifying the clock gating, a clock gating checker is usually added to check whether the related configuration of the clock gating meets the expectation; the conventional configuration step of the clock gating checker is to traverse all clock gating units, and manually write the clock gating checker one by one. However, for a complex chip system, the chip IP (Intellectual Property) is various, and the clock gating is manually written one by one, which is time-consuming and laborious, and is not convenient for reuse between multiple chip projects, resulting in low verification efficiency of the clock gating. Therefore, how to improve the verification efficiency of the clock gating becomes a technical problem to be solved. SUMMARY

[0003] The present application aims to provide a clock gating automatic verification method, an electronic device and a medium, which improves the verification efficiency of the clock gating.

[0004] According to a first aspect of the present application, a clock gating automatic verification method is provided, comprising:

[0005] Step S1, obtaining the clock gating path information {G1, G2,..., Gn} corresponding to the chip design to be tested. n ,...,G N}, Gn is the path information corresponding to the nth clock gating in the chip design to be tested. n G1 is generated by splicing G1, G2,..., Gn, G1 is the name of the chip design to be tested, G2 is the name of the chip IP corresponding to the nth clock gating in the chip design to be tested, and G3 is the name of the public library unit corresponding to the nth clock gating. n n n n n n n The chip design to be tested comprises a plurality of chip IPs, and each chip IP comprises a plurality of public library units, each public library unit corresponding to a clock gating.

[0006] Step S2, generating a corresponding clock gating signal value reading function A n based on each G n .

[0007] Step S3, in the simulation process of the chip design to be tested, calling A n ​​​​​​Acquiring G n Corresponding gated clock actual measurement value B n ;

[0008] Step S4, acquiring the corresponding prediction value of each gated clock, comparing B n with the prediction value corresponding to the nth gated clock, if all B n are consistent with the prediction value corresponding to the nth gated clock, the verification is passed, otherwise, based on the gated clock with inconsistent actual measurement value and prediction value, a prompt information is generated.

[0009] According to the second aspect of the present application, an electronic device is provided, comprising: at least one processor; and a memory in communication connection with the at least one processor; wherein the memory stores instructions executed by the at least one processor, and the instructions are configured to execute the method according to the first aspect of the present application.

[0010] According to the third aspect of the present application, a computer readable storage medium is provided, which stores computer executable instructions, and the computer executable instructions are used to execute the method according to the first aspect of the present application.

[0011] Compared with the prior art, the present application has obvious advantages and beneficial effects. By means of the above technical scheme, the gated clock automatic verification method, electronic device and medium provided by the present application can achieve considerable technical progress and practicability, and have wide industrial utilization value, and at least have the following beneficial effects:

[0012] The present application can automatically acquire the path information of each gated clock in the chip design to be tested, generate a corresponding gated clock signal value reading function based on the path information of each gated clock, acquire the actual value corresponding to each gated clock through the gated clock signal value reading function in the simulation process of the chip design to be tested, compare the actual value of each gated clock with the corresponding prediction value, and realize automatic verification of the gated clock. The present application improves the verification efficiency of the gated clock. BRIEF DESCRIPTION OF DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0014] Figure 1 The gated clock automatic verification method flowchart provided by the embodiment of the present application. DETAILED DESCRIPTION

[0015] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0016] This invention provides an automatic verification method for gated clocks, such as... Figure 1 As shown, it includes:

[0017] Step S1: Obtain the gated clock path information {G1,G2,...,G} corresponding to the chip under test design. n ,...,G N}, G n G represents the path information corresponding to the nth gated clock in the chip under test design. n By G1 n G2 n G3 n Generate by splicing, G1 n G2 is the design name of the chip under test. n G3 is the chip IP name corresponding to the nth gated clock in the chip under test design. n The name of the common library unit corresponding to the nth gated clock is given. The chip design under test includes multiple chip IPs, each of which includes multiple common library units, and each common library unit corresponds to a gated clock.

[0018] It should be noted that the gated clock path information in this embodiment of the invention is generated by concatenating three segments: the design name of the chip under test (DUT), the chip IP name, and the common library unit. Different DUT designs may contain the same chip IP, and different chip IPs may also contain the same common library unit. Therefore, the chip IP name and the common library unit name can be reused by different DUT designs.

[0019] Step S2, based on each G n Generate the corresponding gated clock signal value reading function A n .

[0020] It should be noted that the function template for reading the gated clock signal value is set to input G. n The output is G n The corresponding measured value of the gated clock.

[0021] Step S3: During the design simulation of the chip under test, call A n Get G n The corresponding measured value B of the gated clock n .

[0022] Wherein, in the simulation process of the to-be-tested chip design, the backdoor access mode can be used to call A n Obtaining G n Corresponding measured value B of the gated clock n .

[0023] Step S4, obtaining the predicted value corresponding to each gated clock, comparing B n with the predicted value corresponding to the nth gated clock, if all B n are consistent with the predicted value corresponding to the nth gated clock, the verification is passed, otherwise, the prompt information is generated based on the gated clock with inconsistent measured value and predicted value.

[0024] It should be noted that the embodiment of the present application can automatically obtain the gated clock path information corresponding to the to-be-tested chip design, which will be illustrated by two specific embodiments.

[0025] Embodiment one

[0026] The step S1 comprises:

[0027] Step S11, obtaining the hierarchical information corresponding to the to-be-tested chip design, the hierarchical information corresponding to the to-be-tested chip design comprising the to-be-tested chip design identifier, the chip IP identifier corresponding to the to-be-tested chip design, and the public library unit identifier corresponding to each chip IP of the to-be-tested chip design.

[0028] Step S12, based on the hierarchical information corresponding to the to-be-tested chip design and the first mapping table, the second mapping table and the third mapping table pre-set, obtaining the to-be-tested chip design name, the chip IP name and the public library unit name corresponding to each gated clock; the first mapping table comprises the to-be-tested chip design identifier and the to-be-tested chip design name, the second mapping table comprises the chip IP identifier and the chip IP name, and the third mapping table comprises the public library unit identifier and the public library unit name.

[0029] It should be understood that the information in the second mapping table and the third mapping table can be reused by different to-be-tested chip designs in the first mapping table.

[0030] Step S13, splicing the to-be-tested chip design name, the chip IP name and the public library unit name corresponding to each gated clock to generate the gated clock path information corresponding to each gated clock.

[0031] It should be noted that the first mapping table, the second mapping table and the third mapping table are used to maintain the name mapping information of different levels of the to-be-tested chip design, when a new to-be-tested chip design appears, only the first mapping table, the second mapping table and the third mapping table need to be locally changed, as an embodiment, the method further comprises:

[0032] Step S10, if the to-be-tested chip design is a newly-added to-be-tested chip design, step S20 is performed, otherwise, step S1 is performed.

[0033] Step S20, the name of the newly-added to-be-tested chip design, the chip IP identifiers of all chip IPs of the newly-added to-be-tested chip design and the names of the corresponding chip IPs, and all public library unit identifiers of the newly-added to-be-tested chip design and the names of the corresponding public library units are obtained.

[0034] Step S30, the name of the newly-added to-be-tested chip design and the identifier of the corresponding newly-added to-be-tested chip design are added to the first mapping table.

[0035] Step S40, the chip IP identifiers of the newly-added to-be-tested chip design and the names of the corresponding chip IPs that do not currently exist in the second mapping table are stored in the second mapping table.

[0036] It can be understood that some chip IP identifiers of the newly-added to-be-tested chip design and the names of the corresponding chip IPs may already exist in the second mapping table, and the information already existing in the second mapping table can be directly used, without the need for repeated addition.

[0037] Step S50, the public library unit identifiers of the newly-added to-be-tested chip design and the names of the corresponding public library units that do not currently exist in the third mapping table are stored in the third mapping table, and then step S1 is performed.

[0038] It can be understood that some public library unit identifiers of the newly-added to-be-tested chip design and the names of the corresponding public library units may already exist in the third mapping table, and the information already existing in the third mapping table can be directly used, without the need for repeated addition.

[0039] It should be noted that when a newly-added to-be-tested chip design appears, only partial updating of the first mapping table, the second mapping table and the third mapping table is needed to implement the automatic verification of the gated clock of the to-be-tested chip design based on steps S1-S4, thereby improving the verification efficiency of the gated clock.

[0040] When there is a to-be-tested chip design that needs to be deleted, the method further comprises:

[0041] Step S100, the identifier of the to-be-deleted to-be-tested chip design is obtained.

[0042] Step S200, the chip IP identifiers of the chip IPs that exist in the to-be-deleted to-be-tested chip design and do not exist in other to-be-tested designs except the to-be-deleted chip design are determined as to-be-deleted chip IP identifiers.

[0043] Step S300, determine the common library unit identifiers existing in the to-be-tested chip design to be deleted and not existing in other to-be-tested designs as the to-be-deleted common library unit identifiers.

[0044] Step S400, delete the mapping relationship information corresponding to the to-be-tested chip design identifier in the first mapping table, delete the mapping relationship information corresponding to the to-be-deleted chip IP identifier in the second mapping table, and delete the mapping relationship corresponding to the common library unit identifier in the to-be-tested design in the third mapping table.

[0045] Embodiment one can realize fast generation of the gated clock path information through the first mapping table, the second mapping table and the third mapping table, and only needs to locally change the first mapping table, the second mapping table and the third mapping table in the process of adding or deleting the to-be-tested chip design.

[0046] Embodiment two

[0047] At least one register is pre-set in the chip IP of each to-be-tested chip design, that is, one register or multiple registers. The register of the chip IP is pre-configured with the gated clock path information corresponding to the chip IP and the gated clock opening identifier, that is, the gated clock path information corresponding to the chip IP and the gated clock opening identifier can exist in one register or be distributed in multiple registers.

[0048] The step S1 comprises:

[0049] Step C11, traverse each register of each chip IP in the to-be-tested chip design, and obtain the gated clock path information {G1, G2,..., G n ,...,G N} corresponding to the to-be-tested chip design.

[0050] In this embodiment, the gated clock path information corresponding to the to-be-tested chip design is obtained by reading each register of each chip IP.

[0051] The default prediction value of each gated clock is set as a first value, and the step S4 of obtaining the prediction value corresponding to each gated clock comprises:

[0052] Step S41, read the gated clock opening identifier in each register of the chip IP of the to-be-tested chip design.

[0053] The gated clock opening identifier specifically comprises an opening identifier and a closing identifier.

[0054] Step S42, if the gate clock opening identifier is an opening identifier, a preset value corresponding to the gate clock is set as a second value, and if the gate clock opening identifier is a closing identifier, the preset value corresponding to the gate clock is kept as a default first value.

[0055] As an example, the first value is set as 1, and the second value is set as 2.

[0056] As another example, the chip design to be tested is provided with a target register for storing overall preset value configuration information, and in step S4, the predicted value corresponding to each gate clock is obtained, including:

[0057] Step S40, the target register is read, if the configuration value is empty, step S41 is executed, if the target register is the first configuration value, the preset value corresponding to all gate clocks of the chip design to be tested is set as the first value, and if the target register is the second configuration value, the preset value corresponding to all gate clocks of the chip design to be tested is set as the second value.

[0058] Step S40 can further meet the application scenario with the overall predicted value unified configuration requirement.

[0059] It should be noted that some example embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts depict the steps in a particular order, many of the steps can be performed concurrently, in parallel, or simultaneously. In addition, the order of the steps can be re-arranged. The processes can terminate when their operations are completed, but can also have additional steps not included in the figure. The processes can correspond to methods, functions, procedures, subroutines, subprograms, etc.

[0060] The embodiment of the present application also provides an electronic device, comprising: at least one processor; and a memory connected with the at least one processor in communication; wherein the memory stores instructions executed by the at least one processor, and the instructions are arranged to execute the method provided by the embodiment of the present application.

[0061] The embodiment of the present application also provides a computer readable storage medium, which stores computer executable instructions, and the computer executable instructions are used for executing the method provided by the embodiment of the present application.

[0062] The embodiment of the present application can automatically acquire the path information of each gate clock in the chip design to be tested, generate a corresponding gate clock signal value reading function based on the path information of each gate clock, acquire the actual value corresponding to each gate clock through the gate clock signal value reading function in the simulation process of the chip design to be tested, compare the actual value of each gate clock with the corresponding predicted value, and realize the automatic verification of the gate clock. The present application improves the verification efficiency of the gate clock.

[0063] The above merely describes preferred embodiments of the present application, and is not intended to limit the present application in any form. Although the present application has been disclosed with the preferred embodiments as above, it is not intended to limit the present application, and any person skilled in the art can make some changes or modifications to the above disclosed technical contents to obtain equivalent embodiments with equivalent changes, as long as the changes or modifications do not depart from the technical solution of the present application. Any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application still falls within the scope of the technical solution of the present application.

Claims

1. An automatic verification method for a gated clock, characterized in that, include: Step S1: Obtain the gated clock path information {G1,G2,...,G} corresponding to the chip under test design. n ,...,G N }, G n G represents the path information corresponding to the nth gated clock in the chip under test design. n By G1 n G2 n G3 n Generate by splicing, G1 n G2 is the design name of the chip under test. n G3 is the chip IP name corresponding to the nth gated clock in the chip under test design. n The name of the common library unit corresponding to the nth gated clock is given. The chip under test design includes multiple chip IPs, and each chip IP includes multiple common library units. Each common library unit corresponds to a gated clock. Step S2, based on each G n Generate the corresponding gated clock signal value reading function A n ; Step S3: During the design simulation of the chip under test, call A n Get G n The corresponding measured value B of the gated clock n ; Step S4: Obtain the predicted value corresponding to each gate clock, and set B... n Compare with the predicted value corresponding to the nth gated clock, if all B n If all values ​​are consistent with the predicted value corresponding to the nth gated clock, the verification is successful; otherwise, a prompt message is generated based on the gated clock whose measured value and predicted value are inconsistent. Step S1 includes: Step S11: Obtain the hierarchical information corresponding to the chip design under test. The hierarchical information corresponding to the chip design under test includes the chip design identifier, the chip IP identifier corresponding to the chip design under test, and the common library unit identifier corresponding to each chip IP of the chip design under test. Step S12: Based on the hierarchical information corresponding to the chip design under test and the pre-set first mapping table, second mapping table and third mapping table, obtain the chip design name, chip IP name and common library unit name corresponding to each gated clock; The first mapping table includes the chip design identifier and the chip design name, the second mapping table includes the chip IP identifier and the chip IP name, and the third mapping table includes the common library unit identifier and the common library unit name; Step S13: Concatenate the design name of the chip under test, the chip IP name, and the common library unit name corresponding to each gated clock to generate the gated clock path information corresponding to each gated clock. The default prediction value for each gated clock is set to a first value. In step S4, obtaining the prediction value corresponding to each gated clock includes: Step S41: Read the gated clock enable flag in each register of the chip IP of the chip design under test; Step S42: If the gate clock is on, set the preset value corresponding to the gate clock to the second value; if the gate clock is off, keep the preset value corresponding to the gate clock at the default first value.

2. The method according to claim 1, characterized in that, The method further includes: Step S10: If the chip under test is a newly added chip under test design, then proceed to step S20; otherwise, proceed to step S1. Step S20: Obtain the name of the newly added chip design under test, the chip IP identifiers and corresponding chip IP names of all chip IPs of the newly added chip design under test, and the identifiers and corresponding common library unit names of all common library units of the newly added chip design under test. Step S30: Add the name of the newly added chip design under test and the corresponding identifier of the newly added chip design under test to the first mapping table; Step S40: Store the chip IP identifier and the corresponding chip IP name of the newly added chip design under test that does not currently exist in the second mapping table in the second mapping table; Step S50: Store the public library unit identifier and corresponding public library unit name of the newly added chip design under test that does not currently exist in the third mapping table in the third mapping table, and then execute step S1.

3. The method according to claim 1, characterized in that, The method further includes: Step S100: Obtain the design identifier of the chip to be deleted; Step S200: The chip IP identifier of the chip IP that exists in the chip design to be deleted but does not exist in other designs to be deleted is determined as the chip IP identifier to be deleted; Step S300: Determine the common library cell identifier that exists in the chip design to be deleted but does not exist in other designs to be deleted outside the chip design to be deleted as the common library cell identifier to be deleted; Step S400: Delete the mapping relationship information corresponding to the chip design identifier under test in the first mapping table, delete the mapping relationship information corresponding to the chip IP identifier to be deleted in the second mapping table, and delete the mapping relationship corresponding to the common library unit identifier in the design under test in the third mapping table.

4. The method according to claim 1, characterized in that, Each chip IP design under test has at least one register pre-configured, and the register of the chip IP is pre-configured with the gated clock path information and gated clock enable flag corresponding to the chip IP.

5. The method according to claim 4, characterized in that, Step S1 includes: Step C11: Traverse each register of each chip IP in the chip under test design to obtain the gated clock path information {G1,G2,...,G...} corresponding to the chip under test design. n ,...,G N } 6. The method according to claim 5, characterized in that, The chip under test design includes a target register for storing overall preset value configuration information. In step S4, obtaining the predicted value corresponding to each gate clock includes: Step S40: Read the target register. If the configuration value is empty, proceed to step S41. If the target register is the first configuration value, set the preset value corresponding to all gated clocks of the chip under test to the first value. If the target register is the second configuration value, set the preset value corresponding to all gated clocks of the chip under test to the second value.

7. An electronic device, characterized in that, include: At least one processor; And, a memory communicatively connected to the at least one processor; The memory stores instructions that are executed by the at least one processor, the instructions being configured to perform the method of any one of claims 1-6.

8. A computer-readable storage medium, characterized in that, The device stores computer-executable instructions for performing the method of any one of claims 1-6.

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