Novel capacitance-free dynamic random access memory device
By adopting a stacking structure of N-type write transistors and P-type read transistors in 2T0CDRAM, the storage window is increased and the charge is stored using the parasitic capacitive coupling effect, which solves the power increase problem caused by the capacitive coupling effect, and achieves higher retention characteristics and lower operating voltage.
Patent Information
- Application Number
- CN202410212534.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-02-27
- Publication Date
- 2025-08-29
AI Technical Summary
In the existing 2T0CDRAM cell, both the write transistor and the read transistor are based on n-type transistors, resulting in a capacitive coupling effect that reduces the SN point voltage, the write voltage of state 1 becomes larger, and the window between state 1 and state 0 becomes smaller, increasing power consumption.
The stacking structure of N-type write transistors and P-type read transistors is adopted to increase the storage window through the capacitance coupling effect generated by the parasitic capacitance of the N-type write transistor, and the gate capacitance of the P-type read transistor is used to store charges, forming an interconnect structure to reduce the operating voltage and refresh frequency.
The storage window is enhanced, the charge retention time is extended, the operating voltage and refresh frequency are reduced, and the retention characteristics of the new capacitance-free dynamic random storage device are improved.
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Figure CN120564792A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the technical field of integrated circuits and microelectronic devices, and in particular to a novel capacitor-free dynamic random access memory device. Background Art
[0002] Dynamic random access memory (DRAM) is a volatile, capacitor-based, destructive memory. Since its invention in the 1960s, DRAM has undergone decades of development and currently holds a significant position in the memory market, accounting for over 50% of the market.
[0003] For a long time, DRAM cells have consisted of a structure consisting of one transistor and one capacitor (1T1C). When performing a write operation, this type of storage cell turns on the transistor, and charge is pushed into the capacitor (writing 1) or removed from the capacitor (writing 0). When reading, the charge in the capacitor is extracted. Traditional 1T1C DRAM has fast read and write speeds, but it cannot meet the needs of achieving higher capacity, higher performance and smaller cell size without increasing power consumption. In addition, the transistors in DRAM are based on traditional Si-based transistors, which have large off-state leakage and need to be refreshed every 64ms. When reading information from the capacitor, the charge will be lost and need to be rewritten and refreshed, which is a destructive read operation. The capacitor-free 2T0C DRAM cell proposed in recent years can solve the limitations of further miniaturization. The write transistor based on oxide transistors has ultra-low off-state current and long retention time. The read operation is a non-destructive operation, which can effectively reduce the power consumption of DRAM cells.
[0004] For capacitor-less 2T0CDRAM, in the write phase, a positive voltage is applied to the WWL terminal to turn on the write transistor, and a positive / negative voltage is applied to the WBL terminal to write the state 1 / 0 to the SN terminal. The charge is stored in the gate electrode of the read transistor to save the information; in the read phase, a negative voltage is applied to the WWL terminal to ensure that the write transistor is completely turned off, and the DRAM storage information is read by reading the current at the RBL terminal.
[0005] However, the write transistor and read transistor of the currently proposed 2T0CDRAM cell are both based on n-type transistors. After writing the 1 state, the write transistor switches from on to off, and the WWL level switches from positive to negative. However, due to the parasitic capacitance between the WWL and SN terminals of the write transistor, the capacitive coupling effect causes the SN point voltage to decrease, resulting in a lower state 1 write voltage, an increase in the operating voltage, and a smaller window between state 1 and state 0, which increases the power consumption of the DRAM.
[0006] Therefore, how to reduce the impact of capacitive coupling effect on write level and operating voltage is a technical problem that needs to be solved urgently in 2T0C DRAM. Summary of the Invention
[0007] In view of the defects in the prior art, the present invention aims to provide a novel capacitor-free dynamic random access memory device.
[0008] To achieve the above objectives, according to one aspect of the present disclosure, a novel capacitor-less dynamic random access memory device is provided, comprising: an N-type write transistor, a P-type read transistor, and an interconnect structure disposed between the N-type write transistor and the P-type read transistor, wherein the N-type write transistor is disposed above the P-type read transistor;
[0009] The ports of the N-type write transistor include an N-tube source WBL terminal, an N-tube drain terminal, and an N-tube gate terminal WWL terminal, and the N-type write transistor is used as a switching element of the storage unit;
[0010] The P-type read transistor includes a P-tube source RWL terminal, a P-tube drain RBL terminal and a P-tube gate terminal, and the P-type read transistor is used as a storage element of the storage unit;
[0011] The drain of the N-type transistor and the gate of the P-type transistor are connected to form the interconnection structure, the N-type write transistor forms a parasitic capacitor, and the gate capacitance of the P-type transistor is used to store charge.
[0012] Optionally, the N-type write transistor further includes a first semiconductor layer, and the first semiconductor layer is made of a metal oxide semiconductor material.
[0013] Optionally, the N-type transistor source WBL end, the N-type transistor drain and the first semiconductor layer are arranged in the same layer.
[0014] Optionally, the source electrode WBL of the N-type transistor is connected to one end of the first semiconductor layer, and the drain electrode of the N-type transistor is connected to the other end of the first semiconductor layer.
[0015] Optionally, the P-type read transistor further includes a second semiconductor layer, and the second semiconductor layer is made of any one of low-temperature polysilicon, single crystal silicon, and germanium.
[0016] Optionally, the P-type transistor source RWL end, the P-type transistor drain RBL end, and the second semiconductor layer are arranged on the same layer.
[0017] Optionally, the source electrode RWL of the P-type transistor is connected to one end of the second semiconductor layer, and the drain electrode RBL of the P-type transistor is connected to the other end of the second semiconductor layer.
[0018] Optionally, the material of the N-transistor source WBL, the N-transistor drain and the N-transistor gate WWL is any one of nickel, gold, titanium and indium tin oxide, or a combination of two or more thereof.
[0019] Optionally, the N-type write transistor is a bottom-gate transistor, and the P-type read transistor is a top-gate transistor.
[0020] Optionally, the interconnect structure is made of any one of indium oxide, nickel, and titanium, or a combination of two or more thereof.
[0021] Compared with the prior art, the embodiments of the present disclosure have at least one of the following beneficial effects:
[0022] Through the above technical solution, a novel capacitor-free dynamic random access memory device is formed by using an N-type write transistor, a P-type read transistor, and an interconnection structure formed by connecting the N-type write transistor and the P-type read transistor. During the read and write phases, the capacitive coupling effect generated by the parasitic capacitance of the N-type write transistor is used to increase the write voltage and storage window of the storage element, namely the P-type read transistor. The gate capacitance of the P-transistor is used to store charge and extend the retention time of the charge stored in the P-type read transistor, thereby improving the retention characteristics of the novel capacitor-free dynamic random access memory device. In addition, the operating voltage and refresh frequency of the novel capacitor-free dynamic random access memory device can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Other features, objects and advantages of the present disclosure will become more apparent upon reading the detailed description of non-limiting embodiments with reference to the following drawings:
[0024] Figure 1 The figure is a circuit diagram of a novel capacitor-free dynamic random access memory device according to an exemplary embodiment.
[0025] Figure 2 FIG. 1 is a schematic cross-sectional view of a novel capacitor-free dynamic random access memory device according to an exemplary embodiment.
[0026] Figure 3 The figure is a schematic diagram of voltage time domain waveforms of write and read operations of a novel capacitor-less dynamic random access memory device according to an exemplary embodiment.
[0027] Figure 4 The figure is a comparative diagram showing the influence of the capacitive coupling effect on the initial voltage of the SN point during the read and write phases of an N+P type capacitor-free dynamic random access memory device and an N+N type capacitor-free dynamic random access memory device, according to an exemplary embodiment.
[0028] Figure 5 The figure is a schematic diagram showing the relationship between the initial voltage corresponding to the read phase and the voltage applied to the N-tube source WBL terminal and the N-tube gate WWL terminal of a novel capacitor-free dynamic random access memory device during the write state 1 according to an exemplary embodiment.
[0029] Figure 6The figure is a current-time diagram of state 0 and state 1 of a novel capacitor-free dynamic random access memory device in a read phase, shown as an exemplary embodiment.
[0030] Description of Reference Numerals
[0031] 100 New Capacitor-Free Dynamic Random Access Memory Device
[0032] 1 Bottom-gate transistor
[0033] 2 Top-gate transistor
[0034] 11N tube source WBL end
[0035] 12. First semiconductor layer
[0036] 13 N tube drain
[0037] 14N tube gate WWL terminal
[0038] 15P tube source RWL end
[0039] 16 second semiconductor layer
[0040] 17P tube drain RBL terminal
[0041] 18 P tube gate
[0042] 19 Interconnection Structure DETAILED DESCRIPTION
[0043] The present disclosure is described in detail below with reference to specific embodiments. The following embodiments will help those skilled in the art further understand the present disclosure, but are not intended to limit the present disclosure in any way. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the scope of the present disclosure. These modifications and improvements are all within the scope of protection of the present disclosure.
[0044] Figure 1 The figure is a circuit diagram of a novel capacitor-free dynamic random access memory device according to an exemplary embodiment. Figure 2 FIG. 1 is a schematic cross-sectional view of a novel capacitor-free dynamic random access memory device according to an exemplary embodiment.
[0045] like Figure 1 As shown, the present disclosure provides a novel capacitor-free dynamic random access memory device 100, comprising: an N-type write transistor, a P-type read transistor, and an interconnection structure 19 arranged between the N-type write transistor and the P-type read transistor.
[0046] like Figure 2As shown, the N-type write transistor is arranged above the P-type read transistor, and the N-type write transistor and the P-type read transistor adopt a stacked structure. The P-type write transistor and the N-type read transistor can be fabricated sequentially in a bottom-up manner to form a vertically stacked high-density monolithic three-dimensional integrated structure.
[0047] By adopting a bottom-up monolithic three-dimensional integrated packaging method, the integration of internal components of the novel capacitor-free dynamic random access memory device 100 and the storage density of the semiconductor structure can be improved, and the size of the storage unit in the novel capacitor-free dynamic random access memory device 100 can be reduced.
[0048] like Figure 1 、 Figure 2 As shown, the ports of the N-type write transistor include an N-tube source WBL terminal 11 , an N-tube drain 13 , and an N-tube gate WWL terminal 14 . The N-type write transistor is used as a switching element of the storage element.
[0049] The N-type write transistor may be a bottom-gate transistor 1 .
[0050] In a possible embodiment, the material of the N-transistor source WBL terminal 11 , the N-transistor drain 13 , and the N-transistor gate WWL terminal 14 is any one of nickel, gold, titanium, and indium tin oxide, or a combination of two or more thereof.
[0051] The P-type read transistor includes a P-transistor source RWL terminal 15 , a P-transistor drain RBL terminal 17 , and a P-transistor gate 18 . The P-type read transistor is used as a storage element.
[0052] The P-type read transistor may be a top-gate transistor 2 .
[0053] The drain electrode 13 of the N-type transistor and the gate electrode 18 of the P-type transistor are connected to form an interconnection structure 19 . The N-type write transistor forms a parasitic capacitor, and the gate capacitance of the P-type transistor is used to store charge.
[0054] The N-transistor drain 13 and the P-transistor gate 18 are connected to form an interconnection structure 19 which can be recorded as an SN node, thereby forming a 2T0C circuit structure in the memory cell, that is, a circuit structure with two transistors and no capacitor.
[0055] In a possible embodiment, the material of the interconnect structure may be any one of indium oxide, nickel, and titanium, or a combination of two or more thereof.
[0056] The material of the interconnect structure can be the same as that of the N-transistor source WBL terminal 11 , the N-transistor drain 13 , and the N-transistor gate WWL terminal 14 .
[0057] In a possible embodiment, the capacitive coupling effect of the parasitic capacitance causes the node voltage at the SN point to be greater than the voltage at the written N-transistor source WBL terminal 11 .
[0058] Through the above technical solution, a novel capacitor-free dynamic random access memory device 100 is formed by using an N-type write transistor, a P-type read transistor, and an interconnection structure 19 formed by connecting the N-type write transistor and the P-type read transistor. During the read and write phases, the capacitive coupling effect generated by the parasitic capacitance of the N-type write transistor is used to increase the write voltage and storage window of the storage element, namely the P-type read transistor. The gate capacitance of the P-tube is used to store charge and extend the retention time of the charge stored in the P-type read transistor, thereby improving the retention characteristics of the novel capacitor-free dynamic random access memory device 100. In addition, the operating voltage and refresh frequency of the novel capacitor-free dynamic random access memory device 100 can also be reduced.
[0059] In a possible embodiment, the N-type write transistor further includes a first semiconductor layer 12 , and the first semiconductor layer 12 is made of a metal oxide semiconductor material.
[0060] For example, the first semiconductor layer 12 may be made of zinc oxide semiconductor material or indium gallium zinc oxide semiconductor material. In addition, the electron mobility of the first semiconductor layer 12 is greater than 10 cm 2 / V·s.
[0061] In a possible embodiment, the first semiconductor layer 12 may be prepared by atomic layer deposition or sputtering deposition, and the preparation temperature is less than 400°C.
[0062] For example, the zinc oxide material is prepared by an atomic layer deposition process, or the multi-component oxide material containing indium oxide and zinc oxide (ie, indium gallium zinc oxide material) is prepared by an atomic layer deposition process, and the preparation temperature is less than 400°C.
[0063] Through the above technical solution, the N-type write transistor adopts the atomic layer deposition process, which is not only compatible with uniform deposition over a larger area, but also can accurately control the thickness performance of the thin film of the first semiconductor layer 12, while maintaining low leakage while obtaining high mobility. For example, the leakage current of the N-type write transistor is less than 10-17A / μm, which is beneficial to improving the retention characteristics of the new capacitor-free dynamic random access memory device 100.
[0064] like Figure 2 As shown, the N-transistor source WBL terminal 11 , the N-transistor drain 13 and the first semiconductor layer 12 are arranged on the same layer.
[0065] The N-type transistor source electrode WBL terminal 11 is connected to one end of the second semiconductor layer 12 , and the N-type transistor drain electrode 13 is connected to the other end of the second semiconductor layer 12 .
[0066] The N-tube gate WWL terminal 14 may be disposed below the layer where the N-tube source WBL terminal 11 , the second semiconductor layer 12 , and the N-tube drain 13 are located.
[0067] In a possible embodiment, the N-type write transistor further includes a first insulating layer, which is disposed between the N-transistor source WBL terminal 11 , the N-transistor drain 13 , the first semiconductor layer 12 , and the N-transistor gate WWL terminal 14 .
[0068] The first insulating layer of the N-type write transistor may be prepared by an atomic layer deposition process, and the material of the first insulating layer of the N-type write transistor may be a metal oxide material with a high dielectric constant, such as aluminum oxide or hafnium oxide.
[0069] In a possible embodiment, the P-type read transistor further includes a second semiconductor layer 16 , and the second semiconductor layer 16 is made of any one of low-temperature polysilicon, single crystal silicon, and germanium.
[0070] For example, the second semiconductor layer 16 may be made of low-temperature polysilicon, silicon, or germanium. In addition, the hole mobility of the second semiconductor layer 16 is greater than 50 cm 2 / V·s.
[0071] The second semiconductor layer 16 has stable performance under high temperature conditions, thereby preventing the N-type write transistor from affecting the P-type read transistor during the preparation process.
[0072] like Figure 2 As shown, in a possible embodiment, the P-tube source RWL terminal, the P-tube drain RBL terminal 17 and the second semiconductor layer 16 are arranged on the same layer.
[0073] In the present disclosure, the P-tube source RWL terminal, the P-tube drain RBL terminal 17 and the second semiconductor layer 16 are all disposed on the upper surface of the substrate.
[0074] The source electrode RWL of the P-type transistor is connected to one end of the second semiconductor layer 16 , and the drain electrode RBL of the P-type transistor is connected to the other end of the second semiconductor layer 16 .
[0075] The P-tube gate 18 may be disposed above the layer where the P-tube PWL segment, the second semiconductor layer 16 , and the P-tube drain RBL terminal 17 are located.
[0076] In a possible embodiment, the P-type read transistor also includes a second insulating layer, which is disposed between the P-type transistor source RWL terminal, the P-type transistor drain RBL terminal 17 , the layer where the second semiconductor layer 16 is located, and the P-type transistor gate 18 .
[0077] like Figure 2As shown, the bottom layer is a top-gate transistor 2, i.e., a P-type read transistor, which serves as the storage element of the memory cell in the novel capacitor-less dynamic random access memory device 100. The top layer is a bottom-gate transistor 1, i.e., an N-type write transistor, which serves as the switching element of the memory cell in the novel capacitor-less dynamic random access memory device 100. This simplifies the manufacturing process of the novel capacitor-less dynamic random access memory device 100 while further reducing the size of the memory cell, thereby reducing the manufacturing difficulty.
[0078] Figure 3 The figure is a schematic diagram of voltage time domain waveforms of write and read operations of a novel capacitor-less dynamic random access memory device according to an exemplary embodiment.
[0079] like Figure 3 As shown, in a possible embodiment, during the operation of the novel capacitor-less dynamic random access memory device 100, a write operation is performed on the N-type write transistor, a high-level signal is applied to the N-type gate WWL terminal 14, and the N-type write transistor is turned on. A low-level signal is applied to the N-type source WBL terminal 11, and charge is stored in the capacitance of the P-type read transistor gate 18, which is recorded as writing "1". At this time, the voltage at the SN point is negative, and the P-type read transistor is in the on state.
[0080] In another possible embodiment, when performing a write operation on the N-type write transistor, a high-level signal is applied to the N-type transistor source WBL terminal 11, and the charge is stored in the capacitance of the P-type read transistor gate 18, which is recorded as writing "0". At this time, the voltage at the SN point is a positive level, the P-type read transistor is in the off state, and the P-type transistor source RWL terminal 15 maintains a constant voltage, and the P-type transistor drain RBL terminal 17 maintains a voltage of 0V.
[0081] In another possible embodiment, when performing a read operation on the P-type read transistor, the potential of the SN point and the charge amount and storage information in the storage unit can be determined by reading the current at the P-type transistor source RWL terminal 15.
[0082] like Figure 3 As shown in the figure, during the process from writing "1" stage to reading stage, the level of the N-tube gate WWL terminal 14 drops from a positive level to a negative level. Due to the capacitive coupling effect of the parasitic capacitance of the SN point, the level of the SN point drops accordingly, the current corresponding to writing "1" is further increased, and the absolute value of the potential corresponding to the SN point becomes larger, so the state "1" is enhanced.
[0083] If a capacitor-free dynamic random access memory device composed of two N-type transistors is used, the state "1" will be weakened due to the same capacitive coupling effect.
[0084] Figure 4The figure is a comparative diagram showing the influence of the capacitive coupling effect on the initial voltage of the SN point during the read and write phases of an N+P type capacitor-free dynamic random access memory device and an N+N type capacitor-free dynamic random access memory device, according to an exemplary embodiment.
[0085] like Figure 4 As shown, in the writing phase of the N+N type capacitor-free dynamic random access memory device, when the N type write transistor switches from on to off, the N transistor gate WWL terminal 14 switches from high level to low level, and the capacitive coupling effect between the N transistor gate WWL terminal 14 and the SN point causes the voltage of the SN point to drop by ΔV. SN,CC , which results in the initial voltage V SN,init The absolute value of decreases and the state "1" is weakened.
[0086] In the write phase of the N+P type capacitor-free dynamic random access memory device, when the N type write transistor switches from on to off, the N transistor gate WWL terminal 4 changes from high level to low level. The capacitive coupling effect between the N transistor gate WWL terminal 14 and the SN point causes the voltage of the SN point to increase by ΔV. SN,CC , which results in the initial voltage V SN,init The absolute value V SN,init As , the state "1" is enhanced, achieving the effect of increasing the storage window.
[0087] Figure 5 1 is a schematic diagram showing the relationship between the initial voltage corresponding to the read phase and the voltage applied to the N-transistor source WBL terminal 11 and the N-transistor gate WWL terminal 14 of a novel capacitor-less dynamic random access memory device 100 during the write state 1 according to an exemplary embodiment.
[0088] like Figure 5 As shown, in a possible embodiment, in the write phase, when the write voltage is a negative level as the state "1" to the SN point, that is, when a negative level is applied to the N-tube source WBL terminal 11, the absolute value of the SN point voltage obtained in the read phase is higher than the voltage applied to the N-tube source WBL terminal 11 during writing, indicating that the capacitive coupling effect enhances the state "1".
[0089] Moreover, during writing, the lower the voltage applied to the WWL terminal 14 of the N transistor gate is, the weaker the capacitive coupling effect is, and the smaller the absolute value of the initial voltage at the SN point is.
[0090] Figure 6 The figure is a current-time diagram of state 0 and state 1 of a novel capacitor-free dynamic random access memory device in a read phase, shown as an exemplary embodiment.
[0091] like Figure 6As shown in a possible embodiment, the novel capacitor-free dynamic random access memory device 100 disclosed in the present invention can still maintain a 10-second difference between the state "1" and the state "0" after 10,000 seconds. 4 The current ratio is mainly due to the ground leakage characteristics of the oxide semiconductor layer, which enables the storage element to retain charge for a long time. In addition, due to the additional gain of the capacitive coupling effect on the state "1", the current ratio and retention time are further enhanced.
[0092] The above describes specific embodiments of the present disclosure. It should be understood that the present disclosure is not limited to the specific embodiments described above, and those skilled in the art may make various modifications or variations within the scope of the claims, which do not affect the essence of the present disclosure. The above preferred features may be used in any combination as long as they do not conflict with each other.
Claims
1. A novel capacitor-free dynamic random access memory device, characterized in that: include: An N-type write transistor, a P-type read transistor, and an interconnect structure disposed between the N-type write transistor and the P-type read transistor, wherein the N-type write transistor is disposed above the P-type read transistor; The ports of the N-type write transistor include an N-tube source WBL terminal, an N-tube drain terminal, and an N-tube gate terminal WWL terminal, and the N-type write transistor is used as a switching element of the storage unit; The P-type read transistor includes a P-tube source RWL terminal, a P-tube drain RBL terminal and a P-tube gate terminal, and the P-type read transistor is used as a storage element of the storage unit; The drain of the N-type transistor and the gate of the P-type transistor are connected to form the interconnection structure, the N-type write transistor forms a parasitic capacitor, and the gate capacitance of the P-type transistor is used to store charge.
2. The novel capacitor-less dynamic random access memory device according to claim 1, wherein: The N-type write transistor further includes a first semiconductor layer, and the first semiconductor layer is made of a metal oxide semiconductor material.
3. The novel capacitor-less dynamic random access memory device according to claim 2, wherein: The N-type transistor source WBL end, the N-type transistor drain and the first semiconductor layer are arranged on the same layer.
4. The novel capacitor-less dynamic random access memory device according to claim 3, wherein: The N-type transistor source WBL is connected to one end of the first semiconductor layer, and the N-type transistor drain is connected to the other end of the first semiconductor layer.
5. The novel capacitor-less dynamic random access memory device according to claim 1, wherein: The P-type read transistor further includes a second semiconductor layer, and the second semiconductor layer is made of any one of P-type low-temperature polysilicon, single crystal silicon, and germanium.
6. The novel capacitor-less dynamic random access memory device according to claim 5, wherein: The P-type transistor source electrode RWL, the P-type transistor drain electrode RBL and the second semiconductor layer are arranged on the same layer.
7. The novel capacitor-less dynamic random access memory device according to claim 6, wherein: The source electrode RWL of the P-type transistor is connected to one end of the second semiconductor layer, and the drain electrode RBL of the P-type transistor is connected to the other end of the second semiconductor layer.
8. The novel capacitor-less dynamic random access memory device according to claim 1, wherein: The material of the N-type transistor source WBL end, the N-type transistor drain end and the N-type transistor gate WWL end is any one of nickel, gold, titanium, and indium tin oxide, or a combination of two or more thereof.
9. The novel capacitor-less dynamic random access memory device according to claim 1, wherein: The N-type write transistor is a bottom-gate transistor, and the P-type read transistor is a top-gate transistor.
10. The novel capacitor-less dynamic random access memory device according to claim 1, wherein: The interconnect structure is made of any one of indium oxide, nickel, and titanium, or a combination of two or more thereof.