Pre-charge circuit and non-volatile memory
By using a second switch module with a larger on-current in the nonvolatile memory and a pulse generation module, the problem of pre-charge duration extended due to the increase in bit line load is solved, and faster pre-charge and readout speed is achieved.
Patent Information
- Application Number
- CN202510642296.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-19
- Publication Date
- 2025-08-29
AI Technical Summary
With the increase of nonvolatile memory memory cells, the bit line load increases, resulting in an extended pre-charge time, affecting the effective readout speed of the NVM.
A precharge circuit including the first and second switching modules and a pulse generation module is adopted. The conduction current of the second switching module is greater than that of the first switching module, and the load is precharged with the first switching module within the pulse duration by controlling the pulse signal.
The pre-charge time is shortened and the effective readout speed of non-volatile memory is improved.
Smart Images
Figure CN120564796A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of electronic circuits, and in particular to a pre-charging circuit and a non-volatile memory. Background Art
[0002] In non-volatile memory (NVM) storage circuits, as the number of memory cells increases, the storage capacity continues to grow. This increase in memory cells also leads to a corresponding increase in the bit line load. When precharging the bit lines, the precharging time of the bit lines is prolonged, and this prolonged precharging time greatly affects the effective read speed of the NVM.
[0003] Therefore, how to reduce the pre-charge time of the memory cell bit line and improve the effective read speed of the NVM is an urgent problem to be solved. Summary of the Invention
[0004] In view of this, embodiments of the present application provide a pre-charging circuit and a non-volatile memory to solve the problems existing in the background technology.
[0005] According to a first aspect of an embodiment of the present disclosure, a pre-charging circuit is provided, the pre-charging circuit comprising: a first switching module, a second switching module and a pulse generating module;
[0006] The input end of the first switch module is used to connect to the power signal, and the output end of the first switch module is used to connect to the load; the input end of the second switch module is used to connect to the power signal, and the output end of the second switch module is used to connect to the load;
[0007] The first switch module is configured to, based on the control of a first control signal, conduct the power supply voltage signal to the load to pre-charge the load in response to the first control signal switching from a first level to a second level;
[0008] The pulse generating module is configured to generate a control pulse signal in response to the first control signal switching from a first level to a second level;
[0009] The second switch module is configured to be turned on within the pulse duration of the control pulse signal based on the control of the control pulse signal, and to conduct the power supply voltage signal to the load, so as to pre-charge the load together with the first switch module within the pulse duration;
[0010] The conduction current of the second switch module is greater than the conduction current of the first switch module.
[0011] In some embodiments, the pulse generation module includes: a first inverter, a first delay device and an OR gate, wherein:
[0012] The input terminal of the first inverter is used to input the first control signal, and the output terminal of the first inverter is used to output the second control signal;
[0013] The first delay device is used to delay the second control signal;
[0014] The first input end of the OR gate is used to input the first control signal, the second input end of the OR gate is used to input the delayed second control signal, and the output end of the OR gate is used to output the control pulse signal.
[0015] In some embodiments, the first delay device includes a first transistor,
[0016] The output terminal of the first inverter, the control terminal of the first transistor and the second input terminal of the OR gate are connected, and the input terminal of the first transistor and the output terminal of the first transistor are used to connect to a power ground signal.
[0017] In some embodiments, the first delay device includes a first capacitor,
[0018] The output terminal of the first inverter, the first terminal of the first capacitor and the second input terminal of the OR gate are connected, and the second terminal of the first capacitor is used to connect to a power ground signal.
[0019] In some embodiments, the pulse generation module includes: a second inverter, a third inverter, a second delay device, an AND gate, and a fourth inverter, wherein:
[0020] The input terminal of the second inverter is used to input the first control signal;
[0021] The output terminal of the second inverter, the input terminal of the third inverter and the first input terminal of the AND gate are connected;
[0022] The output terminal of the third inverter is used to output a third control signal;
[0023] The second delay device is used to delay the third control signal;
[0024] The second input terminal of the AND gate is used to input the delayed third control signal;
[0025] The output end of the AND gate is connected to the input end of the fourth inverter, and the output end of the fourth inverter is used to output the control pulse signal.
[0026] In some embodiments, the second delay device includes a second transistor,
[0027] The output terminal of the third inverter, the control terminal of the second transistor and the second input terminal of the AND gate are connected, and the input terminal of the second transistor and the output terminal of the second transistor are used to connect to a power ground signal.
[0028] In some embodiments, the second delay device includes a second capacitor,
[0029] The output terminal of the third inverter, the first terminal of the second capacitor and the second input terminal of the AND gate are connected, and the second terminal of the second capacitor is used to connect to a power ground signal.
[0030] In some embodiments, the first switch module includes a third transistor, wherein a control terminal of the third transistor is used to input the first control signal;
[0031] The second switch module includes a fourth transistor, wherein the control terminal of the fourth transistor is used to input the control pulse signal.
[0032] In some embodiments, a first aspect ratio of a channel width of the third transistor to a channel length of the third transistor is greater than a second aspect ratio of a channel width of the fourth transistor to the channel length of the fourth transistor.
[0033] In some embodiments, the load of the precharge circuit is a bit line of a memory cell in a non-volatile memory.
[0034] According to a second aspect of an embodiment of the present disclosure, a nonvolatile memory is provided, comprising: a storage unit and the precharge circuit according to the first aspect;
[0035] Wherein, the load of the precharge circuit is the bit line of the memory cell.
[0036] Embodiments of the present application provide a pre-charging circuit and a non-volatile memory; the pre-charging circuit includes: a first switch module, a second switch module, and a pulse generating module; the input end of the first switch module is used to connect to a power supply signal, and the output end of the first switch module is used to connect to a load; the input end of the second switch module is used to connect to the power supply signal, and the output end of the second switch module is used to connect to the load; the first switch module is used to, based on the control of a first control signal, conduct the power supply voltage signal to the load in response to the first control signal switching from a first level to a second level to pre-charge the load; the pulse generating module is used to generate a control pulse signal in response to the first control signal switching from a first level to a second level; the second switch module is used to, based on the control of the control pulse signal, conduct within the pulse duration of the control pulse signal, conduct the power supply voltage signal to the load, and pre-charge the load together with the first switch module within the pulse duration; wherein the conduction current of the second switch module is greater than the conduction current of the first switch module. In this way, the second switch module uses a larger conduction current to pre-charge the load together with the first switch module within the pulse duration, which can shorten the pre-charging time. The second switch module can remain in the off state outside the pulse duration, thereby reducing the impact on the load.
[0037] Additional aspects and advantages of the embodiments of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through practice of the embodiments of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation of the present application. In the drawings:
[0039] Figure 1 A circuit diagram of a specific example of a pre-charging circuit;
[0040] Figure 2 This is one of the circuit block diagrams of the pre-charging circuit provided in an embodiment of the present application;
[0041] Figure 3 This is a second circuit block diagram of a pre-charging circuit provided in an embodiment of the present application;
[0042] Figure 4 The third circuit block diagram of the pre-charging circuit provided in an embodiment of the present application;
[0043] Figure 5This is one of the timing diagrams of the pre-charging circuit provided in an embodiment of the present application;
[0044] Figure 6 The second timing diagram of the pre-charging circuit provided in the embodiment of the present application;
[0045] Figure 7 This is a fourth circuit block diagram of a pre-charging circuit provided in an embodiment of the present application;
[0046] Figure 8 This is a fifth circuit block diagram of a pre-charging circuit provided in an embodiment of the present application;
[0047] Figure 9 The sixth circuit block diagram of the pre-charging circuit provided in an embodiment of the present application;
[0048] Figure 10 This is a seventh circuit block diagram of a pre-charging circuit provided in an embodiment of the present application;
[0049] Figure 11 This is the eighth circuit block diagram of the pre-charging circuit provided in an embodiment of the present application. DETAILED DESCRIPTION
[0050] To make the technical solutions and beneficial effects of the present invention more clearly understood, the following detailed description is given by way of specific embodiments. The accompanying drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly illustrate the details of the local features. Unless otherwise defined, the technical and scientific terms used herein have the same meanings as those in the technical field to which this application belongs.
[0051] The embodiments of the present application are not exhaustive, but are merely illustrative of some embodiments and are not intended to be a specific limitation on the scope of protection of the present application. In the absence of contradiction, each step in a certain embodiment can be implemented as an independent embodiment, and the steps can be arbitrarily combined. For example, a solution after removing some steps in a certain embodiment can also be implemented as an independent embodiment, and the order of the steps in a certain embodiment can be arbitrarily exchanged. In addition, the optional implementations in a certain embodiment can be arbitrarily combined; in addition, the embodiments can be arbitrarily combined. For example, some or all of the steps in different embodiments can be arbitrarily combined, and a certain embodiment can be arbitrarily combined with the optional implementations of other embodiments.
[0052] In each embodiment of the present application, unless otherwise specified or there is any logical conflict, the terms and / or descriptions between the embodiments are consistent and can be referenced by each other. The technical features in different embodiments can be combined to form a new embodiment based on their inherent logical relationships.
[0053] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application.
[0054] In the embodiments of the present application, unless otherwise specified, elements expressed in the singular, such as "a", "an", "the", "above", "said", "the", "the", etc., can mean "one and only one", or "one or more", "at least one", etc. For example, when using articles such as "a", "an", "the" in English in translation, the noun following the article can be understood as a singular expression or a plural expression.
[0055] In the embodiments of the present application, "plurality" refers to two or more.
[0056] In some embodiments, the terms "at least one", "one or more", "a plurality of", "multiple" and the like can be used interchangeably.
[0057] The prefixes such as "first" and "second" in the embodiments of the present application are only used to distinguish different description objects and do not limit the position, order, priority, value or content of the description objects. For the statement of the description objects, please refer to the description in the context of the claims or embodiments, and no unnecessary restrictions should be imposed due to the use of prefixes. For example, the numerical value of the description object is not limited by the ordinal number and can be one or more. Taking "first device" as an example, the numerical value of "device" can be one or more. In addition, the objects modified by different prefixes can be the same or different. For example, if the description object is "device", then the "first device" and the "second device" can be the same device or different devices, and their types can be the same or different.
[0058] In some embodiments, the term "connection" may indicate the transmission of electrical signals or data between a connected end and a connected end, and may be understood as "electrical connection," "communication connection," etc. A "connection" may be a direct connection between two components, an indirect connection established through other components, internal connectivity between two components, or any other possible connection form.
[0059] In some embodiments, terms such as "greater than", "greater than or equal to", "not less than", "more than", "more than or equal to", "not less than", "higher than", "higher than or equal to", "not less than", "above", and "exceed" can be replaced with each other, and terms such as "less than", "less than or equal to", "not greater than", "less than", "less than or equal to", "not more than", "lower than", "lower than or equal to", "not higher than", and "below" can be replaced with each other.
[0060] In addition, each element, each row, or each column in the table of the embodiment of the present disclosure can be implemented as an independent embodiment, and the combination of any elements, any rows, and any columns can also be implemented as an independent embodiment.
[0061] It should be noted that the transistors in the embodiments of the present application can be either N-type transistors or P-type transistors when there is no contradiction. For N-type transistors, the on-level is a high level and the off-level is a low level. That is, when the gate of the N-type transistor is at a high level, the input and output terminals are connected, and when the gate of the N-type transistor is at a low level, the input and output terminals are disconnected. For P-type transistors, the on-level is a low level and the off-level is a high level. That is, when the control terminal of the P-type transistor is at a low level, the input and output terminals are connected, and when the control terminal of the P-type transistor is at a high level, the input and output terminals are disconnected. In a specific implementation, the gate of each of the above-mentioned switching transistors serves as its control terminal. In the embodiments of the present application, the drain and source are determined according to the type of transistor: for N-type transistors, the drain can be used as the input terminal and the source as the output terminal; for P-type transistors, the source can be used as the input terminal and the drain as the output terminal. In addition, the on-level and off-level in the embodiment of the present invention are both general terms. The on-level refers to any level that can turn on the transistor, and the off-level refers to any level that can turn off / off the transistor.
[0062] Figure 1 This is a schematic diagram of a circuit for precharging the bit line of a storage unit in an NVM in the related art. Figure 1 As shown, when the bit line VBL in the NVM cell is precharged, control signal ENb turns on transistor PM1, which pulls up the bit line VBL in the NVM cell via the power signal VDD at the input terminal of transistor PM1. When the NVM cell does not pull down current, the bit line VBL is charged to approximately half the power signal VDD, allowing a 1 to be effectively read. When the NVM cell pulls down current, a 0 can be effectively read.
[0063] Due to design limitations of the memory cell, for example, the on-state current of transistor PM1 must be smaller than the pull-down current of the NVM memory cell. Therefore, the channel width to channel length ratio of transistor PM1 must be smaller than the channel width to channel length ratio of the transistors in the memory cell. Consequently, the on-state current (i.e., drain current) of transistor PM1 is relatively small.
[0064] In NVM storage circuit design, as the storage capacity continues to increase, the bit line load increases accordingly. Figure 1 As shown, capacitor Cx is the parasitic capacitance of the memory cell on the bit line. As the storage capacity continues to increase (that is, the number of memory cells continues to increase), the capacitor Cx continues to increase (that is, the bit line load continues to increase). When transistor PM1 is turned on, capacitor Cx needs to be charged to ensure that the voltage of bit line VBL reaches at least half of VDD. The on-state current (that is, the drain current) of transistor PM1 is small and fixed. Therefore, the larger the capacitor Cx, the longer it takes to charge, which in turn prolongs the charging time of bit line VBL, significantly affecting the effective read speed of NVM.
[0065] The present application embodiment provides a pre-charging circuit, such as Figure 2 As shown, the pre-charging circuit 10 includes: a first switch module 11, a second switch module 12 and a pulse generating module 13;
[0066] The input end of the first switch module 11 is used to connect to the power signal VDD, and the output end of the first switch module 11 is used to connect to the load; the input end of the second switch module 12 is used to connect to the power signal VDD, and the output end of the second switch module 12 is used to connect to the load;
[0067] The first switch module 11 is configured to conduct the power supply voltage signal to the load to pre-charge the load based on the control of the first control signal and in response to the first control signal switching from the first level to the second level;
[0068] The pulse generating module 13 is configured to generate a control pulse signal in response to the first control signal switching from the first level to the second level;
[0069] The second switch module 12 is configured to be turned on within the pulse duration of the control pulse signal based on the control pulse signal, and to conduct the power supply voltage signal to the load, so as to pre-charge the load together with the first switch module 11 within the pulse duration;
[0070] The conduction current of the second switch module 12 is greater than the conduction current of the first switch module 11 .
[0071] Here, the precharge circuit 10 can be applied to a nonvolatile memory.
[0072] In some embodiments, the load of the precharge circuit 10 is a bit line of a memory cell in a nonvolatile memory. The precharge circuit 10 can be used to precharge the bit line of the memory cell in the nonvolatile memory. For example, the precharge circuit 10 can be used to precharge the parasitic capacitance of the bit line (VBL) of the memory cell in the nonvolatile memory so that the bit line reaches a predetermined voltage.
[0073] In a possible implementation, the first level is a high level, and the second level is a low level.
[0074] The first control signal is Figure 2 As shown in ENb (in the drawings of the embodiments of this application, unless otherwise specified, ENb represents the first control signal, which will not be repeated hereafter). When the first control signal is at a first level, the first switch module 11 is turned off. When the first control signal is at a second level, the first switch module 11 is turned on. The power supply voltage signal can pre-charge the load through the first switch module 11. The first switch module 11 is turned on during the effective duration of the second level.
[0075] Here, the switch module is turned on by turning on the input and output of the switch module. The switch module is turned off by turning off the input and output of the switch module. The control terminal of the first switch module 11 is used to input the first control signal, and the control terminal of the second switch module 12 is used to input the control pulse signal.
[0076] In one possible implementation, precharging the load includes: precharging the load so that the load voltage reaches at least a predetermined voltage, for example, so that the load voltage reaches at least half of the voltage value of the power signal VDD.
[0077] In a possible implementation, the pulse duration of the control pulse signal is within a pre-charging period in which the load is pre-charged from an initial voltage to a predetermined voltage.
[0078] In one possible implementation, the pulse duration can be determined based on the on-current of the second switch module 12 so that the load (eg, bit line) can reach a certain voltage within the pulse duration. For example, the pulse duration can be 1-2 ns.
[0079] The pulse generating module 13 is specifically configured to generate a control pulse signal in response to the first control signal switching from a first level to a second level, and within a pre-charging period when the load is pre-charged from an initial voltage to a predetermined voltage; for example, the control pulse signal generated by the pulse generating module 13 is within a pre-charging period when the load is pre-charged from 0V to a predetermined voltage.
[0080] The control pulse signal generated by the pulse generating module 13 is used to turn on the second switch module 12 within the pulse duration (or pulse width), so that the power supply voltage signal can pre-charge the load through the second switch module 12 .
[0081] Here, the on-current of the second switch module 12 can be greater than the on-current of the first switch module 11. Therefore, a larger current can be used to pre-charge the load within the pulse duration, thereby increasing the pre-charging speed and shortening the time it takes for the load to reach the predetermined voltage.
[0082] In one possible implementation, the pulse generation module 13 may generate a control pulse signal based on an edge trigger when the first control signal switches from a first level to a second level. For example, the pulse generation module 13 may generate a control pulse signal based on a falling edge trigger when the first control signal switches from a first level to a second level.
[0083] In a possible implementation, the second switch module 12 is in an off state outside the pulse duration of the control pulse signal.
[0084] Exemplarily, the precharge circuit 10 is used to precharge the bit lines of a non-volatile memory. When the bit line voltage reaches a predetermined voltage, the bit line can be effectively read. During the precharge process, a first control signal switches from a first level to a second level, turning on the first switch module 11. The power supply signal VDD precharges the bit line through the first switch module 11. The switching of the first control signal from the first level to the second level triggers the control pulse signal generated by the pulse generation module 13 to turn on the second switch module 12 within the pulse duration. The power supply signal VDD precharges the bit line through the first switch module 11. During the precharge phase, the bit line is not read. Therefore, the precharge current is not limited. The second switch module 12 can use a larger current for precharging, thereby shortening the precharge duration and increasing the effective read speed of the NVM. The pulse duration of the control pulse signal is before the bit line voltage reaches a predetermined voltage (e.g., half the voltage value of the power supply signal VDD). Therefore, after the bit line voltage reaches the predetermined voltage, the first switch module 11 provides power, enabling effective readout. When the NVM memory cell has a pull-down current, it can effectively read out 0. Here, the conduction current of the first switch module 11 can be smaller than the pull-down current of the memory cell.
[0085] In this way, the second switch module 12 uses a larger conduction current to pre-charge the load together with the first switch module 11 during the pulse duration, thereby shortening the pre-charging time. The second switch module 12 can remain in the off state outside the pulse duration, thereby reducing the impact on the load.
[0086] In some embodiments, as Figure 3As shown, the first switch module 11 includes a third transistor PM1, wherein the control end of the third transistor PM1 is used to input the first control signal; the second switch module 12 includes a fourth transistor PM2, wherein the control end of the fourth transistor PM2 is used to input the control pulse signal.
[0087] In one possible implementation, the control end of the third transistor PM1 includes the gate of the third transistor PM1 , and the control end of the fourth transistor PM2 includes the gate of the fourth transistor PM2 .
[0088] Exemplarily, the third transistor PM1 and the fourth transistor PM2 are P-channel transistors. The first level is a high level, and the second level is a low level. When the first control signal is at a high level, the third transistor PM1 is turned off; when the first control signal switches from a high level to a low level, the third transistor PM1 is turned on. In response to the first control signal switching from the first level to the second level, the pulse generation module 13 generates a control pulse signal to control the fourth transistor PM2 to be turned on within the pulse duration. Here, the control pulse signal can be a low-level pulse signal. The pulse generation module 13 can output a high level beyond the pulse duration of the control pulse signal to turn off the fourth transistor PM2.
[0089] It can be understood that, here, the transistor being turned on may mean that the source and drain of the transistor are turned on, and the transistor being turned off may mean that the source and drain of the transistor are turned off.
[0090] In some embodiments, a first aspect ratio of a channel width of the third transistor PM1 to a channel length of the third transistor PM1 is greater than a second aspect ratio of a channel width of the fourth transistor PM2 to a channel length of the fourth transistor PM2 .
[0091] The aspect ratio between the channel width of the transistor and the channel length of the transistor is positively correlated with the on-state current (ie, drain current) of the transistor.
[0092] Here, in order to effectively read a 0 on the bit line when the NVM memory cell has a pull-down current, the on-current of the third transistor PM1 needs to be less than the pull-down current of the memory cell. Therefore, the first width-to-length ratio of the third transistor PM1 can be set to a smaller value. The fourth transistor PM2 can be turned on during the precharge phase without affecting the bit line reading. Therefore, the second width-to-length ratio of the fourth transistor PM2 can be set to a larger value. For example, the on-current of the fourth transistor PM2 can be set to 50 to 200 times the on-current of the third transistor PM1, such as 100 times. In this way, within the pulse duration, the fourth transistor PM2 can achieve high-current precharge, thereby shortening the precharge duration and increasing the speed of effective NVM reading.
[0093] In some embodiments, as Figure 4 As shown, the pulse generating module 13 includes: a first inverter INV1, a first delay 131 and an OR gate OR1, wherein,
[0094] The input end of the first inverter INV1 is used to input the first control signal, and the output end of the first inverter INV1 is used to output the second control signal;
[0095] The first delayer 131 is used to delay the second control signal;
[0096] The first input terminal of the OR gate OR1 is used to input the first control signal, the second input terminal of the OR gate OR1 is used to input the delayed second control signal, and the output terminal of the OR gate OR1 is used to output the control pulse signal.
[0097] Here, the delay of the first delay device 131 is positively correlated with the pulse duration of the control pulse signal. The first delay device 131 controls the on-time of the third transistor PM1 by delaying.
[0098] Combine Figure 4 The working principle of the pre-charge circuit 10 is described below. The timing diagram of the pre-charge circuit 10 is as follows: Figure 5 and Figure 6 As shown, Figure 6 for Figure 5 ENb is the signal curve of the first control signal, ENbD is the signal curve of the control terminal of the fourth transistor PM2, VBL represents the voltage change curve of the bit line, wherein the red curve of VBL is the voltage change curve of the bit line when the pre-charging circuit 10 of the embodiment of the present application is adopted, and the light blue curve of VBL is the voltage change curve of the bit line when the pre-charging circuit 10 of the embodiment of the present application is adopted. Figure 1 The voltage variation curve of the bit line when the precharge circuit 10 is shown.
[0099] like Figure 4 As shown, before precharging, the first level of the first control signal is high, so the third transistor PM1 is in the off state. The second control signal output by the first inverter INV1 is low. The first input terminal of the OR gate OR1 is high, and the second input terminal of the OR gate OR1 is low. Therefore, the output terminal of the OR gate OR1 outputs a high level to turn off the second transistor NM2.
[0100] When the precharge circuit 10 starts to precharge the bit line, the first control signal switches from the first level (high level) to the second level (low level), so the third transistor PM1 is in the on state and starts to precharge the bit line. The first input terminal of the OR gate OR1 is at a low level, and the second control signal output by the first inverter INV1 switches from a low level to a high level. However, due to the delay effect of the first delay device 131, the high level is delayed, and the second input terminal of the OR gate OR1 maintains a low level during the delay phase until the delay ends. During the delay phase of the first delay device 131, the first input terminal of the OR gate OR1 and the second terminal of the valve are both at a low level, thereby outputting a low-level control pulse signal at the output terminal of the OR gate OR1, thereby turning on the fourth transistor PM2 for precharging the bit line during the pulse duration of the control pulse signal. Figure 5 and Figure 6 As described above, during the pulse duration, since the fourth transistor PM2 has a large on-current, the bit line is quickly charged, and the voltage of the bit line rises to 1 / 4 of the voltage value of the power signal VDD during the pulse duration. Figure 1 The precharge curve of the precharge circuit 10 shown in FIG. 1 shows that after the precharge circuit 10 of the embodiment of the present application is used, the time required for the bit line voltage to reach the predetermined voltage is Figure 1 The charging time of the pre-charging circuit 10 is half of the charging time. This shows that within the pulse duration, the fourth transistor PM2 can achieve high current pre-charging, thereby shortening the pre-charging time and improving the speed of effective reading of the NVM.
[0101] In some embodiments, as Figure 7 As shown, the first delay device 131 includes a first capacitor C1,
[0102] The output end of the first inverter INV1, the first end of the first capacitor C1 and the second input end of the OR gate OR1 are connected, and the second end of the first capacitor C1 is used to connect to the power ground signal GND.
[0103] Here, the first capacitor C1 may be used to delay the second control signal.
[0104] Specifically, before precharging, the second control signal output by the first inverter INV1 is at a low level. That is, the first end of the first capacitor C1 is at a low level. When the precharge circuit 10 starts to precharge the bit line, the first control signal is switched from the first level to the second level (low level), and the second control signal output by the first inverter INV1 is switched from a low level to a high level. However, due to the energy storage function of the first capacitor C1, the level of the first end of the first capacitor C1 cannot change suddenly. The second control signal output by the first inverter INV1 needs to charge the capacitor, thereby generating a delay.
[0105] In this way, the second control signal is delayed by the first capacitor C1, thereby controlling the OR gate OR1 to generate a control pulse signal, so as to realize high current pre-charging of the fourth transistor PM2 within the pulse duration, thereby shortening the pre-charging time and improving the effective read speed of the NVM.
[0106] In some embodiments, as Figure 8 As shown, the first delay device 131 includes a first transistor NM1,
[0107] The output end of the first inverter INV1, the control end of the first transistor NM1 and the second input end of the OR gate OR1 are connected, and the input end of the first transistor NM1 and the output end of the first transistor NM1 are used to connect to the power ground signal GND.
[0108] Here, the first transistor NM1 may be used to implement a capacitance characteristic to delay the second control signal.
[0109] In one possible implementation, the first transistor NM1 may be an N-channel transistor. The input terminal of the first transistor NM1 may be the drain of the N-channel transistor, the output terminal of the first transistor NM1 may be the source of the N-channel transistor, and the control terminal of the first transistor NM1 may be the gate of the N-channel transistor. The control terminal of the first transistor NM1 constitutes a first terminal of the capacitor, and the input terminal of the first transistor NM1 and the output terminal of the first transistor NM1 are connected to the power ground signal GND, constituting the second terminal of the capacitor.
[0110] Specifically, such as Figure 8 As shown, before precharging, the second control signal output by the first inverter INV1 is at a low level. That is, the control terminal of the first transistor NM1 is at a low level. When the precharging circuit 10 starts to precharge the bit line, the first control signal is switched from the first level to the second level (low level), and the second control signal output by the first inverter INV1 is switched from a low level to a high level. However, due to the energy storage of the capacitor, the level of the control terminal of the first transistor NM1 cannot change suddenly. The second control signal output by the first inverter INV1 needs to charge the capacitor, thereby generating a delay.
[0111] In this way, the capacitor formed by the first transistor NM1 realizes the delay of the second control signal, and then controls the OR gate OR1 to generate a control pulse signal, so as to realize the large current pre-charging of the fourth transistor PM2 within the pulse duration, thereby shortening the pre-charging time and improving the effective reading speed of the NVM.
[0112] In some embodiments, as Figure 9As shown, the pulse generating module 13 includes: a second inverter INV2, a third inverter INV3, a second delay 132, an AND gate AND1 and a fourth inverter INV4, wherein,
[0113] The input terminal of the second inverter INV2 is used to input the first control signal;
[0114] The output end of the second inverter INV2, the input end of the third inverter INV3 and the first input end of the AND gate AND1 are connected;
[0115] The output end of the third inverter INV3 is used to output a third control signal;
[0116] The second delayer 132 is used to delay the third control signal;
[0117] The second input terminal of the AND gate AND1 is used to input the delayed third control signal;
[0118] The output end of the AND gate AND1 is connected to the input end of the fourth inverter INV4 , and the output end of the fourth inverter INV4 is used to output the control pulse signal.
[0119] Here, the delay of the second delay device 132 is positively correlated with the pulse duration of the control pulse signal. The second delay device 132 controls the on-time of the third transistor PM1 by delaying.
[0120] Combine Figure 9 The working principle of the pre-charge circuit 10 is described below. The timing diagram of the pre-charge circuit 10 is as follows: Figure 5 and Figure 6 As shown, Figure 6 for Figure 5 ENb is the signal curve of the first control signal, ENbD is the signal curve of the control terminal of the fourth transistor PM2, VBL represents the voltage change curve of the bit line, wherein the red curve of VBL is the voltage change curve of the bit line when the pre-charging circuit 10 of the embodiment of the present application is adopted, and the light blue curve of VBL is the voltage change curve of the bit line when the pre-charging circuit 10 of the embodiment of the present application is adopted. Figure 1 The voltage variation curve of the bit line when the precharge circuit 10 is shown.
[0121] like Figure 9As shown, before precharging, the first level of the first control signal is high, thus turning off the third transistor PM1. The second inverter outputs a low level to the first input of the AND gate AND1 and the input of the third inverter INV3. The first input of the AND gate AND1 is low, and the output of the AND gate AND1 or the OR gate OR1 outputs a low level to the fourth inverter INV4. The fourth inverter INV4 outputs a high level to turn off the second transistor NM2. The third control signal outputted by the output of the third inverter INV3 is high.
[0122] When the precharge circuit 10 starts to precharge the bit line, the first control signal switches from the first level to the second level (low level), so the third transistor PM1 is in the on state and starts to precharge the bit line. The second inverter outputs a high level to the first input terminal of the AND gate AND1 and the input terminal of the third inverter INV3, and the first input terminal of the AND gate AND1 is a high level. The third control signal output by the third inverter switches from a high level to a low level. However, due to the delay effect of the second delay 132, the low level is delayed, and the second input terminal of the AND gate AND1 maintains a high level during the delay stage until the delay ends. During the delay stage of the second delay 132, the first input terminal of the AND gate AND1 and the second terminal of the AND gate AND1 are both high levels, thereby outputting a high-level pulse signal at the output terminal of the AND gate AND1. The high-level pulse signal passes through the fourth inverter INV4 to generate a control pulse signal of the second level, thereby turning on the fourth transistor PM2 for precharging the bit line during the pulse duration of the control pulse signal. Figure 5 and Figure 6 As described above, during the pulse duration, since the fourth transistor PM2 has a large on-current, the bit line is quickly charged, and the voltage of the bit line rises to 1 / 4 of the voltage value of the power signal VDD during the pulse duration. Figure 1 The precharge curve of the precharge circuit 10 shown in FIG. 1 shows that after the precharge circuit 10 of the embodiment of the present application is used, the time required for the bit line voltage to reach the predetermined voltage is Figure 1 The charging time of the pre-charging circuit 10 is half of the charging time. This shows that within the pulse duration, the fourth transistor PM2 can achieve high current pre-charging, thereby shortening the pre-charging time and improving the speed of effective reading of the NVM.
[0123] In some embodiments, as Figure 10 As shown, the second delay device 132 includes a second capacitor C2,
[0124] The output end of the third inverter INV3, the first end of the second capacitor C2 and the second input end of the AND gate AND1 are connected, and the second end of the second capacitor C2 is used to connect to the power ground signal GND.
[0125] Here, the second capacitor C2 may be used to delay the second control signal.
[0126] Specifically, before precharging, the third control signal output by the third inverter is at a high level. That is, the first end of the second capacitor C2 is at a high level. When the precharge circuit 10 begins to precharge the bit line, the first control signal switches from the first level to the second level (low level), and the second control signal output by the third inverter switches from a high level to a low level. However, due to the energy storage function of the second capacitor C2, the level of the first end of the second capacitor C2 cannot change suddenly. The capacitor needs to discharge to the output end of the third inverter, thereby generating a delay.
[0127] In this way, the delay of the third control signal is achieved through the second capacitor C2, and then the AND gate AND1 is controlled to generate a pulse signal, and then the control pulse signal is generated through the fourth inverter INV4, so that the fourth transistor PM2 is pre-charged with a large current within the pulse duration, thereby shortening the pre-charging time and improving the effective read-out speed of the NVM.
[0128] In some embodiments, as Figure 11 As shown, the second delay device 132 includes a second transistor NM2,
[0129] The output end of the third inverter INV3, the control end of the second transistor NM2 and the second input end of the AND gate AND1 are connected, and the input end of the second transistor NM2 and the output end of the second transistor NM2 are used to connect to the power ground signal GND.
[0130] Here, the second transistor NM2 may be used to implement a capacitance characteristic to delay the second control signal.
[0131] In one possible implementation, the second transistor NM2 may be an N-channel transistor. The input terminal of the second transistor NM2 may be the drain of the N-channel transistor, the output terminal of the second transistor NM2 may be the source of the N-channel transistor, and the control terminal of the second transistor NM2 may be the gate of the N-channel transistor. The control terminal of the second transistor NM2 constitutes a first terminal of the capacitor, and the input terminal of the second transistor NM2 and the output terminal of the second transistor NM2 are connected to the power ground signal GND, constituting the second terminal of the capacitor.
[0132] Specifically, before precharging, the third control signal output by the third inverter is at a high level. That is, the control terminal of the second transistor NM2 is at a high level. When the precharge circuit 10 begins to precharge the bit line, the first control signal switches from the first level to the second level (low level), and the second control signal output by the third inverter switches from a high level to a low level. However, due to the energy storage effect of the capacitor, the level of the control terminal of the second transistor NM2 cannot change suddenly. The capacitor needs to discharge the output terminal of the third inverter, thereby generating a delay.
[0133] In this way, the delay of the third control signal is realized by the second transistor NM2, and then the AND gate AND1 is controlled to generate a pulse signal, and then the control pulse signal is generated by the fourth inverter INV4, so that the fourth transistor PM2 is pre-charged with a large current within the pulse duration, thereby shortening the pre-charging time and improving the effective read-out speed of the NVM.
[0134] A specific example of a pre-charging circuit 10 is provided in combination with the above embodiments.
[0135] The precharge circuit 10 is as follows Figure 8 As shown, the pulse generating module 13 and the fourth transistor PM2 are used in conjunction with each other to increase the charging speed of the NVM bit line VBL, thereby increasing the read speed of the large-capacity NVM.
[0136] The pulse generation module 13 is primarily controlled by the ENb signal (the first control signal). It passes through logic gates (the first inverter INV1 and the OR gate OR1) and a first delay 131 to generate a short control pulse signal. This control pulse signal is generated immediately following the falling edge of the ENb signal. Here, the technique adds a PMOS pull-up transistor (the fourth transistor PM2) and two logic gates: the first inverter INV1 and the OR gate OR1. An NMOS transistor (the first transistor NM1) acts as a capacitor to generate a control pulse signal (with a zero level duration of approximately 1-2 ns).
[0137] The fourth transistor PM2 is turned on under the control of the control pulse signal generated by the pulse generating module 13, generating a large transient charging current for the pull-up of the NVM, thereby shortening the charging time of the NVM bit line VBL and the read time of the NVM memory.
[0138] The purpose of the present example precharge circuit 10 is to Figure 8The pulse generation module 13 shown generates a control pulse signal (level 0 duration of approximately 1-2 ns) following the ENb signal. This signal controls the fourth transistor PM2 (PMOS transistor) to turn on. After the fourth transistor PM2 turns on, it directly pulls the voltage to a position of VDD / 4 within this short time of 1-2 ns. The voltage continues to charge from VDD / 4 to approximately VDD / 2, and then flips to read DOUT as 1. The timing is as follows: Figure 5 and Figure 6 shown.
[0139] An embodiment of the present application further provides a non-volatile memory, the non-volatile memory comprising: a storage unit and a pre-charging circuit;
[0140] Wherein, the load of the precharge circuit is the bit line of the memory cell.
[0141] Here, the specific implementation manner of the pre-charging circuit is as described in any of the above embodiments and will not be repeated here.
[0142] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.
[0143] Throughout this specification, references to "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" mean that a specific feature, structure, material, or characteristic described in conjunction with an embodiment or example is included in at least one embodiment or example of the present application. In this specification, illustrative references to the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
[0144] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.
Claims
1. A pre-charging circuit, characterized in that: The pre-charging circuit includes: a first switch module, a second switch module and a pulse generating module; The input end of the first switch module is used to connect to the power signal, and the output end of the first switch module is used to connect to the load; the input end of the second switch module is used to connect to the power signal, and the output end of the second switch module is used to connect to the load; The first switch module is configured to, based on the control of a first control signal, conduct the power supply voltage signal to the load to pre-charge the load in response to the first control signal switching from a first level to a second level; The pulse generating module is configured to generate a control pulse signal in response to the first control signal switching from a first level to a second level; The second switch module is configured to be turned on within the pulse duration of the control pulse signal based on the control of the control pulse signal, and to conduct the power supply voltage signal to the load, so as to pre-charge the load together with the first switch module within the pulse duration; The conduction current of the second switch module is greater than the conduction current of the first switch module.
2. The precharge circuit according to claim 1, wherein The pulse generation module includes: a first inverter, a first delay device and an OR gate, wherein: The input terminal of the first inverter is used to input the first control signal, and the output terminal of the first inverter is used to output the second control signal; The first delay device is used to delay the second control signal; The first input end of the OR gate is used to input the first control signal, the second input end of the OR gate is used to input the delayed second control signal, and the output end of the OR gate is used to output the control pulse signal.
3. The precharge circuit according to claim 2, wherein The first delay device includes a first transistor, The output terminal of the first inverter, the control terminal of the first transistor and the second input terminal of the OR gate are connected, and the input terminal of the first transistor and the output terminal of the first transistor are used to connect to a power ground signal.
4. The precharge circuit according to claim 2, wherein The first delay device includes a first capacitor, The output terminal of the first inverter, the first terminal of the first capacitor and the second input terminal of the OR gate are connected, and the second terminal of the first capacitor is used to connect to a power ground signal.
5. The precharge circuit according to claim 1, wherein: The pulse generating module includes: a second inverter, a third inverter, a second delay device, an AND gate and a fourth inverter, wherein: The input terminal of the second inverter is used to input the first control signal; The output terminal of the second inverter, the input terminal of the third inverter and the first input terminal of the AND gate are connected; The output terminal of the third inverter is used to output a third control signal; The second delay device is used to delay the third control signal; The second input terminal of the AND gate is used to input the delayed third control signal; The output end of the AND gate is connected to the input end of the fourth inverter, and the output end of the fourth inverter is used to output the control pulse signal.
6. The precharge circuit according to claim 5, wherein: The second delay device includes a second transistor, The output terminal of the third inverter, the control terminal of the second transistor and the second input terminal of the AND gate are connected, and the input terminal of the second transistor and the output terminal of the second transistor are used to connect to a power ground signal.
7. The precharge circuit according to claim 5, wherein: The second delay device includes a second capacitor, The output terminal of the third inverter, the first terminal of the second capacitor and the second input terminal of the AND gate are connected, and the second terminal of the second capacitor is used to connect to a power ground signal.
8. The pre-charging circuit according to any one of claims 1 to 7, characterized in that: The first switch module includes a third transistor, wherein the control terminal of the third transistor is used to input the first control signal; The second switch module includes a fourth transistor, wherein the control terminal of the fourth transistor is used to input the control pulse signal.
9. The precharge circuit according to claim 8, wherein: A first aspect ratio of a channel width of the third transistor to a channel length of the third transistor is greater than a second aspect ratio of a channel width of the fourth transistor to the channel length of the fourth transistor.
10. The pre-charging circuit according to any one of claims 1 to 7, characterized in that: The load of the precharge circuit is a bit line of a storage unit in a nonvolatile memory.
11. A non-volatile memory, characterized in that: The non-volatile memory comprises: a memory unit and a pre-charge circuit according to any one of claims 1 to 10; Wherein, the load of the precharge circuit is the bit line of the memory cell.