Semiconductor memory device and method of controlling authentication operation thereof

Abstract

The invention relates to a semiconductor memory device and a method of controlling a verify operation thereof. The semiconductor memory device includes a plurality of bit lines, a plurality of page buffers, and a page buffer control circuit. Each of the plurality of page buffers is coupled with the plurality of bit lines and operates in response to the plurality of page buffer control signals. The page buffer control circuitry generates a plurality of page buffer control signals to perform program and verify operations including a plurality of loops. The page buffer control circuit simultaneously pre-charges bit lines coupled to page buffers among a plurality of page buffers using a plurality of page buffer control signals, the page buffers among the plurality of page buffers corresponding to a plurality of verify levels corresponding to each of a plurality of cycles.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Application No. 10-2024-0029800 filed on February 29, 2024, in the Korean Intellectual Property Office, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Various embodiments relate generally to a semiconductor circuit, and more particularly, to a semiconductor memory device and a method for controlling a verification operation of the semiconductor memory device. Background Art

[0004] A typical semiconductor memory device, such as a flash memory, requires program and verify operations as well as a read operation to store data.

[0005] The programming operation may include a sub-programming operation for increasing the threshold voltage of the memory cells included in the memory block, and a verification operation for determining whether the threshold voltage of the memory cells has reached a target voltage. The programming operation may be performed using an incremental step pulse programming (ISPP) method, in which the programming voltage applied to the word lines connected to the memory cells is gradually increased. For example, the sub-programming operation and the verification operation may form a single loop, and the programming operation may be performed in multiple loops. The programming voltage may be increased by a step voltage with each loop.

[0006] The read operation may include sensing the memory cell using a read voltage and outputting the sensed data from the memory cell to an external device. The external device may be a controller that sends commands and addresses to the memory device.

[0007] To further increase the integration density of flash memory, multi-bit cells, which allow multiple data to be stored in a single memory cell, are being actively researched. A memory cell can store one, two, or more bits of data, depending on how it is programmed. For example, when one bit of data is stored in a memory cell, it is called a single-level cell method; when two bits of data are stored in a memory cell, it is called a multi-level cell (MLC) method; when three bits of data are stored in a memory cell, it is called a triple-level cell method; and when four bits of data are stored in a memory cell, it is called a quad-level cell method. Furthermore, more than four bits of data can be stored in a single memory cell.

[0008] Figure 1 This is a typical 2-bit MLC threshold voltage distribution diagram.

[0009] Reference Figure 1, shows that the threshold voltage distribution diagram of an MLC capable of storing 2-bit data is divided into four distributions. It represents the threshold voltage distributions of the unprogrammed state

[11] and the programmed states

[01] ,

[00] , and

[10] .

[0010] In state

[01] , a first sub-verification operation is performed using a first verification level PV1 (i.e., a verification voltage of the first level) to verify whether the programming operation has passed or failed. In state

[00] , a second sub-verification operation is performed using a second verification level PV2 (i.e., a verification voltage of the second level higher than the first level) to verify whether the programming operation has passed or failed. In state

[10] , a third sub-verification operation is performed using a third verification level PV3 (i.e., a verification voltage of the third level higher than the second level) to verify whether the programming operation has passed or failed. On the other hand, memory cells whose threshold voltage distribution is in state

[11] do not require a verification operation because they have not yet been programmed or have been erased after programming. However, for ease of explanation, the verification level corresponding to the memory cells whose threshold voltage distribution is in state

[11] will be referred to as no verification level PV0.

[0011] This programming method is a programming method using Gray code, which means a method of programming so that only one bit among the bits including data changes. Figure 1 In the case of a single-shot programming, only the value "1" changes to "0", and only one bit can be changed using single-shot programming. This applies not only to two bits, but also to MLCs that can store n bits, so even if an error occurs in a single cell, at least one bit will change, which is why the Gray code method is used.

[0012] Figure 2 is a diagram illustrating conventional program and verification operations.

[0013] Reference Figure 2 , a conventional programming operation may include a plurality of loops LP1, LP2, ..., LP15, .... These loops are performed until the threshold voltage of the selected memory cell reaches a target voltage, and if the verification voltage fails before the number of executed loops reaches a threshold, the selected memory block is deemed a bad block.

[0014] Each loop includes a sub-programming operation and a main verification operation. Taking the first loop LP1 as an example, the first loop LP1 includes a first sub-programming operation PGM1 and a first main verification operation MV1. In the first sub-programming operation PGM1, a program voltage is applied to the selected word line WL to increase the threshold voltage of the memory cell.

[0015] In the first main verification operation MV1 , a plurality of sub-verification operations, for example, a first sub-verification operation and a second sub-verification operation using a first verification level PV1 and a second verification level PV2 , respectively, are performed.

[0016] After the first main verification operation MV1, other loops are sequentially performed. For example, in the seventh loop LP7, the seventh sub-programming operation PGM7 and the seventh main verification operation MV7 are performed. In the seventh main verification operation MV7, the first to third sub-verification operations are performed using the first verification level PV1, the second verification level PV2, and the third verification level PV3, respectively.

[0017] The plurality of loops LP1, LP2, ..., LP15, ... are executed in the above-described manner.

[0018] In order to perform each main verification operation included in the plurality of loops LP1 , LP2 , . . . , LP15 , . . . , a bit line precharge operation is required, and one of a full bit line precharge method and a selected bit line sequential precharge method is used.

[0019] The all-bitline precharge method precharges all bitlines regardless of the number of verify levels. Specifically, for the first main verify operation MV1, only the first verify level PV1 and the second verify level PV2 are used. However, all bitlines corresponding to the first to third verify levels PV1-PV3, as well as the bitline corresponding to the no-verify level PV0, are included. Therefore, the all-bitline precharge method increases current consumption by precharging all bitlines, resulting in a decrease in operational performance due to peak current.

[0020] The method of selecting a sequential pre-charge of the bit lines performs pre-charging and discharging on each sub-verification operation in sequence. For example, in the first sub-verification operation of the seventh loop LP7, only the bit lines corresponding to the first verification level PV1 are selected from all the bit lines for pre-charging and discharging after verification. Then, in the second sub-verification operation, only the bit lines corresponding to the second verification level PV2 are selected from all the bit lines for pre-charging and discharging after verification. Then, in the third sub-verification operation, only the bit lines corresponding to the third verification level PV3 are selected from all the bit lines for pre-charging and discharging after verification. The above operation is repeated for each of the multiple loops LP1, LP2, ..., LP15, .... Therefore, the method of selecting a sequential pre-charge of the bit lines increases the bit line setup time by only selecting the bit lines corresponding to the verification level and repeating the pre-charging and discharging. As the memory capacity increases, the bit line setup time further increases, and ultimately the verification time increases, thereby reducing the product operating performance. Summary of the Invention

[0021] In an embodiment, a semiconductor memory device may include a plurality of bit lines, a plurality of page buffers, and a page buffer control circuit. Each of the plurality of page buffers may be coupled to the plurality of bit lines and may be configured to operate in response to a plurality of page buffer control signals. The page buffer control circuit may be configured to generate the plurality of page buffer control signals to perform a program and verify operation comprising a plurality of cycles. The page buffer control circuit may be configured to simultaneously precharge the bit lines coupled to the page buffers among the plurality of page buffers using the plurality of page buffer control signals, the page buffers among the plurality of page buffers corresponding to a plurality of verify levels, the plurality of verify levels corresponding to each of the plurality of cycles.

[0022] In an embodiment, a semiconductor memory device may include a bit line, a data latch group, a sensing information latch, a backup latch, a precharge selection information latch, and a page buffer control circuit. The bit line may be coupled to a sensing node via at least one switch. The data latch group may be coupled to the sensing node and may include multiple data latches, each of the multiple data latches being configured to store at least one bit of data. The sensing information latch may be coupled to the sensing node and may be configured to store, as sensing information, whether multiple sub-verification operations corresponding to multiple verification levels have passed or failed. The backup latch may be coupled to the sensing node and may be configured to store the sensing information as backup information. The precharge selection information latch may be coupled to the sensing node and may be configured to store precharge selection information. The page buffer control circuit may be configured to control the data latch group and the backup latch so that the backup information is reset according to data, may be configured to control the backup latch and the precharge selection information latch so that the backup information is stored as precharge selection information, and may be configured to control at least one switch to precharge the bit line according to the precharge selection information.

[0023] In an embodiment, a semiconductor memory device may include a plurality of bit lines, a plurality of page buffers, and a page buffer control circuit. The sensing nodes of the plurality of page buffers may be coupled to the plurality of bit lines via at least one switch. The plurality of page buffers may be configured to store data, backup information, sensing information, and precharge selection information in response to a plurality of page buffer control signals. The page buffer control circuit may be configured to generate a plurality of page buffer control signals to perform programming and verification operations including a plurality of cycles. The page buffer control circuit may be configured to perform a bit line set operation, the bit line set operation including at least one of a preliminary set operation and a main set operation to select a page buffer corresponding to a plurality of verification levels from among the plurality of page buffers, and the page buffer control circuit may be configured to perform a plurality of sub-verification operations using each of the plurality of verification levels, while simultaneously precharging the bit lines from the plurality of bit lines coupled to the page buffers corresponding to the plurality of verification levels.

[0024] In an embodiment, a method for controlling a verification operation of a semiconductor memory device, the semiconductor memory device comprising: a plurality of bit lines; a plurality of page buffers, each page buffer being connected to the plurality of bit lines and configured to store data, backup information, sensing information, and precharge selection information; and a page buffer control circuit configured to control the plurality of page buffers to perform programming and verification operations comprising a plurality of cycles, the method may include: performing a preliminary set operation based on data resetting backup information; performing a main set operation to store the backup information as precharge selection information; and performing a simultaneous precharge operation of selecting bit lines according to the precharge selection information to simultaneously precharge the bit lines connected to the page buffers among the plurality of page buffers, the page buffers among the plurality of page buffers corresponding to a plurality of verification levels, the plurality of verification levels corresponding to each of the plurality of cycles. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is a typical 2-bit MLC threshold voltage distribution diagram.

[0026] Figure 2 is a diagram illustrating conventional program and verification operations.

[0027] Figure 3 is a diagram illustrating a configuration of a semiconductor memory device according to an embodiment of the present disclosure.

[0028] Figure 4 It shows Figure 3 Schematic diagram of an embodiment of a connection configuration of memory blocks included in a plane.

[0029] Figure 5 It shows Figure 3 A diagram of an embodiment of a configuration of a page buffer.

[0030] Figure 6 yes Figure 5 A diagram of an embodiment of data stored in a page buffer and verification levels.

[0031] Figure 7 is a diagram illustrating program and verification operations according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] Various embodiments of the present disclosure may improve operation performance by reducing current consumption and verification time due to a bit line precharge operation.

[0033] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0034] Figure 3 is a diagram illustrating a configuration of a semiconductor memory device 100 according to an embodiment of the present disclosure.

[0035] Reference Figure 3 , the semiconductor memory device 100 may include a memory cell array 110 , a peripheral circuit 170 , and a control circuit 180 .

[0036] The memory cell array 110 may include at least one plane. For example, the memory cell array 110 may include first to k-th planes PL1-PLk. Each of the first to k-th planes PL1-PLk may include a memory block. The memory block may be formed in a two-dimensional structure or a three-dimensional structure. A memory block with a two-dimensional structure may include memory cells arranged parallel to a substrate. A memory block with a three-dimensional structure may include memory cells stacked perpendicular to the substrate. Depending on the programming method, the memory cell may store one, two, or more bits of data.

[0037] The peripheral circuit 170 may be configured to perform a program operation to store data in the memory cell array 110, a read operation to output data stored in the memory cell array 110, and an erase operation to erase data stored in the memory cell array 110. For example, the peripheral circuit 170 may include a voltage generator 120, a row decoder group 130, a page buffer group 140, a column decoder 150, and an input / output circuit 160.

[0038] The voltage generator 120 can generate various operating voltages VOP for programming, reading, or erasing operations in response to an operation code OPCD. For example, the voltage generator 120 can be configured to generate a program voltage, a pass voltage, a turn-on voltage, a turn-off voltage, a ground voltage, a verify voltage, a read voltage, an erase voltage, and the like in response to the operation code OPCD. A program voltage is a voltage applied to a selected word line during a programming operation, which can be used to increase the threshold voltage of a memory cell. A pass voltage is a voltage applied to unselected word lines during a programming or read operation, which can be used to turn on unselected memory cells. An turn-on voltage is a voltage applied to a drain select line or a source select line, which can be used to turn on a drain select transistor or a source select transistor. A turn-off voltage is a voltage applied to a drain select line or a source select line, which can be used to turn off a drain select transistor or a source select transistor. The ground voltage can be zero voltage. A verify voltage is a voltage applied to a selected word line or all word lines connected to a selected memory block during a programming or erase operation to determine the threshold voltage of a selected memory cell. The read voltage is the voltage applied to the select word line during a read operation, which can be used to determine the data stored in the memory cell. The erase voltage is the voltage applied to the source line during an erase operation, which can be used to lower the threshold voltage of the memory cell.

[0039] The row decoder group 130 can be configured to transmit the operating voltage VOP to the local line LCL connected to the selected memory block according to the row address RADD. For example, the row decoder group 130 can be connected to the voltage generator 120 via a global line and connected to the first to kth planes PL1-PLk via the local line LCL. The row decoder group 130 may include a plurality of row decoders (not shown), each of which is connected to the first to kth planes PL1-PLk. Each of the plurality of row decoders (not shown) can be connected to the memory block included in the first to kth planes PL1-PLk via the local line LCL. The local line LCL may include a drain select line, a word line, a source select line, and a source line.

[0040] Page buffer group 140 may include multiple page buffers PB1-PBn. The multiple page buffers PB1-PBn may have the same circuit configuration. The multiple page buffers PB1-PBn may be connected to memory cell array 110 via multiple bit lines BL. The multiple page buffers PB1-PBn may adjust the voltage levels applied to the multiple bit lines BL and the duration of the voltage application to the bit lines BL in response to multiple page buffer control signals PBSIG. The multiple page buffers PB1-PBn may store externally provided data in response to the multiple page buffer control signals PBSIG. Among the multiple page buffers PB1-PBn, the page buffers corresponding to the remaining sub-verification operations other than the verified sub-verification operation may simultaneously precharge the bit lines connected thereto. The multiple page buffers PB1-PBn may determine the corresponding sub-verification operation based on the stored data. In response to the multiple page buffer control signals PBSIG, the multiple page buffers PB1-PBn may precharge the corresponding bit lines by applying a precharge voltage to the corresponding bit lines for each sub-verification operation.

[0041] Column decoder 150 may be configured to transfer data between page buffer group 140 and input / output circuit 160 in response to column address CADD. For example, column decoder 150 may be coupled to page buffer group 140 via column lines CL and to input / output circuit 160 via data lines DL.

[0042] The input / output circuit 160 may transfer a command CMD and an address ADD received from an external device (e.g., a controller) to the control circuit 180. In a program operation, the input / output circuit 160 may transfer data received from the external device to the column decoder 150. In a read operation, the input / output circuit 160 may output data received from the column decoder 150 to the external device.

[0043] The control circuit 180 can output an operation code OPCD, a row address RADD, a page buffer control signal PBSIG, and a column address CADD in response to a command CMD and an address ADD. When the input command CMD specifies an erase operation, the control circuit 180 can control the peripheral circuit 170 to perform an erase operation on the memory block selected by the address ADD. If the input command CMD specifies a read operation, the control circuit 180 can control the peripheral circuit 170 to perform a read operation on the memory block selected by the address and output the read data. When the input command CMD specifies a program operation, the control circuit 180 can control the peripheral circuit 170 to perform program and verify operations on the selected memory block.

[0044] The control circuit 180 may include a page buffer control circuit 180A. In response to a command CMD, the page buffer control circuit 180A may generate a page buffer control signal PBSIG to adjust the voltage level applied to the bit line BL or the duration of applying the voltage to the bit line BL. The page buffer control signal PBSIG may include various signals for adjusting the voltage applied to the bit line BL and the circuits included in the plurality of page buffers PB1-PBn.

[0045] The page buffer control circuit 180A may adjust the page buffer control signal PBSIG so that an erase voltage is applied to the bit line BL during an erase operation. The page buffer control circuit 180A may adjust the page buffer control signal PBSIG so that a precharge voltage is applied to the bit line BL.

[0046] The page buffer control circuit 180A may adjust the value of the page buffer control signal PBSIG so that a program enable voltage is applied to a selected bit line among the bit lines BL and a program inhibit voltage is applied to unselected bit lines during a program operation.

[0047] The page buffer control circuit 180A can control a program operation determined by data and a main verification operation including a plurality of sub-verification operations. The page buffer control circuit 180A can use a page buffer control signal PBSIG to control the page buffers corresponding to the remaining sub-verification operations among the plurality of page buffers PB1-PBn except for the verified sub-verification operation to simultaneously precharge the bit lines connected thereto.

[0048] Figure 4 The first to m-th memory blocks BLK1 -BLKm included in the first plane PL1 are used as an example to illustrate Figure 3 Schematic diagram of a connection configuration of storage blocks included in a plane.

[0049] Reference Figure 4 , each of the first to mth memory blocks BLK1-BLKm can be connected to a first row decoder 130a through a local line LCL, and the first row decoder 130a is one of the plurality of row decoders included in the row decoder group 130. The first to mth memory blocks BLK1-BLKm can be commonly connected to a plurality of bit lines BL1-BLn. The first row decoder 130a can transmit an operating voltage through the local line LCL connected to a selected memory block among the first to mth memory blocks BLK1-BLKm in response to a row address RADD. When a program, read, or erase operation is performed on the selected memory block, the first row decoder 130a can float the local line LCL connected to the unselected memory block. The local line LCL may include a drain select line, a word line, a source select line, and a source line, and may further include a dummy line.

[0050] Figure 5 It shows Figure 3 FIG. 1 is a diagram illustrating a configuration of the page buffer PB1.

[0051] Reference Figure 5 The page buffer PB1 may include a data latch group 210 , 220 , a backup latch 230 , a sensing information latch 240 , a precharge selection information latch 250 , and a plurality of switches, eg, first to eighth switches 261 - 268 .

[0052] The data latch group 210 , 220 , the backup latch 230 , the sensing information latch 240 , the precharge selection information latch 250 , and the first to eighth switches 261 - 268 may operate in response to the page buffer control signal PBSIG.

[0053] The first switch 261 can be coupled between the power supply terminal VCORE and the sense node SO and can be turned on in response to a first precharge control signal PRECHSO_N. When the first precharge control signal PRECHSO_N is at a first logic level, such as a low level, the first switch 261 can precharge the sense node SO to the voltage level of the power supply terminal VCORE. In the above description, an example is given where the first logic level is a low level, but the first logic level is not limited to a low level or a high level, but can vary according to the circuit design. For ease of description, the following discussion will assume that the first logic level is a low level and the second logic level is a high level.

[0054] The second switch 262 and the third switch 263 may be coupled between the power supply terminal VCORE and the sense node SO. The second switch 262 may be turned on based on the logic level of the latch node QS of the precharge selection information latch 250. The third switch 263 may be turned on based on the logic level of the second precharge control signal SA_PRECH_N. When the latch node QS of the precharge selection information latch 250 and the second precharge control signal SA_PRECH_N are both at a low logic level, the second switch 262 and the third switch 263 may precharge the sense node SO to the voltage level of the power supply terminal VCORE.

[0055] The fourth switch 264 may be coupled between the first node ND1 and the second node ND2. The first node ND1 and the second node ND2 may have the same potential as the sensing node SO, differing only in physical location. The fourth switch 264 may be turned on in response to the first sensing control signal SA_SENSE. When the first sensing control signal SA_SENSE is at a high level, the fourth switch 264 may connect the first node ND1 and the second node ND2.

[0056] The fifth switch 265 may be coupled between the third node ND3 and the bit line BL. The fifth switch 265 may be turned on in response to the second sensing control signal PB_SENSE. The third node ND3 may have the same potential as the sensing node SO, differing only in physical position.

[0057] The sixth switch 266 and the seventh switch 267 may be coupled between the third node ND3 and the power supply terminal VCORE. The sixth switch 266 may be turned on based on the logic level of the third sensing control signal SA_CSOC. The seventh switch 267 may be turned on based on the logic level of the latch node QS of the precharge selection information latch 250. When the third sensing control signal SA_CSOC is at a high level and the logic level of the latch node QS of the precharge selection information latch 250 is at a high level, the sixth switch 266 and the seventh switch 267 may precharge the third node ND3 to the voltage level of the power supply terminal VCORE.

[0058] The eighth switch 268 may be coupled between the fourth node ND4 and the ground terminal. When the sensing node SO is at a high level, the eighth switch 268 may connect the fourth node ND4 to the ground terminal.

[0059] Each of the first to eighth switches 261 - 268 may include a transistor.

[0060] The data latch groups 210 and 220, the backup latch 230, the sensing information latch 240, and the precharge selection information latch 250 may be coupled in parallel between the sensing node SO and the fourth node ND4. The data latch groups 210 and 220, the backup latch 230, the sensing information latch 240, and the precharge selection information latch 250 may each have one end coupled to the sensing node SO and the other end commonly coupled to the eighth switch 268 via the fourth node ND4.

[0061] The data latch group 210, 220 may include a first data latch 210 and a second data latch 220. As an example and not a limitation, the first data latch 210 and the second data latch 220 are configured to store 2-bit data to match a 2-bit MLC. For example, if the memory cells of the memory cell array 110 are 3-bit triple-level cells, the data latch group may include three data latches, and if the memory cells are 4-bit quad-level cells, the data latch group may include four data latches.

[0062] The first data latch 210 can store one of two bits of data, such as the LSB, in response to a first transmission control signal pair TRAN1, TRAN1_N, a first set signal Q1SET, and a first reset signal Q1RST. The first data latch 210 may include a first inverter 211, a second inverter 212, and a plurality of transistors, such as first through sixth transistors 213-218. The first inverter 211 may have an output terminal coupled to a latch node Q1 and an input terminal coupled to a latch node Q1_N (e.g., one of the latch node pair Q1, Q1_N). The second inverter 212 may have an output terminal coupled to the latch node Q1_N and an input terminal coupled to the latch node Q1. The first transistor 213 may have a source terminal coupled to a fourth node ND4, a drain terminal coupled to the latch node Q1_N, and a gate terminal that receives the first set signal Q1SET as an input. When the first set signal Q1SET is at a high level, the first transistor 213 may connect the latch node Q1_N to the fourth node ND4. When the first set signal Q1SET is at a high level and the sense node SO is at a high level, the first transistor 213 may cause the latch node Q1_N to be at a low level. The second transistor 214 may have a source terminal coupled to the fourth node ND4, a drain terminal coupled to the latch node Q1, and a gate terminal that receives the first reset signal Q1RST as an input. When the first reset signal Q1RST is at a high level, the second transistor 214 may connect the latch node Q1 to the fourth node ND4. When the first reset signal Q1RST is at a high level and the sense node SO is at a high level, the second transistor 214 may cause the latch node Q1 to be at a low level. The third transistor 215 may have a drain terminal coupled to the ground terminal and a gate terminal coupled to the latch node Q1. The fourth transistor 216 may have a drain terminal coupled to the source terminal of the third transistor 215, a source terminal coupled to the sense node SO, and a gate terminal receiving one of the first transmission control signal pair TRAN1 and TRAN1_N (e.g., the first transmission control signal TRAN1) as an input. When the latch node Q1 and the first transmission control signal TRAN1 are at a high level, the third transistor 215 and the fourth transistor 216 may cause the logic level of the sense node SO to be low. The fifth transistor 217 may have a drain terminal coupled to the ground terminal and a gate terminal coupled to the latch node Q1_N. The sixth transistor 218 may have a drain terminal coupled to the source terminal of the fifth transistor 217, a source terminal coupled to the sense node SO, and a gate terminal receiving the first transmission control signal TRAN1_N as an input.When the latch node Q1_N and the first transmission control signal TRAN1_N are at a high level, the fifth transistor 217 and the sixth transistor 218 may make the logic level of the sensing node SO at a low level.

[0063] When the sense node SO is at a high level, the first data latch 210 can maintain the latch node Q1_N at a low level in response to the first set signal Q1SET at a high level, thereby storing the LSB data at a low level. When the sense node SO is at a high level, the first data latch 210 can maintain the latch node Q1_N at a high level in response to the first reset signal Q1RST at a high level, thereby storing the LSB data at a high level. Since the latch node Q1 and the latch node Q1_N are complementary to each other and always maintain opposite logic levels, the logic level of one of the latch node pair Q1 and Q1_N can be used as the LSB data. The above description of determining the logic level of the LSB data based on the logic level of the latch node Q1_N is merely an example, and vice versa is also possible. The first data latch 210 may control the level of the sensing node SO using the logic level of the latch node Q1 when the first transmission control signal TRAN1 is high, and may control the level of the sensing node SO using the logic level of the latch node Q1_N when the first transmission control signal TRAN1_N is high.

[0064] The second data latch 220 can store one of two bits of data, such as the MSB, in response to the second transmission control signal pair TRAN2, TRAN2_N, the second set signal Q2SET, and the second reset signal Q2RST. The second data latch 220 may include a first inverter 221, a second inverter 222, and a plurality of transistors, such as first to sixth transistors 223-228. The first inverter 221 may have an output terminal coupled to a latch node Q2 and an input terminal coupled to a latch node Q2_N (e.g., one of the latch node pair Q2, Q2_N). The second inverter 222 may have an output terminal coupled to the latch node Q2_N and an input terminal coupled to the latch node Q2. The first transistor 223 may have a source terminal coupled to a fourth node ND4, a drain terminal coupled to the latch node Q2_N, and a gate terminal that receives the second set signal Q2SET as an input. When the second set signal Q2SET is at a high level, the first transistor 223 may connect the latch node Q2_N to the fourth node ND4. When the second set signal Q2SET is at a high level and the sense node SO is at a high level, the first transistor 223 may cause the latch node Q2_N to be at a low level. The second transistor 224 may have a source terminal coupled to the fourth node ND4, a drain terminal coupled to the latch node Q2, and a gate terminal that receives the second reset signal Q2RST as an input. When the second reset signal Q2RST is at a high level, the second transistor 224 may connect the latch node Q2 to the fourth node ND4. When the second reset signal Q2RST is at a high level and the sense node SO is at a high level, the second transistor 224 may cause the latch node Q2 to be at a low level. The third transistor 225 may have a drain terminal coupled to the ground terminal and a gate terminal coupled to the latch node Q2. The fourth transistor 226 may have a drain terminal coupled to the source terminal of the third transistor 225, a source terminal coupled to the sense node SO, and a gate terminal receiving any one of the second transmission control signal pair TRAN2 and TRAN2_N (e.g., the second transmission control signal TRAN2) as an input. When the latch node Q2 and the second transmission control signal TRAN2 are at a high level, the third transistor 225 and the fourth transistor 226 may cause the logic level of the sense node SO to be low. The fifth transistor 227 may have a drain terminal coupled to the ground terminal and a gate terminal coupled to the latch node Q2_N. The sixth transistor 228 may have a drain terminal coupled to the source terminal of the fifth transistor 227, a source terminal coupled to the sense node SO, and a gate terminal receiving the second transmission control signal TRAN2_N as an input. When the latch node Q2_N and the second transmission control signal TRAN2_N are at a high level, the fifth transistor 227 and the sixth transistor 228 may cause the logic level of the sense node SO to be low.

[0065] When the sense node SO is at a high level, the second data latch 220 can maintain the latch node Q2_N at a low level in response to the second set signal Q2SET at a high level, thereby storing the MSB data at a low level. When the sense node SO is at a high level, the second data latch 220 can maintain the latch node Q2_N at a high level in response to the second reset signal Q2RST at a high level, thereby storing the MSB data at a high level. Since the latch node Q2 and the latch node Q2_N are complementary to each other and always maintain opposite logic levels, the logic level of one of the latch node pair Q2 and Q2_N can be used as the MSB data. The above description of determining the logic level of the MSB data based on the logic level of the latch node Q2_N is merely an example, and vice versa is also possible. The second data latch 220 can control the level of the sensing node SO using the logic level of the latch node Q2 when the second transmission control signal TRAN2 is at a high level, and can control the level of the sensing node SO using the logic level of the latch node Q2_N when the second transmission control signal TRAN2_N is at a high level.

[0066] The backup latch 230 can be configured to store sensing information (i.e., sensing information stored in the sensing information latch 240) as backup information. The backup latch 230 can back up the sensing information in response to the third transmission control signal TRANT, the third set signal QTSET, and the third reset signal QTRST. The backup latch 230 may include a first inverter 231, a second inverter 232, and a plurality of transistors, such as first to fourth transistors 233-236. The first inverter 231 may have an output terminal coupled to any one of the latch node pair QT and QT_N (e.g., the latch node QT) and an input terminal coupled to the latch node QT_N. The second inverter 232 may have an output terminal coupled to the latch node QT_N and an input terminal coupled to the latch node QT. The first transistor 233 may have a source terminal coupled to the fourth node ND4, a drain terminal coupled to the latch node QT_N, and a gate terminal that receives the third set signal QTSET as an input. When the third set signal QTSET is at a high level, the first transistor 233 may connect the latch node QT_N to the fourth node ND4. When the third set signal QTSET is at a high level and the sense node SO is at a high level, the first transistor 233 may cause the latch node QT_N to be at a low level. The second transistor 234 may have a source terminal coupled to the fourth node ND4, a drain terminal coupled to the latch node QT, and a gate terminal that receives the third reset signal QTRST as an input. When the third reset signal QTRST is at a high level, the second transistor 234 may connect the latch node QT to the fourth node ND4. When the third reset signal QTRST is at a high level and the sense node SO is at a high level, the second transistor 234 may cause the latch node QT to be at a low level. The third transistor 235 may have a drain terminal coupled to the ground terminal and a gate terminal coupled to the latch node QT. The fourth transistor 236 may have a drain terminal coupled to the source terminal of the third transistor 235, a source terminal coupled to the sensing node SO, and a gate terminal receiving the third transmission control signal TRAN as an input. When the latch node QT and the third transmission control signal TRAN are at a high level, the third transistor 235 and the fourth transistor 236 may cause the logic level of the sensing node SO to be at a low level.

[0067] When the sensing node SO is at a high level, the backup latch 230 can maintain the latch node QT_N at a low level in response to the third set signal QTSET having a high level, thereby storing the backup information at a low level. When the sensing node SO is at a high level, the backup latch 230 can maintain the latch node QT_N at a high level in response to the third reset signal QTRST having a high level, thereby storing the backup information at a high level.

[0068] The sensing information latch 240 can be configured to store a result signal from a verification operation, namely, sensing information. The sensing information latch 240 can store the sensing information in response to a fourth transmission control signal TRANM_N, a fourth set signal QMSET, and a fourth reset signal QMRST. The sensing information latch 240 can include a first inverter 241, a second inverter 242, and a plurality of transistors, such as first to fourth transistors 243-246. The first inverter 241 can have an output terminal coupled to any one of the latch node pair QM and QM_N (e.g., latch node QM) and an input terminal coupled to latch node QM_N. The second inverter 242 can have an output terminal coupled to latch node QM_N and an input terminal coupled to latch node QM. The first transistor 243 can have a source terminal coupled to a fourth node ND4, a drain terminal coupled to latch node QM_N, and a gate terminal that receives the fourth set signal QMSET as an input. When the fourth set signal QMSET is at a high level, the first transistor 243 may connect the latch node QM_N to the fourth node ND4. When the fourth set signal QMSET is at a high level and the sense node SO is at a high level, the first transistor 243 may bring the latch node QM_N to a low level. The second transistor 244 may have a source terminal coupled to the fourth node ND4, a drain terminal coupled to the latch node QM, and a gate terminal that receives the fourth reset signal QMRST as an input. When the fourth reset signal QMRST is at a high level, the second transistor 244 may connect the latch node QM to the fourth node ND4. When the fourth reset signal QMRST is at a high level and the sense node SO is at a high level, the second transistor 244 may bring the latch node QM to a low level. The third transistor 245 may have a drain terminal coupled to the ground terminal and a gate terminal coupled to the latch node QM. The fourth transistor 246 may have a drain terminal coupled to the source terminal of the third transistor 245, a source terminal coupled to the sensing node SO, and a gate terminal receiving the fourth transmission control signal TRANM_N as an input. When the latch node QM and the fourth transmission control signal TRANM_N are at a high level, the third transistor 245 and the fourth transistor 246 may cause the logic level of the sensing node SO to be at a low level.

[0069] When the sense node SO is at a high level, the sense information latch 240 can maintain the latch node QM_N at a low level in response to the fourth set signal QMSET at a high level, thereby storing the sense information at a low level. When the sense node SO is at a high level, the sense information latch 240 can maintain the latch node QM_N at a high level in response to the fourth reset signal QMRST at a high level, thereby storing the sense information at a high level. The sense information can be used as a signal indicating the result of the verification operation. If the sense information is at a high level, it can be defined as a fail, that is, the programming operation is not completed. If the sense information is at a low level, it can be defined as a pass, that is, the programming operation is completed.

[0070] The precharge selection information latch 250 can be configured to store precharge selection information, i.e., information for selecting bit lines corresponding to the remaining sub-verification operations, excluding the verified sub-verification operation, among the multiple sub-verification operations included in the main verification operation. The precharge selection information latch 250 can back up the sensing information in response to the discharge control signal SA_DISCH, the fifth set signal QSSET, and the fifth reset signal QSRST. The precharge selection information latch 250 can include a first inverter 251, a second inverter 252, and a plurality of transistors, such as first to fourth transistors 253-256. The first inverter 251 can have an output terminal coupled to any one of the latch node pair QS, QS_N (e.g., latch node QS) and an input terminal coupled to latch node QS_N. The second inverter 252 can have an output terminal coupled to latch node QS_N and an input terminal coupled to latch node QS. The first transistor 253 may have a source terminal coupled to the fourth node ND4, a drain terminal coupled to the latch node QS_N, and a gate terminal receiving the fifth set signal QSSET as an input. When the fifth set signal QSSET is at a high level, the first transistor 253 may connect the latch node QS_N to the fourth node ND4. When the fifth set signal QSSET is at a high level and the sense node SO is at a high level, the first transistor 253 may cause the latch node QS_N to be at a low level. The second transistor 254 may have a source terminal coupled to the fourth node ND4, a drain terminal coupled to the latch node QS, and a gate terminal receiving the fifth reset signal QSRST as an input. When the fifth reset signal QSRST is at a high level, the second transistor 254 may connect the latch node QS to the fourth node ND4. When the fifth reset signal QSRST is at a high level and the sense node SO is at a high level, the second transistor 254 may cause the latch node QS to be at a low level. The third transistor 255 may have a drain terminal coupled to the ground terminal and a gate terminal coupled to the latch node QS. The fourth transistor 256 may have a drain terminal coupled to the source terminal of the third transistor 255, a source terminal coupled to the sense node SO, and a gate terminal receiving the discharge control signal SA_DISCH as an input. When the latch node QS and the discharge control signal SA_DISCH are at a high level, the third transistor 255 and the fourth transistor 256 may cause the logic level of the sense node SO to be at a low level.

[0071] When the sensing node SO is at a high level, the precharge selection information latch 250 can maintain the latch node QS_N at a low level in response to the fifth set signal QSSET having a high level, thereby storing the precharge selection information at a low level. When the sensing node SO is at a high level, the precharge selection information latch 250 can maintain the latch node QS_N at a high level in response to the fifth reset signal QSRST having a high level, thereby storing the precharge selection information at a high level.

[0072] The precharge selection information may be used as a signal to set which page buffers should precharge the bit lines in a main verification operation. If the precharge selection information is at a high level, the corresponding page buffer may be defined to correspond to the verification level included in the main verification operation; if the precharge selection information is at a low level, the corresponding page buffer may be defined not to correspond to the verification level included in the main verification operation.

[0073] Reference Figure 3 The described page buffer control signal PBSIG may include a first precharge control signal PRECHSO_N, a second precharge control signal SA_PRECH_N, a first sensing control signal SA_SENSE, a second sensing control signal PB_SENSE, a third sensing control signal SA_CSOC, a first transmission control signal pair TRAN1 and TRAN1_N, a first set signal Q1SET, a first reset signal Q1RST, a second transmission control signal pair TRAN2 and TRAN2_N, a second set signal Q2SET, a second reset signal Q2RST, a third transmission control signal TRANT, a third set signal QTSET, a third reset signal QTRST, a fourth transmission control signal TRANM_N, a fourth set signal QMSET, a fourth reset signal QMRST, a discharge control signal SA_DISCH, a fifth set signal QSSET, and a fifth reset signal QSRST.

[0074] Reference Figures 5 to 7 , programming and verification operations of a semiconductor memory device according to an embodiment of the present disclosure will be described below.

[0075] Figure 6 It shows Figure 5 A diagram of the data stored in the page buffer and the verification level, Figure 7 is a diagram illustrating program and verification operations according to an embodiment of the present disclosure.

[0076] Reference Figure 6In response to external data input, the latch node Q1_N of the first data latch 210 and the latch node Q2_N of the second data latch 220 can store a Gray code corresponding to the external input data. The Gray code can correspond to the first to third verification levels PV1-PV3 or the non-verification level PV0, respectively.

[0077] When the Gray code stored in the latch node Q1_N and the latch node Q2_N of the page buffer is '10', the sub-verification operation using the first verification level PV1 can be used to verify whether the corresponding programming operation passes or fails; when the Gray code stored in the latch node Q1_N and the latch node Q2_N is '00', the sub-verification operation using the second verification level PV2 can be used to verify whether the corresponding programming operation passes or fails; when the Gray code stored in the latch node Q1_N and the latch node Q2_N is '01', the sub-verification operation using the third verification level PV3 can be used to verify whether the corresponding programming operation passes or fails.

[0078] The corresponding bit line precharge operation must be performed before the sub-verification operation. Therefore, the embodiment of the present disclosure can select the bit lines corresponding to all the verification levels included in the main verification operation according to the value of the Gray code stored in the page buffer and precharge them simultaneously.

[0079] Reference Figure 7 , a program operation according to an embodiment of the present disclosure may include a plurality of loops LP1, LP2, . . . , LP15, . . .

[0080] Each loop may include a sub-programming operation and a main verification operation. A main verification operation may include multiple sub-verification operations. For example, the main verification operations of the first to sixth loops LP1 to LP6 may include a first sub-verification operation using a first verification level PV1 and a second sub-verification operation using a second verification level PV2. The main verification operation of the seventh loop LP7 includes first to third sub-verification operations using first to third verification levels PV1-PV3. The main verification operation of the fifteenth loop LP15 includes second and third sub-verification operations using second and third verification levels PV2 and PV3.

[0081] First, a first sub-program operation PGM1 of a first loop LP1 may be performed to match Gray codes stored in latch nodes Q1_N and Q2_N. In the first sub-program operation PGM1, a program voltage is applied to a selection word line WL to increase a threshold voltage of a memory cell.

[0082] A first main verification operation MV1 may then be performed. The first main verification operation MV1 may include a bit line set operation, a first sub-verification operation using a first verification level PV1, and a second sub-verification operation using a second verification level PV2.

[0083] As a bitline set operation, a method for simultaneously precharging selected bitlines is employed. This method differs from conventional methods for precharging all bitlines and sequentially precharging selected bitlines. To perform the method, the bitline set operation may include selecting a bitline to be simultaneously precharged from among all bitlines (hereinafter referred to as a preliminary set operation). The bitline set operation may include a preliminary set operation and a main set operation.

[0084] The preliminary setting operation may include at least one of the following operations: a first preliminary setting operation of selecting a page buffer corresponding to a first verification level PV1 from the total page buffer, a second preliminary setting operation of selecting a page buffer corresponding to a second verification level PV2 from the total page buffer, and a third preliminary setting operation of selecting a page buffer corresponding to a third verification level PV3 from the total page buffer.

[0085] The first main verification operation MV1 applies only the first verification level PV1 and the second verification level PV2, and since the first verification level PV1 and the second verification level PV2 are applied first, the first preliminary setting operation and the second preliminary setting operation can be performed as preliminary setting operations. Each of the first preliminary setting operation and the second preliminary setting operation can include an operation of resetting backup information.

[0086] The first preliminary setup operation can be performed using the first precharge control signal PRECHSO_N, the first transfer control signal TRAN1, the second transfer control signal TRAN2_N, and the third reset signal QTRST. The detailed operation is as follows. First, the first precharge control signal PRECHSO_N is input in the form of a low pulse to precharge the sense node SO to a high level, that is, the power supply voltage VCORE level. The latch nodes Q1_N and Q2_N of the page buffer corresponding to the first verification level PV1 store the Gray code '10'. Therefore, by applying the first transfer control signal TRAN1, the second transfer control signal TRAN2_N, and the third reset signal QTRST in the form of a high pulse, the sense node SO of the page buffer storing the Gray code '10' remains at a high level. Since the sense node SO is at a high level, the backup information, that is, the logic level of the latch node QT_N, can be reset to a high level. On the other hand, the sense node SO of the page buffer that does not store the Gray code '10' transitions to a low level. Since the sense node SO is at a low level, the backup information retains its previous value.

[0087] The second preliminary setup operation can be performed using the first precharge control signal PRECHSO_N, the first transfer control signal TRAN1_N, the second transfer control signal TRAN2_N, and the third reset signal QTRST. The detailed operation is as follows. First, the first precharge control signal PRECHSO_N in the form of a low pulse is input to precharge the sense node SO to a high level, that is, the power supply voltage VCORE level. The latch nodes Q1_N and Q2_N of the page buffer corresponding to the second verification level PV2 store the Gray code '00'. Therefore, by applying the first transfer control signal TRAN1_N, the second transfer control signal TRAN2_N, and the third reset signal QTRST in the form of a high pulse, the sense node SO of the page buffer storing the Gray code '00' remains at a high level. Since the sense node SO is at a high level, the backup information can be reset to a high level. On the other hand, the sense node SO of the page buffer where the Gray code is not stored as '00' is converted to a low level. Since the sense node SO is at a low level, the backup information retains its previous value.

[0088] The main set operation can be completed by storing the backup information stored in the backup latch 230 in the precharge selection information latch 250. The main set operation can be performed using the first precharge control signal PRECHSO_N, the fifth set signal QSSET, the third transmission control signal TRANT, and the fifth reset signal QSRST. The first precharge control signal PRECHSO_N is input in the form of a low pulse to precharge the sense node SO to a high level, that is, the power supply voltage VCORE level. In the first and second preliminary set operations described above, the backup information is reset to a high level. Since the backup information is at a high level, the logic level of the precharge selection information (i.e., the logic level of the latch node QS_N) can be set to a high level by sequentially applying the fifth set signal QSSET in the form of a high pulse, the third transmission control signal TRANT, and the fifth reset signal QSRST.

[0089] Subsequently, a first sub-verification operation may be performed using the first verification level PV1 and a second sub-verification operation may be performed using the second verification level PV2. The first sub-verification operation may include a bit line selection and simultaneous precharging operation, an evaluation operation, a first verification level shielding operation, and a sensing operation.

[0090] The simultaneous precharging of selected bit lines can be performed using the second precharge control signal SA_PRECH_N, the first sense control signal SA_SENSE, the second sense control signal PB_SENSE, the third sense control signal SA_CSOC, and the discharge control signal SA_DISCH. The detailed operation is as follows. By maintaining the second precharge control signal SA_PRECH_N at a low level and maintaining the first sense control signal SA_SENSE, the second sense control signal PB_SENSE, the third sense control signal SA_CSOC, and the discharge control signal SA_DISCH at high levels, the second switches 262 of the page buffers storing precharge selection information at a high level remain turned on, while the second switches 262 of the page buffers storing precharge selection information at a low level remain turned off. Consequently, the bit lines BL connected to all page buffers corresponding to the first verify level PV1 and the second verify level PV2 (i.e., the page buffers storing precharge selection information at a high level) can be simultaneously precharged to the power supply voltage VCORE level. The terms "simultaneously" and "simultaneously" used herein with respect to the processes mean that the processes occur within overlapping time intervals. For example, if a first process occurs within a first time interval and a second process occurs simultaneously within a second time interval, the first and second intervals at least partially overlap with each other such that there is a time when both the first and second processes occur.

[0091] The evaluation operation may be an operation for evaluating a potential change of the sense node SO based on the program state of the memory cell. The evaluation operation may be implemented by switching the second precharge control signal SA_PRECH_N to a high level. Since the second precharge control signal SA_PRECH_N is at a high level, the third switch 263 may be turned off, and the potential of the sense node SO may change accordingly according to the program state of the memory cell coupled to the bit line BL.

[0092] The first verification level masking operation may be an operation that selects only the page buffers connected to the bit lines BL corresponding to the first verification level PV1 among the bit lines BL precharged by the simultaneous bit line selection precharge operation. The first verification level masking operation may be achieved by transitioning the first transfer control signal TRAN1 and the second transfer control signal TRAN2_N to a high level. Since the first transfer control signal TRAN1 and the second transfer control signal TRAN2_N are at a high level, the sense node SO of the page buffer corresponding to the first verification level PV1 remains at a high level, while the sense node SO of the page buffer corresponding to the second verification level PV2 transitions to a low level.

[0093] The sensing operation may be an operation for detecting whether the first sub-verification operation using the first verification level PV1 has passed or failed. The sensing operation may be implemented by switching the first sense control signal SA_SENSE to a low level and applying the fourth set signal QMSET to a high level. Since the first sense control signal SA_SENSE is at a low level and the fourth set signal QMSET is at a high level, when the sense node SO is at a high level, the sensing information (i.e., the logic level of the latch node QM_N) may be stored at a low level.

[0094] Unlike the first sub-verification operation, the second sub-verification operation may further include a sensing node recovery operation, an evaluation operation, a second verification level masking operation, and a sensing operation in addition to a bit line selection and simultaneous precharging operation.

[0095] The sense node recovery operation may be an operation of restoring the sense node SO of the page buffer corresponding to the second verification level PV2 to the power supply voltage VCORE level. The sense node recovery operation may be achieved by converting the second precharge control signal SA_PRECH_N to a low level and applying the first sense control signal SA_SENSE having a high level. Since the second precharge control signal SA_PRECH_N is at a low level and the first sense control signal SA_SENSE is at a high level, the sense node SO of the page buffer storing precharge selection information at a high level may be restored to the power supply voltage VCORE level.

[0096] The evaluation operation may be performed in the same manner as the first sub-verification operation.

[0097] The second verify level masking operation may be an operation that selects only the page buffers connected to the bit lines BL corresponding to the second verify level PV2 from among the bit lines BL precharged by the previously performed simultaneous bit line precharge operation. The second verify level masking operation may be achieved by transitioning the first transfer control signal TRAN1_N and the second transfer control signal TRAN2_N to a high level. Since the first transfer control signal TRAN1_N and the second transfer control signal TRAN2_N are at a high level, the sense node SO of the page buffer corresponding to the second verify level PV2 remains at a high level, while the sense node SO of the page buffer corresponding to the first verify level PV1 transitions to a low level.

[0098] The sensing operation is performed in the same manner as the first sub-verification operation, and sensing information of the page buffer corresponding to the second verification level PV2 may be updated accordingly.

[0099] The determined loops can be sequentially executed in the manner described above. In this case, when one loop is completed and another loop is executed, a selection bit line backup operation can be performed to back up the verification result of the previous loop, i.e., the sensing information. The selection bit line backup operation can be performed by storing the sensing information stored in the sensing information latch 240 as backup information in the backup latch 230. Therefore, the backup latch 230 can store the sensing information according to the most recent loop as backup information.

[0100] The bit line backup operation can be performed using the first precharge control signal PRECHSO_N, the fourth transfer control signal TRANM_N, and the third set signal QTSET. When the first precharge control signal PRECHSO_N is input at a low level, the sense node SO is precharged to the power supply voltage VCORE level. When the fourth transfer control signal TRANM_N is input at a high level, the sense node SO can be converted to a low level when the sense information is at a high level, and the sense node SO can remain at a high level when the sense information is at a low level. When the third set signal QTSET is input at a high level, if the sense node SO is at a high level, the backup information can be stored at a low level, and if the sense node SO is at a low level, the backup information can be maintained at the previous value.

[0101] The seventh sub-programming operation PGM7 of the seventh loop LP7 may be performed in the manner described above. In the seventh sub-programming operation PGM7, a programming voltage is applied to the selected word line WL to increase the threshold voltage of the memory cell. After the seventh sub-programming operation PGM7, a selection bit line backup operation may be performed.

[0102] The main verification operation MV7 of the seventh loop LP7 includes first to third sub-verification operations using first to third verification levels PV1-PV3. In the seventh loop LP7, the third verification level PV3 is applied for the first time, so that a third preliminary setup operation can be performed. The third preliminary setup operation may include an operation of resetting backup information.

[0103] The third preliminary setup operation can be performed using the first precharge control signal PRECHSO_N, the first transfer control signal TRAN1_N, the second transfer control signal TRAN2, and the third reset signal QTRST. The detailed operation is as follows. First, when the first precharge control signal PRECHSO_N is input in the form of a low pulse, the sense node SO is precharged to the power supply voltage VCORE level. The latch nodes Q1_N and Q2_N of the page buffer corresponding to the third verification level PV3 store the Gray code '01'. Therefore, by applying the first transfer control signal TRAN1_N, the second transfer control signal TRAN2, and the third reset signal QTRST in the form of a high pulse, the sense node SO of the page buffer storing the Gray code '01' remains at a high level. Since the sense node SO is at a high level, the backup information, that is, the logic level of the latch node QT_N, can be reset to a high level. On the other hand, the sense node SO of the page buffer that does not store the Gray code '01' transitions to a low level. Since the sense node SO is at a low level, the backup information retains its previous value.

[0104] Then, the first sub-verification operation and the second sub-verification operation may be performed in the same manner as the first round LP1.

[0105] Then, a third sub-verification operation may be performed. The third sub-verification operation may include a sense node recovery operation, an evaluation operation, a third verification level masking operation, and a sense operation. The sense node recovery operation, the evaluation operation, and the sense operation may be performed in the same manner as the second sub-verification operation.

[0106] The third verify level masking operation may be an operation that selects only the page buffers connected to the bit lines BL corresponding to the third verify level PV3 from among the bit lines BL precharged by the previously performed simultaneous bit line precharge operation. The third verify level masking operation may be achieved by transitioning the first transfer control signal TRAN1_N and the second transfer control signal TRAN2 to a high level. Since the first transfer control signal TRAN1_N and the second transfer control signal TRAN2 are at a high level, the sense node SO of the page buffer corresponding to the third verify level PV3 remains at a high level, while the sense nodes SO of the page buffers corresponding to the first verify level PV1 and the second verify level PV2 transition to a low level.

[0107] After the seventh to fourteenth loops LP7-LP14 are completed, it can be determined that the program operation of all memory cells corresponding to the first verification level PV1 has passed. Therefore, the sensing information of all page buffers corresponding to the first verification level PV1 can be stored at a low level. The low-level sensing information can be stored as low-level backup information by selecting the bit line backup operation.

[0108] Then, a fifteenth sub-program operation PGM15 and a fifteenth main verification operation MV15 according to a fifteenth loop LP15 may be performed.

[0109] First, a fifteenth sub-program operation PGM15 may be performed to match the Gray code stored in the latch node Q1_N and the latch node Q2_N. In the fifteenth sub-program operation PGM15, a program voltage is applied to the selection word line WL to increase the threshold voltage of the memory cell.

[0110] A fifteenth main verification operation MV15 may then be performed. The fifteenth main verification operation MV1 may be a bit line set operation and second and third sub-verification operations using second and third verification levels PV2, PV3 in addition to the first verification level PV1.

[0111] Since the second and third verification levels PV2 and PV3 have been applied in the previous cycle, that is, the second and third verification levels PV2 and PV3 are not applied for the first time, the bit line set operation can only include a main set operation. Through the main set operation, the precharge selection information of all page buffers corresponding to the first verification level PV1 can be stored at a low level, while the precharge selection information of all page buffers corresponding to the second and third verification levels PV2 and PV3 can be stored at a high level.

[0112] The second sub-verification operation of the fifteenth loop LP15 may be performed in the same manner as the first sub-verification operation of the seventh loop LP7 , and the third sub-verification operation of the fifteenth loop LP15 may be performed in the same manner as the second sub-verification operation of the seventh loop LP7 .

[0113] During the second sub-verification operation of the fifteenth loop LP15 , all bit lines BL coupled to all page buffers corresponding to the second and third verification levels PV2 and PV3 , except for the page buffer corresponding to the first verification level PV1 , may be simultaneously precharged to the power supply voltage VCORE level.

[0114] The embodiments of the present disclosure described above adopt a selection bit line simultaneous precharging method that allows only bit lines connected to a page buffer corresponding to a verification level determined for each cycle of each program and verification operation to be precharged simultaneously.

[0115] Those skilled in the art to which the present disclosure pertains will appreciate that the present disclosure may be implemented in other specific forms without changing its technical spirit or basic features. Therefore, it should be understood that the above-described embodiments are illustrative in all respects and not restrictive. The scope of the present disclosure is defined by the claims to be described below rather than by the detailed description, and it should be understood that the meaning and scope of the claims and all changes or modifications derived from their equivalent concepts are included within the scope of the present disclosure.

Claims

1. A semiconductor memory device comprising: multiple bit lines; a plurality of page buffers, each page buffer coupled to the plurality of bit lines and operating in response to a plurality of page buffer control signals; as well as a page buffer control circuit that generates the plurality of page buffer control signals to perform a program and verification operation including a plurality of cycles, The page buffer control circuit uses the multiple page buffer control signals to simultaneously precharge the bit lines connected to the page buffers among the multiple page buffers, and the page buffers among the multiple page buffers correspond to multiple verification levels, and the multiple verification levels correspond to each of the multiple cycles.

2. The semiconductor memory device according to claim 1, wherein The page buffer control circuit precharges a bit line connected to a page buffer among the multiple page buffers, wherein the page buffer among the multiple page buffers corresponds to a remaining level among the multiple verification levels, and the remaining level is a level among the multiple verification levels other than the verification level determined to be passed.

3. The semiconductor memory device according to claim 1, wherein Each of the plurality of loops includes a sub-program operation and a main verification operation including a plurality of sub-verification operations corresponding to the plurality of verification levels.

4. The semiconductor memory device according to claim 1, wherein Each of the plurality of page buffers includes a data latch group connected in parallel to a sensing node, a backup latch, a sensing information latch, and a precharge selection information latch.

5. The semiconductor memory device according to claim 4, wherein The data latch group includes a plurality of data latches, and each of the plurality of data latches stores at least one bit of data.

6. The semiconductor memory device according to claim 4, wherein The sensing information latch stores whether a plurality of sub-verification operations corresponding to the plurality of verification levels pass or fail as sensing information.

7. The semiconductor memory device according to claim 6, wherein The backup latch stores the sensing information as backup information.

8. The semiconductor memory device according to claim 4, wherein The precharge selection information latch stores precharge selection information for setting a page buffer corresponding to the plurality of verification levels.

9. A semiconductor memory device comprising: a bit line coupled to the sensing node via at least one switch; a data latch group coupled to the sensing node and comprising a plurality of data latches, each of the plurality of data latches storing at least one bit of data; a sensing information latch coupled to the sensing node and storing, as sensing information, whether a plurality of sub-verification operations corresponding to a plurality of verification levels pass or fail; a backup latch coupled to the sensing node and storing the sensing information as backup information; a precharge selection information latch coupled to the sensing node and storing precharge selection information; as well as The page buffer control circuit controls the data latch group and the backup latch so that the backup information is reset according to the data, controls the backup latch and the precharge selection information latch so that the backup information is stored as the precharge selection information, and controls the at least one switch to precharge the bit line according to the precharge selection information.

10. The semiconductor memory device according to claim 9, wherein The data latch group, the backup latch, the sensing information latch, and the precharge selection information latch are coupled in parallel to the sensing node.

11. The semiconductor memory device according to claim 9, wherein After precharging the bit line, the page buffer control circuit controls the data latch group to convert the sensing node to a low level.

12. A semiconductor memory device comprising: multiple bit lines; a plurality of page buffers, sensing nodes of the plurality of page buffers being coupled to the plurality of bit lines through at least one switch, and the plurality of page buffers storing data, backup information, sensing information, and precharge selection information in response to a plurality of page buffer control signals; as well as a page buffer control circuit that generates the plurality of page buffer control signals to perform a program and verification operation including a plurality of cycles, In which, the page buffer control circuit performs a bit line setting operation, and the bit line setting operation includes at least one of a preliminary setting operation and a main setting operation to select a page buffer corresponding to a plurality of verification levels among the plurality of page buffers, and the page buffer control circuit uses each of the plurality of verification levels to perform a plurality of sub-verification operations, and simultaneously pre-charges the bit lines among the plurality of bit lines connected to the page buffers corresponding to the plurality of verification levels.

13. The semiconductor memory device according to claim 12, wherein When a verification level among the multiple verification levels is first applied, the page buffer control circuit performs a bit line setting operation including the preliminary setting operation and the main setting operation, and when a verification level among the multiple verification levels is not first applied, the page buffer control circuit performs a bit line setting operation including only the main setting operation.

14. The semiconductor memory device according to claim 12, wherein The preliminary setting operation includes resetting the backup information according to the data.

15. The semiconductor memory device according to claim 12, wherein The main setup operation includes storing the backup information as the precharge selection information.

16. The semiconductor memory device according to claim 12, wherein The page buffer control circuit performs a verification level masking operation of selecting only a page buffer coupled to a bit line corresponding to a current verification level among simultaneously precharged bit lines.

17. The semiconductor memory device according to claim 12, wherein The page buffer control circuit performs a sense node recovery operation after performing a first sub-verification operation of the plurality of sub-verification operations, the sense node recovery operation precharging the sense node for each subsequent sub-verification operation.

18. A method for controlling a verification operation of a semiconductor memory device, the semiconductor memory device comprising: multiple bit lines; a plurality of page buffers, each page buffer being coupled to the plurality of bit lines and storing data, backup information, sensing information, and precharge selection information; and a page buffer control circuit for controlling the plurality of page buffers to perform a program and verification operation including a plurality of cycles, the method comprising: performing a preliminary setting operation of resetting the backup information based on the data; performing a main setting operation of storing the backup information as the precharge selection information; and A bit line simultaneous precharge operation is performed according to the precharge selection information to simultaneously precharge bit lines connected to page buffers among the plurality of page buffers, the page buffers among the plurality of page buffers corresponding to a plurality of verification levels corresponding to each of the plurality of cycles.

19. The method according to claim 18, wherein The preliminary setting operation is performed only when a verification level among the plurality of verification levels is applied first.

20. The method of claim 18, further comprising: After performing the selecting bit line simultaneous precharging operation, a verification level masking operation is performed to select only the page buffer coupled to the bit line corresponding to the current verification level among the simultaneously precharged bit lines.

21. The method according to claim 20, further comprising: After performing the verification level masking operation, a sensing operation is performed using the current verification level to detect whether a sub-verification operation passes.

22. The method according to claim 21, further comprising: After performing the sensing operation, a sensing node recovery operation is performed to precharge the sensing node before performing a sub-verification operation.

23. The method of claim 22, further comprising: When one cycle among the plurality of cycles is completed and another cycle among the plurality of cycles is executed, a selection bit line backup operation is performed to store the sensing information as the backup information.

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