Semiconductor device and method of configuring interface of semiconductor device

Abstract

A semiconductor device includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes a first substrate, a first interface circuit, and a first bonding component. The first bonding assembly is arranged in the first bonding array area, and the first interface circuit is arranged in the first bonding array area. The second semiconductor die includes a second substrate, a second interface circuit, and a second bonding component. The first bonding assembly is connected with the second bonding assembly, the first interface circuit and the second interface circuit are located between the first substrate and the second substrate, and the first semiconductor tube core and the second semiconductor tube core are connected through an interface formed by the first interface circuit, the first bonding assembly, the second interface circuit and the second bonding assembly. The invention also provides a method for configuring the interface of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for configuring an interface of the semiconductor device. Background Art

[0002] With the development of the semiconductor industry, semiconductor components have realized more and more functions through the improvement of integration. To achieve high integration, an interface is needed to interconnect two or more semiconductor dies. The configuration of the interface is an indispensable part of the design and manufacture of integrated circuits (ICs). Summary of the Invention

[0003] The present disclosure provides a semiconductor device including an interface connecting two semiconductor dies, and having a flexible design for the configuration of bonding components and interface circuits.

[0004] According to an embodiment of the present disclosure, a semiconductor device includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes a first substrate, a first interface circuit, and a first bonding component, wherein the first bonding component is disposed within a first bonding array region, and the first interface circuit is disposed within the first bonding array region. The second semiconductor die includes a second substrate, a second interface circuit, and a second bonding component. The first bonding component is connected to the second bonding component, the first interface circuit and the second interface circuit are located between the first substrate and the second substrate, and the first semiconductor die and the second semiconductor die are connected via an interface formed by the first interface circuit, the first bonding component, the second interface circuit, and the second bonding component.

[0005] According to an embodiment of the present disclosure, the first interface circuit includes an interface logic circuit, a transceiver, and a receiver. The interface logic circuit, transceiver, and receiver are disposed within the first bonding array region. The transceiver and receiver are each electrically connected to the first bonding element. The pitch of the transceiver and receiver is smaller than the pitch of the first bonding element.

[0006] According to an embodiment of the present disclosure, a portion of the first interface circuit overlaps one or more of the first bonding components.

[0007] According to an embodiment of the present disclosure, the first semiconductor die further includes a functional circuit in signal communication with the first interface circuit, wherein a portion of the functional circuit is disposed within the first bonding array region.

[0008] According to an embodiment of the present disclosure, the first semiconductor die further includes an interconnect wiring structure disposed between the first bonding element and the first interface circuit.

[0009] According to an embodiment of the present disclosure, the first bonding element and the second bonding element include pads, microbumps, or other types of three-dimensional interconnect elements.

[0010] According to an embodiment of the present disclosure, a second bonding component is disposed in a second bonding array region that is substantially mirrored to the first bonding array region. A second interface circuit is disposed within the second bonding array region. The second interface circuit includes an interface logic circuit, a transceiver, and a receiver, which are disposed within the second bonding array region. The transceiver and receiver are each electrically connected to the second bonding component. The pitch between the transceiver and the receiver is smaller than the pitch of the second bonding component.

[0011] According to an embodiment of the present disclosure, a portion of the second interface circuit overlaps one or more of the second bonding components.

[0012] According to an embodiment of the present disclosure, the second semiconductor die further includes a functional circuit, and the functional circuit is in signal communication with the second interface circuit. A portion of the functional circuit is disposed within the second bonding array region of the second bonding element.

[0013] According to an embodiment of the present disclosure, the second semiconductor die further includes an interconnect wiring structure disposed between the second bonding element and the second interface circuit.

[0014] According to an embodiment of the present disclosure, a method for configuring an interface of a semiconductor device includes: providing a first bonding array area for configuring a first bonding component implemented in a first semiconductor die; providing a first interface circuit implemented within the first bonding array area in the first semiconductor die; providing a second interface circuit and a second bonding component implemented in a second semiconductor die; and bonding the first bonding component to the second bonding component.

[0015] According to an embodiment of the present disclosure, the first interface circuit includes an interface logic circuit, a transceiver, and a receiver. The interface logic circuit, transceiver, and receiver are disposed within the first bonding array region. The transceiver and receiver are each electrically connected to the first bonding element, and the pitch between the transceiver and receiver is smaller than the pitch of the first bonding element.

[0016] According to an embodiment of the present disclosure, the second bonding element is disposed in a second bonding array region that is substantially mirrored to the first bonding array region. The second interface circuit includes an interface logic circuit, a transceiver, and a receiver, all of which are disposed within the second bonding array region. The transceiver and receiver are each electrically connected to the second bonding element, with the pitch between the transceiver and the receiver being smaller than the pitch of the second bonding element.

[0017] According to an embodiment of the present disclosure, functional circuits are also provided to be implemented within the first bonding array region in the first semiconductor die.

[0018] According to embodiments of the present disclosure, functional circuitry to be implemented in a second semiconductor die is also provided.

[0019] Based on the above, a semiconductor device includes semiconductor dies bonded to each other in a face-to-face manner. The interface between the semiconductor dies includes corresponding interface circuitry and a bonding assembly on each semiconductor die, and the corresponding interface circuitry is disposed within a corresponding bonding array region of the bonding assembly. Therefore, the interface circuitry is compatible with various pitch designs of the bonding assembly, and the pitch design of the substrate in which the interface circuitry is implemented can be more flexible. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 FIG. 1 schematically illustrates a stacked structure of a semiconductor device having an interface communication mechanism according to an embodiment of the present invention.

[0021] Figure 2 A communication mechanism between a first semiconductor die and an adjacent second semiconductor die according to an interface of an embodiment of the present invention is schematically illustrated.

[0022] Figure 3 An interface interconnection between a first semiconductor die and an adjacent second semiconductor die according to an embodiment of the present invention is schematically shown.

[0023] Figure 4 The configuration of the interface of a semiconductor device according to some embodiments of the present disclosure is schematically shown.

[0024] Figure 5 and Figure 6 Schematically illustrates the configuration of interface circuits and bonding components according to some embodiments of the present disclosure.

[0025] Figure 7 A portion of a semiconductor die according to some embodiments of the present disclosure is schematically shown in cross-section.

[0026] Figure 8 A semiconductor device according to some embodiments of the present disclosure is schematically illustrated in a cross-sectional view. DETAILED DESCRIPTION

[0027] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0028] Figure 1 The stacked structure of a semiconductor device with an interface communication mechanism according to an embodiment of the present invention is schematically shown. Figure 1, the semiconductor device 1000 includes a first semiconductor die 100 and a plurality of second semiconductor dies 200 and an interface 300 connecting the first semiconductor die 100 to the second semiconductor die 200. The first semiconductor die 100, such as a processor semiconductor die, is included in the semiconductor device 1000 as a base semiconductor die. The second semiconductor die 200 (such as a static random-access memory (SRAM) semiconductor die) is stacked on the first semiconductor die 100. The interface 300 is configured to communicate information / data / signals between the first semiconductor die 100 and the second semiconductor die 200. In some embodiments, the interface 300 interconnecting the first semiconductor die 100 to the adjacent second semiconductor die 200 may also be referred to as a three-dimensional die interconnect (GUC multi-die interlink, Glink-3D), which realizes the interconnection between semiconductor dies in a three-dimensional packaging structure.

[0029] In some embodiments, the first semiconductor die 100 of the processor has a command to access data stored in the second semiconductor die 200 of the static random access memory. The first semiconductor die 100 can be considered as the main semiconductor die, and the second semiconductor die 200 can be considered as the slave semiconductor die, but the present disclosure is not limited to this. Due to the implemented interface 300, the read latency can be controlled to be approximately constant and small, for example, 2 nanoseconds (ns) or 5 nanoseconds in an embodiment. A single clock is used in the interface 300 to distribute to all second semiconductor dies 200, and the path length from the first semiconductor die 100 to each second semiconductor die 200 is approximately the same and reliable. The delay can be adjusted to a predictable and approximately constant value.

[0030] Figure 2 Schematically illustrates a communication mechanism between a first semiconductor die and an adjacent second semiconductor die according to an embodiment of the present invention. Figure 2, the first semiconductor die 100 may include functional circuitry 110 and a first interface circuitry 120 implemented therein. In an embodiment, the functional circuitry 110 and the cache circuitry 112 form a processor and are in signal communication with the first interface circuitry 120. For example, the processor is connected to the first interface circuitry 120 to send or receive signals through the first interface circuitry 120 in order to communicate with the second semiconductor die 200. The second semiconductor die 200 may include a second functional circuitry 210 and a second interface circuitry 220 implemented therein. The second functional circuitry 210 may include a static random access memory circuit in signal communication with the second interface circuitry 220 in order to communicate with the first semiconductor die 100. In addition, the first semiconductor die 100 and the second semiconductor die 200 are connected via a bonding structure 400, thereby achieving physical and electrical connection between the first semiconductor die 100 and the second semiconductor die 200. In this embodiment, the first interface circuit 120 , the second interface circuit 220 and the bonding structure 400 constitute the interface 300 . A bidirectional connection is established between the interface 300 and the first semiconductor die 100 and the second semiconductor die 200 for signal transmission. All signals are sent or received in parallel by the interface 300 .

[0031] Figure 3 Schematically shows the interface interconnection between a first semiconductor die and an adjacent second semiconductor die according to an embodiment of the present invention. Figure 3 As shown, the interface 300 includes Figure 1 The first interface circuit 120 implemented in the first semiconductor die 100 is shown as Figure 1 The second interface circuit 220 is implemented in the second semiconductor die 200. The interface 300 further includes a first bonding component 130 and a second bonding component 230. The first bonding component 130 is configured in the first semiconductor die 100, and the second bonding component 230 is configured in the second semiconductor die 200. The first bonding component 130 is bonded to the second bonding component 230 to form a bonding structure 400.

[0032] In this example, see Figures 1 to 3 , the first semiconductor die 100 includes a functional circuit 110, a first interface circuit 120, and a first bonding component 130. The functional circuit 110 may include a cache circuit 112 therein for use as Figure 2 The processor circuit described. Figure 3As shown, the first interface circuit 120 includes an interface logic circuit 122, a transceiver 124, and a receiver 126. The transceiver 124 and the receiver 126 are connected to the first bonding component 130 in a one-to-one manner to establish signal transmission with the second semiconductor die 200. In some embodiments, the interface logic circuit 122 is configured to provide control logic for built-in self-test (BIST), training, repair, parity check functions, and design-for-testability (DFT) logic.

[0033] In some embodiments, the first interface circuit 120 includes flip-flop (FF) units, multiplexers, and other components for establishing interconnection circuits to the second semiconductor die 200. The multiplexers in some embodiments are of a double data rate (DDR) type based on the input data at the flip-flops. Figure 3 As shown, a single clock is provided by the first interface circuit 120 and the second interface circuit 220. The timing of the flip-flop and the multiplexer is controlled by the single clock.

[0034] In some embodiments, the first interface circuit 120 can receive instructions according to the intention of the core circuit (e.g., functional circuit 110) of the first semiconductor die 100 and provide output to the second semiconductor die 200 via the transceiver 124 and the corresponding bonding component 130. In the embodiments, the instructions as input may include a cluster of data Tx_data, a control signal such as an IP control signal, and / or an instruction, without specific limitation. The instruction may also include a selection slave identifier for selecting the second semiconductor die 200 from the core circuit (e.g., functional circuit 110) of the first semiconductor die 100 to execute the instruction. The first interface circuit 120 may also receive a response from the second semiconductor die 200 via the corresponding bonding component 130 and receiver 126, and then transmit the data Rx_data inward to the core circuit (e.g., functional circuit 110) of the first semiconductor die 100.

[0035] In this example, see Figures 1 to 3 The second semiconductor die 200 includes a functional circuit 210, a second interface circuit 220, and a second bonding component 230. The second functional circuit 210 may include: Figure 2 The static random access memory circuit shown in FIG. Figure 3As shown, the second interface circuit 220 includes an interface logic circuit 222, a transceiver 224, and a receiver 226. The receiver 226 in the second interface circuit 220 is connected to the corresponding transceiver 124 in the first interface circuit 120 via the corresponding bonding component 130 and the corresponding bonding component 230. Similarly, the transceiver 224 in the second interface circuit 220 is connected to the corresponding receiver 126 in the first interface circuit 120 via the corresponding bonding component 130 and the corresponding bonding component 230. In addition, the timing of the second interface circuit 220 is controlled by a single clock. Figure 3 As shown, the interface logic circuit 222 can provide a second semiconductor die 220 (eg, Figure 1 As shown) outputs a response, for example, data Rx_data, and receives data Tx_data from the other second semiconductor die 220.

[0036] Figure 4 Schematically illustrates the configuration of the interface of a semiconductor device according to some embodiments of the present disclosure. Figure 4 In the embodiment, semiconductor device 1000 includes a first semiconductor die 100 and a second semiconductor die 200. Specifically, first semiconductor die 100 and second semiconductor die 200 are interconnected by interface 300. First semiconductor die 100 may include functional circuit 110, first interface circuit 120, and first bonding component 130. Second semiconductor die 200 may include functional circuit 210, second interface circuit 220, and second bonding component 230. Figure 4 The component configuration of the interface 300 is intended to be presented, and the configuration of the functional circuit 110 and the functional circuit 210 is not limited to the relationship shown in the figure.

[0037] In this embodiment, the first bonding component 130 can be configured at a predetermined pitch determined based on the bonding technology. Specifically, the first bonding component 130 is configured in the first bonding array region R130. The first interface circuit 120 is configured in a region that is smaller than the first bonding array region R130 and is substantially entirely located within the first bonding array region R130. As described above, the first bonding component 130 is connected to the transceiver 124 and the receiver 126 in the first interface circuit 120 in a one-to-one manner, and the pitch of the transceiver 124 and the receiver 126 can be smaller than the pitch of the first bonding component 130. In some embodiments, a portion of the first interface circuit 120 overlaps with one or more of the first bonding components 130. In this embodiment, the functional circuit 110 communicates signals with the first interface circuit 120. In some embodiments, a portion of the functional circuit 110 can be configured within the first bonding array region R130 and / or can overlap with one or more of the first bonding components 130.

[0038] The second bonding component 230 can be arranged at a predetermined pitch determined by the bonding technology. Specifically, the second bonding component 230 is arranged in the second bonding array region R230. The second bonding component 230 can be arranged corresponding to the first bonding component 130, such that the second bonding array region R230 is substantially a mirror image of the first bonding array region R130. Therefore, the second bonding component 230 is connected to the first bonding component 130 in a one-to-one manner. The second interface circuit 220 is arranged in an area smaller than the second bonding array region R230 and is substantially entirely located within the second bonding array region R230. As described above, the second bonding component 230 is connected to the transceiver 224 and the receiver 226 in the second interface circuit 220 in a one-to-one manner. The pitch between the transceiver 224 and the receiver 226 can be smaller than the pitch of the second bonding component 230. In some embodiments, a portion of the second interface circuit 220 overlaps with one or more portions of the second bonding component 230. In this embodiment, the functional circuit 210 communicates signals with the second interface circuit 220. In some embodiments, the functional circuit 210 may be disposed within the second bonding array region R230 and / or may overlap with one or more of the second bonding elements 230 .

[0039] In some embodiments, the configuration area of ​​the first interface circuit 120 may be independent of the configuration of the first bonding component 130, and the configuration area of ​​the second interface circuit 220 may be independent of the configuration of the second bonding component 230. For example, Figure 5 and Figure 6 Schematically illustrates the configuration of interface circuits and bonding components according to some embodiments of the present disclosure. Figure 5 In the embodiment, the interface circuit 20 may refer to the first interface circuit 120 or the second interface circuit 220 in the aforementioned embodiment, the bonding component 30 may refer to the first bonding component 130 or the second bonding component 230 in the aforementioned embodiment, and the bonding array area R1 may refer to the first bonding array area R130 or the second bonding array area 230 in the aforementioned embodiment. The bonding components 30 are arranged in a 5×5 array at a pitch P1, and the bonding components 30 are arranged in the bonding array area R1 having an area A1. The interface circuit 20 is configured in a prescribed area R2 having an area A2. As described in the previous embodiment, the interface circuit 20 may include an interface logic circuit, a transceiver, and a receiver that can be manufactured using a semiconductor manufacturing process at the nanometer level or smaller. Therefore, the physical implementation of the interface circuit 20 requires a smaller space. As Figure 5 As shown, area A2 is smaller than area A1. In this embodiment, interface circuit 20 is completely configured within bonding array region R2. In some embodiments, other circuits can be configured in the space between the boundaries of area A2 and area A1 to optimize the space utilization of the semiconductor device.

[0040] In such Figure 6 In another embodiment shown, the bonding elements 30 are arranged in a 5×5 array at a pitch P2, and the bonding elements 30 are arranged in a bonding array region R3 having an area A3. Figure 5 and Figure 6 , pitch P2 is greater than pitch P1 and area A3 is greater than area A2, but interface circuit 20 is still configured within the specified region R2 of area A2. Notably, interface circuit 20 can be adapted to various designs of the bonding array region without reconfiguring the components within interface circuit 20. In other words, the configuration of interface circuit 20 can be independent of the configuration of the corresponding bonding component 30. In some embodiments, other circuits can be configured in the space between the boundaries of area A2 and area A3 to optimize space utilization of the semiconductor device.

[0041] Figure 7 A portion of a semiconductor die according to some embodiments of the present disclosure is schematically shown in cross-section. Figure 7 As shown, semiconductor die 500 includes substrate 502, electronic components of functional circuit 510, interface circuit 520, bonding component 530, and electronic components of interconnect wiring structure 504. Substrate 502 can be a semiconductor substrate including an isolation region or a semiconductor substrate. The electronic components for functional circuit 510 and the electronic components for interface circuit 520 are formed in substrate 502. Bonding component 530 is electrically connected to the electronic components in interface circuit 520 via interconnect wiring structure 504.

[0042] The electronic components for functional circuit 510 and the electronic components for interface circuit 520 may include active components such as transistors, passive components such as capacitors, resistors, etc., or a combination thereof. In some embodiments, the electronic components for functional circuit 510 and the electronic components for interface circuit 520 may be partially integrated into substrate 502 and manufactured using nanoscale or smaller semiconductor manufacturing processes.

[0043] The interconnect wiring structure 504 includes multiple metal layers Mx and multiple intervening dielectric layers to establish the required electrical transmission paths for the electronic components of the functional circuit 510 and the electronic components of the interface circuit 520. In some embodiments, the bonding component 530 includes bonding pads, which are optionally manufactured using the same method as the metal layers Mx in the interconnect wiring structure 504. In some embodiments, the bonding component 530 includes microbumps formed in the form of conductive balls / pillars, etc.

[0044] In this embodiment, some electronic components of the interface circuit 520 are electrically connected to corresponding bonding components 530 via the interconnect wiring structure 504. These electronic components include a transceiver and a receiver. In some embodiments, a portion of the electronic components of the interface circuit 520 overlaps with one or more of the bonding components 530. Specifically, the bonding components 530 are disposed within the bonding array region R530, and the interface circuit 520 is disposed within the bonding array region R530. The interface circuit 520 occupies a smaller area than the bonding array region R530, and the area between the outermost components of the interface circuit 520 and the boundary of the bonding array region R530 can be used for other chip-level layout and routing to optimize the pitch utilization of the substrate 502.

[0045] Functional circuit 510 can be configured adjacent to interface circuit 520, and a portion of functional circuit 510 can be located within bonding array region R530. In some embodiments, a portion of the electronic components of functional circuit 510 overlap with one or more bonding components 530. Functional circuit 510 can be in signal communication with interface circuit 520, such that electrical signals from functional circuit 510 can be transmitted to bonding component 530 via interface circuit 520, and signals input from bonding component 530 can be transmitted to functional circuit 510 via interface circuit 520.

[0046] The interconnect wiring structure 504 includes multiple metal layers Mx that establish interleaved signal transmission paths between the electronic components of the interface circuit 520 and the bonding assembly 530. The configuration of the electronic components of the interface circuit 520 can be independent of the configuration of the corresponding bonding assembly 530. For example, when viewed from a top view, the electronic components (transceivers or receivers) of the interface circuit 520 and the corresponding bonding assembly 530 for transmitting the same signal can be located in two separate locations, while other components (transceivers or receivers) of the interface circuit 520 and the corresponding bonding assembly 530 can be located in two separate locations. The interface circuit 520 and / or the bonding assembly 530 can be located between two separate locations. In an alternative embodiment, two adjacent electronic components (transceivers or receivers) of the interface circuit 520 can be separated by a pitch that is smaller than the pitch of the two corresponding bonding assemblies 530 to which they are connected.

[0047] The structure of the semiconductor die 500 may be considered as an embodiment of the first semiconductor die 100 or the second semiconductor die 200 described in the previous embodiments. For example, the functional circuit 510 may be Figures 2 to 4 In the embodiment of the functional circuit 110 or the functional circuit 210 shown, the interface circuit 520 may be Figures 2 to 4 In the embodiment of the first interface circuit 120 or the second interface circuit 220 shown, the bonding component 530 may be Figure 3The embodiment of the first bonding component 130 or the second bonding component 230 shown. Therefore, the interface circuit 520 and the bonding component 530 can be Figures 1 to 4 A portion of the interface 300 is shown. In addition, Figure 5 and Figure 6 The illustrated configuration of the interface circuit 20 and the bonding assembly 30 can be adapted to the structure of the semiconductor die 500 , making the interface circuit 520 compatible with various bond array designs.

[0048] Figure 8 The semiconductor device according to some embodiments of the present disclosure is schematically shown in a cross-sectional view. The semiconductor device 2000 includes a first semiconductor die 500A and a second semiconductor die 500B bonded to each other in a face-to-face manner. Each of the first semiconductor die 500A and the second semiconductor die 500B may be similar to Figure 7 The semiconductor die 500 depicted in FIG. Figure 7 The description of the components of semiconductor die 500 in FIG. 1 applies to the corresponding components of semiconductor device 2000 .

[0049] The first semiconductor die 500A includes a first substrate 502A, a first interface circuit 520A, and a first bonding element 530A. The first bonding element 530A is disposed within a first bonding array region R530A, and the first interface circuit 520A is disposed within the first bonding array region R530A. Specifically, the first semiconductor die 500A also includes an internal interconnect wiring structure 504A located between the first interface circuit 520A and the first bonding element 530A. The internal interconnect wiring structure 504A includes a metal layer that establishes a signal transmission path between the first interface circuit 520A and the first bonding element 530A.

[0050] Second semiconductor die 500B includes a second substrate 502B, a second interface circuit 520B, and a second bonding assembly 530B. Second bonding assembly 530B is disposed within second bonding array region R530B, and second interface circuit 520B is disposed within second bonding array region R530B. Specifically, second semiconductor die 500B also includes an internal interconnect wiring structure 504B located between second interface circuit 520B and second bonding assembly 530B. Internal interconnect wiring structure 504B includes a metal layer that establishes a signal transmission path between second interface circuit 520B and second bonding assembly 530B.

[0051] In this embodiment, the first semiconductor die 500A is oriented with its front side (the side with circuitry implemented) facing upward, and the second semiconductor die 500B is oriented with its front side (the side with circuitry implemented) facing downward. The second bonding array region R530B is substantially a mirror image of the first bonding array region R530A, and the first bonding components 530A and the second bonding components 530B are connected in a one-to-one manner. Figure 8 In the bonding structure shown, the first interface circuit 520A and the second interface circuit 520B are located between the first substrate 502A and the second substrate 502B, which can be understood as a face-to-face bonding structure.

[0052] In an embodiment, first bonding component 530A and second bonding component 530B are pads. Bonding surface FF is formed by first bonding component 530A in contact with second bonding component 530B and dielectric surrounding first bonding component 530A in contact with dielectric surrounding second bonding component 530B. In alternative embodiments, first bonding component 530A and second bonding component 530B may be microbumps or other types of three-dimensional interconnect components, and underfill may be further disposed between first semiconductor die 500A and second semiconductor die 500B to surround the bond structure formed by first bonding component 530A connecting to second bonding component 530B.

[0053] In this embodiment, first semiconductor die 500A and second semiconductor die 500B are connected via interface 600, which is comprised of first interface circuit 520A, first bonding component 530A, second interface circuit 520B, and second bonding component 530B. Interface 600 is considered a three-dimensional interconnect technology for signal communication between semiconductor dies in a three-dimensional stacked structure. Interface 600 can have a design similar to interface 300 described in the previous embodiment.

[0054] In some embodiments, the first semiconductor die 500A may be Figures 1-4 Referring to the previous embodiment, the first interface circuit 520A may include Figure 3 The interface logic circuit 122, the transceiver 124 and the receiver 126 are shown. The transceiver and the receiver in the interface circuit 520A are electrically connected to the first bonding component 530A. In addition, the first bonding component 530A can be configured similarly Figure 5 and Figure 6The array shown is an array of arrays, but the present disclosure is not limited thereto. The interface logic circuitry, transceivers, and receivers in the interface circuitry 520A can be arranged within the first bonding array region R530A. In some embodiments, the pitch of the transceivers and receivers in the interface circuitry 520A can be smaller than the pitch of the first bonding element 530A. In some embodiments, a portion of the first interface circuitry 520A overlaps with one or more of the first bonding elements 530A. In some embodiments, the configuration of the transceivers and receivers in the interface circuitry 520A can be independent of the configuration of the first bonding element 530A.

[0055] In some embodiments, the second semiconductor die 500B may be Figures 1-4 The embodiment of the second semiconductor die 200 is shown. Referring to the above embodiments, the second interface circuit 520B may include Figure 3 The interface logic circuit 222, transceiver 224 and receiver 226 are shown. The second bonding component 530B can be configured similarly Figure 5 and Figure 6 The array shown is an array of arrays, but the present disclosure is not limited thereto. The second interface circuit 520B is disposed within the second bonding array region R530B. The interface logic circuit, the transceiver, and the receiver in the second interface circuit 520B are disposed within the second bonding array region R530B. The transceiver and the receiver in the second interface circuit 520B are electrically connected to the second bonding element 530B, respectively. The pitch of the transceiver and the receiver in the second interface circuit 520B are smaller than the pitch of the second bonding element 530B. A portion of the second interface circuit 520B overlaps with one or more of the second bonding elements 530B.

[0056] In some embodiments, the method for configuring the interface 600 of the semiconductor device 2000 may include providing a first bonding array region R530A for configuring the first bonding component 530A implemented in the first semiconductor die 500A. In some embodiments, the first bonding array region R530A may be determined based on a specified rule for arranging the first bonding components 530A at a pitch. For example, the first bonding array region R530A may be configured to arrange the first bonding components 530A at a pitch ranging from 6 microns to 16 microns, but the present invention is not limited thereto. In other alternative embodiments, the pitch or the first bonding components 530A may be determined based on the design of the product.

[0057] Subsequently, the method further provides a first interface circuit 520A implemented within a first bonding array region R530A in the first semiconductor die 500A. The first interface circuit 520A may include interface logic circuitry, a transceiver, and a receiver fabricated using a semiconductor manufacturing process. The electronic components in the first interface circuit 520A may have dimensions as small as approximately nanometers. Typically, the dimensions and connections of the electronic components in the first interface circuit 520A are predetermined, thereby determining the area within which the interface circuit 520A is configured.

[0058] In this embodiment, the first interface circuit 520A is connected via Figure 8 The illustrated interconnect wiring structure 504A is electrically connected to the corresponding first bonding element 530A, providing a path for signal transmission. Therefore, the first interface circuit 520A is configured within the first bonding array region R530A, regardless of the relative position of the first bonding element 530A. Furthermore, the same specifications for the size and connection relationships of the electronic components in the first interface circuit 520A are compatible with various pitch designs of the first bonding element 530A, providing flexible design rules for manufacturing the first semiconductor die 500A of the semiconductor device 2000. Since the first interface circuit 520A requires a smaller area, the substrate has more space for other circuits or components, increasing the design flexibility of the semiconductor device 2000.

[0059] The method also includes providing a second interface circuit 520B and a second bonding component 530B implemented in a second semiconductor die 500B. Similar to the first semiconductor die 500A, the second bonding component 530B in the second semiconductor die 500B can be configured in a second bonding array region R530B, and the second interface circuit 520B in the second semiconductor die 500B can be configured within the second bonding array region R530B. Furthermore, the configuration of the second interface circuit 520B can be independent of the configuration of the second bonding component 530B. Therefore, the same dimensions and component connection relationships in the second interface circuit 520B are compatible with various pitch designs of the second bonding component 530B. In some embodiments, the second bonding array region R530B can be used to arrange the second bonding components 530B at a pitch ranging from 6 microns to 16 microns, but the present disclosure is not limited thereto. In other alternative embodiments, the pitch or the second bonding component 530B can be determined based on the design of the product.

[0060] The method further includes bonding the first bonding element 530A to the second bonding element 530B. In an embodiment, the second bonding array region R530B may be substantially a mirror image of the first bonding array region R530A, and the first semiconductor die 500A and the second semiconductor die 500B are bonded in a face-to-face manner. Figure 8As shown, first semiconductor die 500A further includes an internal interconnect wiring structure 504A that establishes a path for signal transmission, so the configuration of first interface circuit 520A can be independent of the configuration of first bonding element 530A. Similarly, second interface circuit 520B in second semiconductor die 500B is electrically connected to second bonding element 530B via internal interconnect wiring structure 504B, and the configuration of second interface circuit 520B can be independent of the configuration of second bonding element 530B.

[0061] In summary, the semiconductor device according to some embodiments of the present disclosure includes a plurality of semiconductor dies bonded in a face-to-face manner. The interface between the semiconductor dies includes an interface circuit and a bonding component formed in each semiconductor die. The interface circuit can be configured in a determined area compatible with various pitch designs of the bonding component. Therefore, the configuration of the interface is flexible. In addition, the interface circuit is concentrated in the determined area, so that the substrate implemented together with the interface circuit can have a flexible pitch utility.

[0062] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device, characterized in that: include: a first semiconductor die comprising a first substrate, a first interface circuit, and a first bonding assembly, wherein the first bonding assembly is disposed within a first bonding array region and the first interface circuit is disposed within the first bonding array region; as well as The second semiconductor die includes a second substrate, a second interface circuit and a second bonding component, wherein the first bonding component is connected to the second bonding component, the first interface circuit and the second interface circuit are located between the first substrate and the second substrate, and the first semiconductor die and the second semiconductor die are interconnected through an interface formed by the first interface circuit, the first bonding component, the second interface circuit and the second bonding component.

2. The semiconductor device according to claim 1, wherein The first interface circuit includes an interface logic circuit, a transceiver, and a receiver, and the interface logic circuit, the transceiver, and the receiver are configured inside the first bonding array region.

3. The semiconductor device according to claim 2, wherein The transceiver and the receiver are electrically connected to the first bonding component, respectively.

4. The semiconductor device according to claim 2, wherein A pitch among the transceiver and the receiver is smaller than a pitch of the first bonding assembly.

5. The semiconductor device according to claim 1, wherein A portion of the first interface circuit overlaps one or more of the first engagement components.

6. The semiconductor device according to claim 1, wherein The first semiconductor die also includes functional circuitry, and the functional circuitry is in signal communication with the first interface circuitry.

7. The semiconductor device according to claim 6, wherein: A portion of the functional circuit is disposed inside the first bonding array region.

8. The semiconductor device according to claim 1, wherein The first semiconductor die also includes an interconnect wiring structure disposed between the first bonding component and the first interface circuit.

9. The semiconductor device according to claim 1, wherein The first bonding component and the second bonding component include bonding pads, microbumps, or other types of three-dimensional interconnect components.

10. The semiconductor device according to claim 1, wherein The second bonding element is arranged in a second bonding array region that is substantially a mirror image of the first bonding array region.

11. The semiconductor device according to claim 10, wherein The second interface circuit is configured inside the second bonding array region.

12. The semiconductor device according to claim 10, wherein The second interface circuit includes an interface logic circuit, a transceiver, and a receiver, and the interface logic circuit, the transceiver, and the receiver are configured inside the second bonding array region.

13. The semiconductor device according to claim 12, wherein: The transceiver and the receiver are electrically connected to the second bonding component, respectively.

14. The semiconductor device according to claim 12, wherein A pitch among the transceiver and the receiver is smaller than a pitch of the second bonding assembly.

15. The semiconductor device according to claim 1, wherein A portion of the second interface circuit overlaps one or more of the second engagement components.

16. The semiconductor device according to claim 1, wherein The second semiconductor die also includes functional circuitry, and the functional circuitry is in signal communication with the second interface circuitry.

17. The semiconductor device according to claim 16, wherein A portion of the functional circuit is disposed inside the second bonding array region of the second bonding element.

18. The semiconductor device according to claim 1, wherein The second semiconductor die also includes an interconnect wiring structure disposed between the second bonding element and the second interface circuit.

19. A method for configuring an interface of a semiconductor device, characterized in that: include: providing a first bond array region for configuring a first bond assembly implemented in a first semiconductor die; providing a first interface circuit implemented within the first bonding array region in the first semiconductor die; providing a second interface circuit and a second bonding assembly implemented in a second semiconductor die; as well as The first engagement component is connected to the second engagement component.

20. The method for configuring a semiconductor device interface according to claim 19, wherein: The first interface circuit includes an interface logic circuit, a transceiver, and a receiver, and the interface logic circuit, the transceiver, and the receiver are configured inside the first bonding array region.

21. The method for configuring a semiconductor device interface according to claim 20, wherein: The transceiver and the receiver are electrically connected to the first bonding element, respectively, and a pitch between the transceiver and the receiver is smaller than a pitch between the first bonding element.

22. The method for configuring a semiconductor device interface according to claim 19, wherein: The second bonding assembly is arranged in a second bonding array region that is substantially a mirror image of the first bonding array region.

23. The method for configuring a semiconductor device interface according to claim 22, wherein: The second interface circuit includes an interface logic circuit, a transceiver, and a receiver, and the interface logic circuit, the transceiver, and the receiver are configured inside the second bonding array region.

24. The method for configuring a semiconductor device interface according to claim 23, wherein: The transceiver and the receiver are electrically connected to the second bonding element, respectively, and a pitch between the transceiver and the receiver is smaller than a pitch between the second bonding element.

25. The method for configuring a semiconductor device interface according to claim 19, wherein: Functional circuitry to be implemented within the first bond array region in the first semiconductor die is also provided.

26. The method for configuring a semiconductor device interface according to claim 19, wherein: Functional circuitry implemented in the second semiconductor die is also provided.

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