Embedded double-sided IGBT module packaging structure and manufacturing method

Abstract

The application provides an embedded double-sided IGBT module packaging structure and a manufacturing method, and belongs to the technical field of electronic devices.The embedded double-sided IGBT module packaging structure comprises a P-type base region, the P-type base region comprises a substrate, an IGBT chip is embedded above the substrate, and a freewheeling diode chip is integrated; an ultrafast recovery diode is embedded in a groove below the substrate; an ultra-low inductive electrode layer is arranged above the P-type base region; a polysilicon gate array is arranged between the ultra-low inductive electrode layer and the P-type base region, the polysilicon gate array is composed of a plurality of polysilicon gates, a gate oxide layer of the polysilicon gate array is formed by alternately introducing aluminum oxide and hafnium oxide through atomic layer deposition technology, and thin films are deposited on the surface of the polysilicon gate array layer by layer to form a multilayer structure; a back interconnection layer is arranged below the P-type base region; a composite buffer layer is arranged above the back interconnection layer; and an N-type gradient-doped drift region is arranged between the composite buffer layer and the P-type base region, thereby solving the problem that a traditional IGBT module is usually designed as a single side, resulting in a low power density.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of electronic devices, and particularly relates to an embedded double-sided IGBT module packaging structure and a manufacturing method. BACKGROUND

[0002] An insulated gate bipolar transistor (IGBT) is a high-voltage and large-current power electronic device, which is widely used in frequency converters, inverters and other fields. The traditional single-sided IGBT module can only install a certain number of chips in a limited space, which limits the total power output of the module. Since the chips can only be concentrated on one side, the space on the other side of the substrate cannot be fully utilized, resulting in that the power density cannot be further improved. In addition, a large amount of heat is generated during the operation of the IGBT, which needs to be dissipated in time through a heat sink to ensure the stability and service life of the device. The heat of the single-chip module is mainly conducted to the heat sink through one side of the substrate, and the heat dissipation path is single, so the heat dissipation efficiency is relatively low. In addition, with the increase of the number of chips, the limitation of single-sided heat dissipation is more obvious, which affects the reliability of the module.

[0003] In order to overcome these problems, double-sided IGBT modules have emerged to improve the power density and heat dissipation performance. SUMMARY

[0004] The embodiment of the application provides an embedded double-sided IGBT module packaging structure and a manufacturing method, which solves the problem that the traditional IGBT module is usually designed as a single side, resulting in low power density and limited heat dissipation performance.

[0005] In view of the above problems, the technical scheme provided by the application is:

[0006] The application provides an embedded double-sided IGBT module packaging structure, which comprises a P-type base region, the P-type base region comprises a substrate, an IGBT chip is embedded above the substrate, and a freewheeling diode chip is integrated, an ultrafast recovery diode is embedded in a groove below the substrate, an ultra-low inductance electrode layer is arranged above the P-type base region, a polysilicon gate array is arranged between the ultra-low inductance electrode layer and the P-type base region, the polysilicon gate array is composed of a plurality of polysilicon gates, a thin film is deposited layer by layer on the surface of the polysilicon gate array to form a multilayer structure, a back interconnection layer is arranged below the P-type base region, a composite buffer layer is arranged above the back interconnection layer, and an N-type gradient-doped drift region is arranged between the composite buffer layer and the P-type base region.

[0007] As a preferred technical scheme of the application, the ultra-low inductance electrode layer adopts a gradient copper+graphene composite material, and the thickness is 75-85 mu m, which is designed as a fractal dendritic copper electrode.

[0008] As a preferred technical solution of the present application, the back interconnection layer is a multi-layer structure of titanium + nickel + silver, in a honeycomb silver mesh design, a titanium layer is deposited on the bottom surface of the P-type base region by magnetron sputtering, a nickel layer is deposited on the titanium layer by electrochemical deposition, and a silver layer is deposited on the nickel layer by pulse plating technology.

[0009] As a preferred technical solution of the present application, the composite buffer layer is composed of multiple layers of semiconductor materials with different doping concentrations, and the composite layer includes silicon dioxide, aluminum nitride and molybdenum.

[0010] As a preferred technical solution of the present application, the doping concentration of the N-type gradient-doped drift region gradually decreases with increasing depth, and the silicon of the P-type base region is deposited layer by layer using MBE technology to generate a controllable silicon epitaxial layer.

[0011] As a preferred technical solution of the present application, the upper surface of the polysilicon gate array and the ultra-low inductive electrode layer are connected through a contact hole filled with tungsten metal between the electrode layer and the gate array, forming a low-resistance electrical connection, and the lower surface and the upper surface of the P-type base region are connected through ion implantation technology between the gate array and the base region to form a PN junction, the upper surface of the composite buffer layer and the lower surface of the N-type gradient-doped drift region are activated by plasma treatment to activate the drift region and the buffer layer surface, and then bonded, and the lower surface of the composite buffer layer and the back interconnection layer are connected by laser heating.

[0012] As a preferred technical solution of the present application, microcolumn arrays are embedded on the upper and lower surfaces of the substrate, and are misaligned with the embedded IGBT chip and ultra-fast recovery diode, the microcolumn arrays on the upper and lower surfaces are connected, the microcolumn arrays on the upper surface are connected to the substrate by silver sintering, and the microcolumn arrays on the lower surface are connected through the N-type gradient-doped drift region by copper through holes and extend to the back interconnection layer.

[0013] On the other hand, a method for manufacturing an embedded double-sided IGBT module packaging structure includes the following steps:

[0014] S1, first, an alumina + silica composite substrate is prepared by plasma activation sintering, and a fractal electrode pattern is etched on the front surface of the substrate using ultraviolet laser, which is topologically matched with the ultra-low inductive electrode layer;

[0015] S2, second, a chip groove is etched on the surface of the P-type base region using femtosecond laser, the depth is matched with the polysilicon gate array, and then nano-silver solder is directionally arranged to fill the gate array groove;

[0016] S3, then, laser drilling through the N-type gradient doped drift region, a mixed solution of nitric acid and hydrofluoric acid is used for wet etching, the electroplating liquid is disturbed by ultrasonic waves, and fractals flow channels are constructed on the surface of the composite buffer layer again by using femtosecond laser double-photon polymerization, and aluminum oxide nanowires are dispersed into hafnium oxide to directly contact the composite buffer layer;

[0017] S4, finally, a titanium, nickel and silver stack is deposited on the surface of the back interconnection layer, and the titanium, nickel and silver stack is locally heated by using a pulsed laser to realize connection with a packaging shell.

[0018] Compared with the prior art, the application has the following beneficial effects:

[0019] (1) The surface electrode design of the fractal dendritic copper electrode is adopted, the inductive resistance is significantly reduced, the switching speed and the electric energy conversion efficiency of the module are improved, the back interconnection layer with a honeycomb-shaped silver grid design improves the reliability and the heat conduction efficiency of the electrical connection, and the high-performance operation of the device is ensured, the micro column array embedded on the upper and lower surfaces of the substrate optimizes the heat dissipation path and reduces the thermal resistance, and the heat dissipation efficiency is further improved.

[0020] (2) The design of the N-type gradient doped drift region and the gate array optimizes the electric field distribution, reduces the leakage current, and improves the voltage resistance of the device, the composite buffer layer and the upper gradient matching effectively reduce the thermal stress, and the stability and reliability of the device under temperature change conditions are improved.

[0021] The above description is only a summary of the technical scheme of the application, in order to more clearly understand the technical means of the application, the application can be implemented according to the content of the specification, and in order to make the above and other purposes, characteristics and advantages of the application more obvious and easy to understand, the following specific embodiments of the application are described. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 is a structure diagram of an embedded double-sided IGBT module packaging structure disclosed by the application;

[0023] Figure 2 is a structure diagram of a micro column array of an embedded double-sided IGBT module packaging structure disclosed by the application;

[0024] Figure 3 is a flowchart of a manufacturing method of an embedded double-sided IGBT module packaging structure disclosed by the application;

[0025] Mark 10, P-type base region; 101, substrate; 102, IGBT chip; 103, micro column array; 20, polysilicon gate array; 30, ultra-low inductive electrode layer; 40, back interconnection layer; 50, N-type gradient doped drift region; 60, composite buffer layer. DETAILED DESCRIPTION

[0026] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present application.

[0027] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present application.

[0028] It should be noted that: similar reference numerals and letters indicate similar items in the following drawings, therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0029] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0030] In addition, the terms "first", "second" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0031] Example One

[0032] Referring to the drawings Figures 1-2As shown, the present application provides a technical solution: an embedded double-sided IGBT module packaging structure, comprising a P-type base region 10, the P-type base region 10 comprises a substrate 101, the upper part of the substrate 101 is embedded with an IGBT chip 102, and a freewheeling diode chip is integrated, the chip is sintered using nano-silver copper composite solder, an ultra-fast recovery diode is embedded in the lower groove, the P-type base region 10 is injected with boron ions and laser annealing is performed, an ultra-low inductance electrode layer 30 is arranged above the P-type base region 10, a polysilicon gate array 20 is arranged between the ultra-low inductance electrode layer 30 and the P-type base region 10, the polysilicon gate array 20 is composed of a plurality of polysilicon gates, the groove depth is 11.5-12.5 μm, the gate oxide thickness is 80 nm, the gate oxide layer is deposited on the surface of the polysilicon gate array 20 by alternately introducing aluminum oxide and hafnium oxide by atomic layer deposition technology, a thin film is deposited layer by layer to form a multilayer structure, the switching state of the IGBT is controlled, an MOSFET structure is formed, a back interconnection layer 40 is arranged below the P-type base region 10, a composite buffer layer 60 is arranged above the back interconnection layer 40, and an N-type gradient-doped drift region 50 is arranged between the composite buffer layer 60 and the P-type base region 10.

[0033] The embodiment of the present application is also realized by the following technical solutions.

[0034] In the embodiment of the present application, the ultra-low inductance electrode layer 30 adopts a gradient copper+graphene composite material, the thickness is 75-85 μm, it is designed as a fractal dendritic copper electrode, the inductance resistance is reduced, the switching speed and efficiency of the module are improved, the copper powder is made by using a hot pressing process, and 1-10 wt.% of graphene nanosheets are added to the copper powder (more than 8 wt.% leads to a decrease in conductivity, and less than 5 wt.% is insufficient for heat conduction improvement), the hot pressing temperature is lower than the melting point of copper, so as to avoid breaking the graphene structure, and then vertical graphene nanowalls are grown on the surface of the copper matrix by using chemical vapor deposition to improve the interface bonding strength.

[0035] In the embodiment of the present application, the back interconnection layer 40 is a multi-layer structure of titanium+nickel+silver, which is designed as a honeycomb silver grid, the pore size is 90-105 μm, and the wall thickness is 18-22 μm, a titanium layer (barrier layer) is deposited on the bottom surface of the P-type base region 10 by magnetron sputtering, a nickel layer (transition layer) is deposited on the titanium layer by electrochemical deposition, a silver layer (conductive layer) is deposited on the nickel layer by pulse plating technology, a tin-bismuth alloy is introduced between the silver layer and the nickel layer, a high-strength interface is formed by transient liquid phase diffusion, the internal region of the chip is connected to the external lead, good electrical connection and heat conduction are ensured, and the copper layer is locally thickened.

[0036] In an embodiment of the application, the composite buffer layer 60 is composed of multiple layers of semiconductor materials with different doping concentrations, including silicon dioxide + aluminum nitride + molybdenum, the composite buffer layer 60 is prepared by a low-pressure chemical deposition technology to prepare a silicon dioxide layer, then a plasma-assisted atomic layer deposition technology is used to prepare an aluminum nitride layer on the silicon dioxide layer, and finally a physical vapor deposition technology is used to prepare a molybdenum layer on the aluminum nitride layer, the ratio of silicon dioxide: aluminum nitride: molybdenum is 57:14:29, wherein the ratio is based on the fact that the breakdown field strength of silicon dioxide is >8 MV / cm (≥150 nm is required), and an excessive thickness will increase the thermal resistance, the aluminum nitride is required to cover the surface defects (RMS <0.5 nm) and at the same time avoid stress accumulation, and the molybdenum can offset the difference in the coefficient of thermal expansion between the aluminum nitride and the silicon.

[0037] Wherein, the stress compensation is achieved by the fact that the coefficient of thermal expansion of molybdenum is close to that of aluminum nitride and higher than that of silicon. When the temperature changes, the thermal expansion or contraction of the molybdenum layer is similar to that of the aluminum nitride layer, and the compression stress generated by the aluminum nitride layer due to the higher coefficient of thermal expansion than the silicon is offset by inserting the molybdenum layer between the aluminum nitride layer and the silicon layer.

[0038] In an embodiment of the application, the doping concentration of the N-type gradiently-doped drift region 50 gradually decreases with the increase of the depth, the MBE technology is used to perform layer-by-layer deposition on the silicon of the P-type base region 10 to generate a silicon epitaxial layer with controllable doping concentration, the doping concentration gradually decreases from 1×1018 cm-2 to 5×1018 cm-2 linearly, and the doping concentration of the P-type base region 10 is 1×1019 cm-2. 14 cm -3 The linear gradient is from 1×1018 cm-2 to 5×1018 cm-2. 14 cm -3 This optimizes the electric field distribution, reduces the leakage current, and improves the withstand voltage capability.

[0039] In an embodiment of the application, the upper surface of the polysilicon gate array 20 and the ultra-low inductive electrode layer 30 are connected through a tungsten metal filled in the contact hole between the electrode layer and the gate array to form a low-resistance electrical connection, the diameter of the tungsten plug is 5 microns to ensure sufficient contact area, the lower surface thereof and the upper surface of the P-type base region 10 form a PN junction between the gate array and the base region through ion implantation technology, the self-alignment technology is used to ensure that the implantation region is aligned with the gate array, the junction depth is within ±5 nm, the upper surface of the composite buffer layer 60 and the lower surface of the N-type gradiently-doped drift region 50 are activated by plasma treatment to activate the surfaces of the drift region and the buffer layer, and then are bonded to form a strong physical connection, the bonding strength is more than 15 MPa to ensure the mechanical stability and reliability of the connection, and the lower surface of the composite buffer layer 60 and the back interconnection layer 40 are connected through laser heating to form a transient liquid phase between the composite buffer layer 60 and the back interconnection layer 40, and then diffuse to form a strong connection, the diffusion depth is controlled within 10 μm±0.5 μm to ensure the uniformity and reliability of the connection.

[0040] In the embodiment of the present application, the microcolumn array 103 is embedded on both upper and lower surfaces of the substrate 101 and is staggered with the embedded IGBT chip 102 and super-fast recovery diode. The microcolumn arrays 103 on the upper and lower surfaces are communicated and doped with diamond in the microcolumn gap and are subjected to chemical deposition. The microcolumn array 103 on the upper surface is connected to the substrate 101 through silver sintering, and the microcolumn array 103 on the lower surface is connected to the N-type gradient-doped drift region 50 through a copper via and extends to the back interconnection layer 40. In the embodiment, the microcolumn array 103 on the upper surface is silicon, and the microcolumn array 103 on the lower surface is copper. The microcolumn arrays 103 on the upper and lower surfaces are staggered and connected to the back interconnection layer 40 through the N-type gradient-doped drift region 50 via the copper via, thereby forming a three-dimensional heat dissipation path. The microcolumn diameter is 9-12 μm. When the microcolumn diameter is less than 20 μm, the longitudinal thermal conductivity is significantly improved (reference: DOI: 10.1016 / j.ijheatmasstransfer.2019.118940).

[0041] Embodiment two

[0042] Referring to the accompanying Figure 3 The manufacturing method of the embedded double-sided IGBT module packaging structure provided by the embodiment of the present application comprises the following steps:

[0043] S1, first, an alumina+silica composite substrate 101 is prepared by plasma activation sintering. The sintering temperature is 1650℃±10℃, the pressure is 50MPa, the holding time is 30min, and a fractal electrode pattern is etched on the front surface of the substrate 101 using an ultraviolet laser, which is topologically matched with the ultra-low inductive electrode layer 30. The line width is 50μm±3μm, the copper layer thickness is 320μm, the surface roughness Ra is <0.1μm, and the electrode layer inductance is reduced to 1-2nH / cm 2 . The matching degree of the thermal expansion coefficient (CTE) of the substrate 101 and the electrode layer is 98%, which avoids thermal mismatch cracking.

[0044] S2, second, a chip groove is etched on the surface of the P-type base region 10 using a femtosecond laser. The groove depth is matched with the polysilicon gate array 20, the groove depth error is ±2μm, the sidewall angle is 89.5°, the surface carbonization layer thickness is <50nm, a 0.5T vertical magnetic field is applied, and then nano-silver solder directional arrangement is performed to fill the gate array groove (line width 2μm). The temperature is 225℃ / pressure 12MPa, the porosity is <1%, the gate leakage current is reduced to below 1nA, and the gate oxide integrity (TDDB lifetime) is improved by 3 times.

[0045] S3, then, laser drilling (aperture 60 pm) through the N-type graded-doped drift region 50, depth 720 pm (aspect ratio 12:1), wet etching with a mixture of nitric acid and hydrofluoric acid (ratio 10:1), etching rate 8 pm / min, using 28 kHz ultrasonic agitation to ensure copper filling to the graded-doped interface of the drift region, current density 1.5 A / dm 2 , deposition rate 8 pm / h, resistance uniformity ±2%, drift region electric field distribution optimization, breakdown voltage increased to 7.5 kV (conventional structure 6.5 kV), again, femtosecond laser two-photon polymerization to construct fractal flow channels (minimum channel 50 pm) on the surface of the composite buffer layer 60, channel aspect ratio 15:1, dispersion of aluminum oxide nanowires (5 wt.%) into hafnium oxide, direct contact with the composite buffer layer 60, flow rate 2 m / s, pressure drop <5 kPa, heat transfer coefficient 12000 W / m 2 ·K, composite buffer layer 60 heat conduction path optimization, thermal resistance reduced to 0.09 K / W;

[0046] S4, finally, depositing a titanium, nickel and silver stack (total thickness 50 nm) on the surface of the back interconnection layer 40, cycle number 500 times, film thickness uniformity ±1%, breakdown field strength 12 MV / cm, using pulsed laser (10 ps, 100 kHz) to locally heat the titanium, nickel and silver stack, achieving connection with the packaging shell, welding strength >120 MPa, heat-affected zone <10 pm.

[0047] The above only is the preferred embodiment of the present application, and is not used to limit the present application, for those skilled in the art, the present application can have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0048] It should be understood that the specific order or hierarchy of steps in the processes disclosed is an example of exemplary approaches. Based upon design preferences, it should be understood that the specific order or hierarchy of steps in the processes can be re-arranged while remaining within the scope of the present disclosure. The accompanying method claims present elements of the various steps in exemplary order and are not intended to be limited to the specific order or hierarchy presented.

[0049] In the detailed description above, various features are grouped together in single embodiments for the purpose of streamlining the disclosure. This method of disclosure should not be interpreted as reflecting a necessity to disclose features in any single patent. Rather, according to the inventive concept, features can be combined in any single patent in one or more claims. Thus, the disclosure should be understood to include any single patent having one or more claims reflecting the features of the embodiments described above.

[0050] Those skilled in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein can be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans can implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0051] The steps of a method or algorithm described in connection with the embodiments disclosed herein can be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module can reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium can be integral to the processor. The processor and the storage medium can reside in an ASIC. The ASIC can reside in a user terminal. In the alternative, the processor and the storage medium can reside as discrete components in a user terminal.

[0052] For a software implementation, the techniques described in this application can be implemented with modules (e.g., procedures, functions, and so on) that perform the functions described herein. The software codes can be stored in memory units and executed by processors. The memory unit can be implemented within the processor or external to the processor, in which case it can be communicatively coupled to the processor via various means as is known in the art.

[0053] The above description includes examples of one or more embodiments. Of course, not all possible combinations of components or methods described above can be claimed as an embodiment, but one of ordinary skill in the art will recognize that many such further combinations and permutations of the embodiments described are possible. Accordingly, the described embodiments are intended to embrace all such alterations, modifications and variations which fall within the scope of the appended claims. Additionally, where the description or the claims recite "a", "an" or a "the" one or more of elements, this does not exclude multiple numbers for this element. Further, where the description or the claims recite that an element can or can not be used, this indicates that the element is optional. Additionally, the use of "a" or "an" or "the" preceding an element does not exclude the presence of more than one of the element. Further, the description or the claims can include a plurality of means plus function components consisting of a specific combination of means. The method or process of claims can be implemented by one or more processors or one or more processors in one or more machines where the one or more machines can each comprise one or more processors. The description or the claims can further include a plurality of identifying steps consisting of a specific combination of steps. The machine can be configured to perform the methods or processes of the claims by one or more processors disposed in the machine.

Claims

1. An embedded dual-face IGBT module package structure, characterized by, The application relates to a super low inductance IGBT device, which comprises a P-type base region (10), wherein a substrate (101) is embedded with an IGBT chip (102) above the substrate (101) and integrated with a freewheeling diode chip, an ultrafast recovery diode is embedded in a groove below the substrate (101), an ultra low inductance electrode layer (30) is arranged above the P-type base region (10), the ultra low inductance electrode layer (30) is made of gradient copper + graphene composite material and is designed as a fractal dendritic copper electrode, a polysilicon gate array (20) is arranged between the ultra low inductance electrode layer (30) and the P-type base region (10), the polysilicon gate array (20) is composed of a plurality of polysilicon gates, a thin film is deposited on the surface of the polysilicon gate array (20) layer by layer to form a multilayer structure, a back interconnection layer (40) is arranged below the P-type base region (10), the back interconnection layer (40) is a multilayer structure of titanium + nickel + silver and is designed as a honeycomb silver mesh, a composite buffer layer (60) is arranged above the back interconnection layer (40), the composite buffer layer (60) is composed of a plurality of semiconductor materials with different doping concentrations, and the composite layer comprises silicon dioxide, aluminum nitride and molybdenum, and an N-type gradient doped drift region (50) is arranged between the composite buffer layer (60) and the P-type base region (10).

2. The embedded dual-face IGBT module package structure according to claim 1, wherein, The thickness of the ultra low inductance electrode layer (30) is 75-85 mu m.

3. The embedded dual-face IGBT module package structure of claim 2, wherein, The back interconnection layer (40) is formed by the following steps: depositing a titanium layer on the bottom surface of the P-type base region (10) through magnetron sputtering, depositing a nickel layer on the titanium layer through electrochemical deposition, and depositing a silver layer on the nickel layer through pulse plating technology.

4. The embedded dual-face IGBT module package structure of claim 3, wherein, The doping concentration of the N-type gradient doped drift region (50) gradually decreases with the increase of the depth, the silicon of the P-type base region (10) is deposited layer by layer using MBE technology to generate a silicon epitaxial layer with controllable doping concentration.

5. The embedded dual-face IGBT module package structure of claim 4, wherein, The upper surface of the polysilicon gate array (20) and the ultra low inductance electrode layer (30) are connected through a contact hole filled with tungsten metal between the electrode layer and the gate array to form a low-resistance electrical connection, the lower surface and the upper surface of the P-type base region (10) are connected through ion implantation technology to form a PN junction between the gate array and the base region, the upper surface of the composite buffer layer (60) and the lower surface of the N-type gradient doped drift region (50) are activated through plasma treatment to activate the drift region and the buffer layer surface, and then are bonded, and the lower surface of the composite buffer layer (60) and the back interconnection layer (40) are connected through laser heating.

6. The embedded dual-face IGBT module package structure of claim 1, wherein, Micro column arrays (103) are embedded on the upper and lower surfaces of the substrate (101) and are misaligned with the embedded IGBT chip (102) and ultrafast recovery diode, the micro column arrays (103) on the upper and lower surfaces are communicated, the micro column array (103) on the upper surface is connected to the substrate (101) through silver sintering, and the micro column array (103) on the lower surface penetrates through the N-type gradient doped drift region (50) through a copper through hole and extends to the back interconnection layer (40).

7. A manufacturing method of the embedded double-sided IGBT module packaging structure, applied to the embedded double-sided IGBT module packaging structure in any one of claims 1-6, characterized in that, The application further relates to a preparation method of the super low inductance IGBT device, which comprises the following steps: S1, first, the plasma activated sintering preparation of alumina + silicon oxide composite substrate (101), using a UV laser etching fractal electrode pattern on the front of the substrate (101), with the super low inductive electrode layer (30) topology matching; S2, second, using femtosecond laser etching chip groove on the surface of the P-type base region (10), the depth and the polysilicon gate array (20) matching, and then nano silver solder directional arrangement, filling the gate array trench; S3, then, laser drilling through the N-type gradient doped drift region (50), a mixture of nitric acid and hydrofluoric acid solution for wet etching, ultrasonic disturbance plating solution, again femtosecond laser two photon polymerization on the surface of the composite buffer layer (60) to build fractal flow channel, the alumina nanowire dispersed to hafnium oxide, direct contact with the composite buffer layer (60); S4, finally, the back interconnection layer (40) surface deposition of titanium, nickel and silver stack, using pulsed laser local heating of titanium, nickel and silver stack, realize the connection with the package shell.

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