Three-level bus voltage balance control system

Abstract

The invention discloses a three-level bus voltage balance control system, which comprises a voltage equalizing module, an algorithm adjusting module and an enabling module, the algorithm adjusting module is located in the previous link of the voltage equalizing module and is suitable for outputting different bus voltage average instruction values through non-zero sequence calculation according to the positive and negative period states of the phase voltage; a first duty ratio signal is obtained by dividing the phase voltage by the bus voltage average instruction value; and the enabling module is suitable for judging the unbalance degree of the bus voltage and controlling the algorithm adjusting module and / or the voltage equalizing module to work according to a judgment result. The method has the advantages that compared with a traditional mode, the algorithm adjusting module is adopted in the process of obtaining the duty ratio through the phase voltage, and unbalance of the bus voltage can be restrained to a certain degree; and through a regulation and control mode of hierarchical bus voltage balance of the enabling module, the influence on the system caused by implementation of bus balance can be minimized.

Description

Technical Field

[0001] The present application relates to the field of renewable energy power generation technology, and in particular to a three-level bus voltage balancing control system. Background Art

[0002] For grid-connected systems, three-phase three-wire system is generally used, such as Figure 1 As shown, the DC / AC unit of the grid-connected system adopts a three-level circuit, the three-phase grid-connected current is a symmetrical current, and the control method is generally the traditional dq control.

[0003] When controlling the DC / AC unit, the three-level midpoint voltage balance is an issue that needs to be addressed, because the midpoint current will cause the bus capacitor voltage to fluctuate, and even cause the upper and lower capacitor voltages V dc1 and V dc2 Uneven distribution will endanger the safe operation of the system. Figure 3 As shown, the prior art adds a voltage balancing module 101 on the basis of the traditional dq control. The voltage balancing module 101 can complete the bus voltage difference V dif =V dc1 -V dc2 After calculation, the difference between it and the reference value 0 is sent to the PI controller to obtain the duty cycle common mode offset Δd and add it to the original duty cycle to obtain the new three-phase duty cycles da and d b d c The essence of the voltage balancing module 101 is to adjust the bus voltage by adjusting the zero-sequence current. A major problem with this method is that the introduced zero-sequence current will increase system losses. Summary of the Invention

[0004] One of the objectives of the present application is to provide a three-level bus voltage balancing control system that can solve at least one of the defects in the above-mentioned background technology.

[0005] In order to achieve at least one of the above-mentioned purposes, the technical solution adopted in the present application is: a three-level bus voltage balancing control system, applied to the control loop of the grid-connected system, including a voltage balancing module, an algorithm adjustment module and an enable module; the voltage balancing module is suitable for adding a duty cycle common-mode offset to the first duty cycle signal output by the previous link, thereby obtaining a second duty cycle signal for suppressing bus voltage imbalance; the algorithm adjustment module is located in the previous link of the voltage balancing module; the algorithm adjustment module is suitable for outputting different bus voltage average command values ​​through non-zero sequence calculation according to the positive and negative cycle states of the phase voltage; the first duty cycle signal for suppressing bus voltage imbalance is obtained by dividing the phase voltage by the corresponding bus voltage average command value; the enable module is suitable for judging the degree of bus voltage imbalance, and controlling the algorithm adjustment module and / or the voltage balancing module to work according to the judgment result.

[0006] Preferably, the algorithm adjustment module is suitable for receiving the upper bus voltage, the lower bus voltage and the phase voltage; the algorithm adjustment module includes a filtering unit and a calculation unit; the filtering unit filters the upper bus voltage and the lower bus voltage to obtain the upper bus voltage average value and the lower bus voltage average value; based on the obtained upper bus voltage average value and the lower bus voltage average value, the calculation unit is suitable for outputting different bus voltage average instruction values ​​according to the different periodic states of the phase voltage.

[0007] Preferably, when the phase voltage is in the positive half cycle, the calculation unit is suitable for directly using the average value of the lower bus voltage as the average bus voltage instruction value; when the phase voltage is in the negative half cycle, the calculation unit is suitable for directly using the average value of the upper bus voltage as the average bus voltage instruction value.

[0008] Preferably, the calculation unit is suitable for subtracting the upper bus voltage and the lower bus voltage from the upper bus voltage average value and the lower bus voltage average value respectively to obtain the upper bus voltage AC value and the lower bus voltage AC value; based on the obtained upper bus voltage average value, lower bus voltage average value, upper bus voltage AC value and lower bus voltage AC value, the calculation unit outputs different bus voltage average instruction values ​​according to the different periodic states of the phase voltage.

[0009] Preferably, when the phase voltage is in the positive half cycle, the calculation unit is suitable for adding the average value of the lower bus voltage and the AC value of the upper bus voltage as the average bus voltage instruction value; when the phase voltage is in the negative half cycle, the calculation unit is suitable for adding the average value of the upper bus voltage and the AC value of the lower bus voltage as the average bus voltage instruction value.

[0010] Preferably, the calculation unit is suitable for subtracting the average value of the upper bus voltage from the average value of the lower bus voltage to obtain a DC bus deviation value; based on the obtained upper bus voltage, lower bus voltage and DC bus deviation value, the calculation unit outputs different bus voltage average instruction values ​​according to the different periodic states of the phase voltage.

[0011] Preferably, when the phase voltage is in the positive half cycle, the calculation unit is suitable for subtracting the average value of the upper bus voltage and the lower bus voltage from the DC bus deviation value as the bus voltage average instruction value; when the phase voltage is in the negative half cycle, the calculation unit is suitable for adding the average value of the upper bus voltage and the lower bus voltage to the DC bus deviation value as the bus voltage average instruction value.

[0012] Preferably, the calculation unit is suitable for subtracting the upper bus voltage and the lower bus voltage from the upper bus voltage average value and the lower bus voltage average value respectively to obtain the upper bus voltage AC value and the lower bus voltage AC value; the calculation unit is suitable for subtracting the upper bus voltage average value and the lower bus voltage average value to obtain the DC bus deviation value; based on the obtained upper bus voltage, lower bus voltage, upper bus voltage AC value, lower bus voltage AC value and DC bus deviation value, the calculation unit outputs different bus voltage average command values ​​according to the different periodic states of the phase voltage.

[0013] Preferably, when the phase voltage is in the positive half cycle, the calculation unit is suitable for adding the average value of the upper bus voltage and the lower bus voltage to the AC value of the upper bus voltage and then subtracting the DC bus deviation value as the bus voltage average instruction value; when the phase voltage is in the negative half cycle, the calculation unit is suitable for adding the average value of the upper bus voltage and the lower bus voltage to the AC value of the lower bus voltage and the DC bus deviation value and then taking the bus voltage average instruction value.

[0014] Preferably, the upper bus voltage and the lower bus voltage are filtered to obtain the upper bus voltage average value V dc1_avg and the average value of the lower bus voltage V dc2_avg The enabling module is provided with a first threshold value V th1 , the second threshold value V th2 and hysteresis value ΔV; where V th2 >V th1 ; When |V dc1_avg -V dc2_avg |<(V th1 -ΔV), the enabling module controls the algorithm adjustment module to work, and the voltage balancing module does not work at this time; when (V th1 +ΔV)<|V dc1_avg -V dc2_avg |<(V th2 -ΔV), the enabling module controls the voltage balancing module to work, and the algorithm adjustment module does not work at this time; when |V dc1_avg -V dc2_avg |>(V th2 +ΔV), the enabling module controls the algorithm adjustment module and the voltage balancing module to work simultaneously; when |V dc1_avg -V dc2_avg |Located in [V th1 -ΔV, V th1 +ΔV] or [V th2 -ΔV, V th2 +ΔV], the control of the enabling module on the voltage balancing module and the algorithm adjustment module is the same as that at the previous moment.

[0015] Compared with the prior art, the present invention has the following advantages: Compared with traditional methods, the algorithm adjustment module is used in the process of obtaining the duty cycle through phase voltage, which can suppress the imbalance of bus voltage to a certain extent; and by enabling the module's hierarchical bus voltage balancing control method, it can minimize the impact of implementing bus balancing on the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 Schematic diagram of the architecture of a traditional grid-connected inverter system of this application.

[0017] Figure 2 For this application Figure 1 Schematic diagram of the specific process of DPWM zero-sequence generation in the shown architecture.

[0018] Figure 3 For this application Figure 1 Schematic diagram of the architecture with the addition of a voltage balancing module.

[0019] Figure 4 This is a schematic diagram of the overall architecture for bus voltage balancing control in this application.

[0020] Figure 5 This is a workflow diagram of Example 1 of the algorithm adjustment module in this application.

[0021] Figure 6 This application is approved Figure 5 Schematic diagram of waveform changes when the algorithm adjustment module performs bus equalization.

[0022] Figure 7 This is a workflow diagram of Example 2 of the algorithm adjustment module in this application.

[0023] Figure 8 This is a workflow diagram of Example 3 of the algorithm adjustment module in this application.

[0024] Figure 9 This is a workflow diagram of Example 4 of the algorithm adjustment module in this application.

[0025] Figure 10 This is a schematic diagram of the workflow of the enabling module in this application.

[0026] Figure 11 This is a timing diagram of setting a hysteresis zone for bus voltage balancing control in this application.

[0027] In the figure: voltage balancing module 101, algorithm adjustment module 102, enabling module 103. DETAILED DESCRIPTION

[0028] Below, the present application is further described in conjunction with specific implementation methods. It should be noted that, in the description of this specification, the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" and the like are intended to mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms should not be understood as necessarily referring to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0029] In the description of this application, it should be noted that for directional words, such as the terms "center", "horizontal", "longitudinal", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and so on, indicating the orientation and position relationship are based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and cannot be understood as limiting the specific scope of protection of this application.

[0030] It should be noted that the terms "first", "second", etc. in the description and claims of this application are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0031] In this application, unless otherwise expressly specified or limited, terms such as "mounted," "connected," "connect," and "fixed" should be understood in a broad sense. For example, they may refer to connection, detachable connection, or integration; mechanical connection or electrical connection; direct connection or indirect connection through an intermediate medium; and internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0032] In this application, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Moreover, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0033] The terms "comprises" and "having" and any variations thereof in the specification and claims of this application are intended to cover non-exclusive inclusions. For example, a process, method, system, product or apparatus that includes a series of steps or units is not necessarily limited to those steps or units expressly listed, but may include other steps or units not expressly listed or inherent to such process, method, product or apparatus.

[0034] In order to facilitate the understanding of the technical solution of this application, we can first Figure 1 It is understood that the DC / AC unit is the main factor affecting the bus voltage balance of the grid-connected system, so the specific working process of the control loop of the three-level DC / AC unit will be described below.

[0035] like Figure 1 As shown in the figure, the control loop of the DC / AC unit takes the bus voltage loop as the outer loop, and the bus voltage loop sets the bus voltage to a given value V dc_sum * And bus voltage value V dc_sum =V dc1 +V dc2 After making the difference, the PI controller generates the d-axis current reference I d * At the same time, by the three-phase current i a 、i b and i c After collecting and converting through abc / dq0, the current feedback I is obtained. d , I q and I0. The current is given by I d * and I q * Respectively with the current feedback I d and I q After the difference is made, it passes through the PI controller and then the dq0 / abc transformation to obtain the three-phase voltage reference v a 、v b and v cThen, divide by the average bus voltage (V dc1 +V dc2 ) / 2, and get the duty cycle signal d a d b and d c The duty cycle signal d a d b and d c Send it to the DPWM zero sequence generation unit to get the signal d z , and then added to the original duty cycle signal d a d b and d c The final duty cycle d is generated az d bz and d cz Finally, the signal S that drives each switch tube of the DC / AC unit is generated through modulation. dc1 Indicates the upper bus voltage, V dc2 Indicates the lower bus voltage.

[0036] like Figure 2 The figure shows the specific working process of the DPWM zero sequence generating unit. Specifically, according to the duty cycle signal d a d b and d c ; When a corresponds to the duty cycle signal d a > 0, the minimum duty cycle d corresponding to a is generated ha 1-d a , a corresponding to the next smallest duty cycle d al =d a ; When a corresponds to the duty cycle signal d a When ≤0, the minimum duty cycle d corresponding to a is generated ha -d a , a corresponding to the next smallest duty cycle d al =1+d a When b corresponds to the duty cycle signal d b > 0, the minimum duty cycle d corresponding to b is generated hb 1-d b , b corresponds to the next smallest duty cycle d bl =d b ; When b corresponds to the duty cycle signal d b When ≤0, the minimum duty cycle d corresponding to b is generated hb -d b , b corresponds to the next smallest duty cycle d bl =1+d b When c corresponds to the duty cycle signal d c >0, the minimum duty cycle d corresponding to c is generated hc1-d c , c corresponds to the next smallest duty cycle d cl =d c ; When c corresponds to the duty cycle signal d c When ≤0, the minimum duty cycle d corresponding to c is generated hc -d c , c corresponds to the next smallest duty cycle d cl =1+d c .

[0037] According to the minimum duty cycle d ha d hb and d hc , the three corresponding minimum duty cycles d can be calculated min_hk , d min_hk =min(d ha , d hb , d hc ); According to the obtained second smallest duty cycle d al d bl and d cl , we can calculate the three corresponding minimum duty cycles d min_kl , d min_ kl =min(d al , d bl , d cl ). When the calculated d min_hk <d min_k1 When the signal d z =d min_hk ; When the calculated d min_hk ≥d min_k1 When the signal d z =-d min_k1 .

[0038] like Figure 3 As shown, after adding the voltage balancing module 101, the three-phase voltage reference v a 、v b and v c The acquired duty cycle signal can be labeled as the first duty cycle signal d a ´、d b ´ and d c The voltage balancing module 101 mainly includes a comparator and a PI controller. The comparator is suitable for converting the bus voltage difference V dif =V dc1 -V dc2 The difference between the reference value 0 and the difference result can be sent to the PI controller. After limiting the output of the PI controller, the duty cycle common mode offset Δd can be obtained. This duty cycle common mode offset Δd is combined with the first duty cycle signal d a ´、d b´ and d c By superimposing the second duty cycle signal d a d b and d c .

[0039] One of the preferred embodiments of this application is as follows: Figure 4 As shown, a three-level bus voltage balancing control system is applied to the control loop of the above-mentioned grid-connected system, including a voltage balancing module 101, an algorithm adjustment module 102 and an enabling module 103. The voltage balancing module 101 can add a duty cycle common-mode offset to the first duty cycle signal output by the previous link, thereby obtaining a second duty cycle signal for suppressing bus voltage imbalance. The algorithm adjustment module 102 is located in the previous link of the voltage balancing module 101; the algorithm adjustment module 102 can output different bus voltage average command values ​​through non-zero sequence calculation according to the positive and negative cycle states of the phase voltage; by dividing the phase voltage by the corresponding bus voltage average command value, a first duty cycle signal for suppressing bus voltage imbalance can be obtained. The enabling module 103 can judge the degree of bus voltage imbalance and control the algorithm adjustment module 102 and / or the voltage balancing module 101 to work according to the judgment result.

[0040] It is understandable that the algorithm adjustment module 102 is weaker in suppressing bus voltage imbalance than the voltage balancing module 101. Since the bus voltage imbalance suppression of the voltage balancing module 101 requires the use of zero-sequence current to adjust the bus voltage, and the zero-sequence current will increase the loss of the system. Therefore, when the bus voltage imbalance is relatively weak, the algorithm adjustment module 102 can be used to suppress the bus voltage imbalance, so as to ensure that the system will not have additional losses; and when the bus voltage imbalance is relatively serious, the voltage balancing module 101 or the voltage balancing module 101 and the algorithm adjustment module 102 can be used to work at the same time, so as to achieve the maximum suppression of bus voltage imbalance. The enabling of the algorithm adjustment module 102 and the voltage balancing module 101 in different situations is achieved through the enabling module 103.

[0041] It should be noted that when the algorithm adjustment module 102 is not working, the first duty cycle d a d b and d c The acquisition is obtained in a traditional way, that is, through the three-phase voltage reference v a 、v b and v c Divide by the average bus voltage (V dc1 +V dc2 ) / 2 to obtain the required first duty cycle d a ´、d b ´ and d cWhen the algorithm adjustment module 102 is working, the algorithm adjustment module 102 can replace the traditional first duty cycle d a ´、d b ´ and d c 'Acquisition method; that is, the algorithm adjustment module 102 is based on the phase voltage v a 、v b and v c The cycle state is used to output different bus voltage average command values ​​V dc_a 、V dc_b and V dc_c Then the voltage reference of each phase can be divided by the corresponding average bus voltage command value to obtain the first duty cycle signal d that can suppress the bus voltage imbalance to a certain extent. a ´、d b ´ and d c ´. In order to facilitate the description of the following content, the phase voltage in the following content is expressed as v x The average bus voltage command value is expressed as V dc_x Represented by; where x={a, b, c}.

[0042] More generally, the algorithm adjustment module 102 in this embodiment can generate an average bus voltage command value V corresponding to each phase. dc_x , and the average bus voltage command value of each phase is V dc_x The specific value is different when the phase voltage cycle is different; that is, the average bus voltage command value V dc_x Adaptive changes can be made according to the bus voltage imbalance state, thereby suppressing the bus voltage imbalance.

[0043] Therefore, compared with the traditional method, the technical solution of the present application can suppress the imbalance of the bus voltage to a certain extent by adopting the algorithm adjustment module 102 in the process of obtaining the duty cycle through the phase voltage; and by enabling the hierarchical bus voltage balancing control method of the module 103, it can minimize the impact of the implementation of bus balancing on the system.

[0044] Since the specific structure and operation process of the voltage balancing module 101 are well known to those skilled in the art and have been described above, the specific structure and operation process of the algorithm adjustment module 102 will be described in detail below. There are many specific structures of the algorithm adjustment module 102 that can achieve the above functions. For ease of understanding, the following will be described in detail using four specific examples.

[0045] Example 1: Figure 5 As shown, the algorithm adjustment module 102 can receive the upper bus voltage V dc1 , lower bus voltage V dc2 And the phase voltage vx The algorithm adjustment module 102 includes a filtering unit and a calculation unit; the filtering unit can be used to adjust the bus voltage V dc1 and the lower bus voltage V dc2 Filter and get the average value of upper bus voltage V dc1_avg and the average value of the lower bus voltage V dc2_avg Based on the average upper bus voltage V dc1_avg and the average value of the lower bus voltage V dc2_avg , the calculation unit can be based on the phase voltage v x The cycle state is different to output different bus voltage average command values.

[0046] Specifically, such as Figure 5 As shown, when the phase voltage reference signal v x In the positive half cycle, that is, v x >0; the calculation unit can calculate the average value of the lower bus voltage V dc2_avg Directly used as the bus voltage average command value V dc_x , that is, V dc_x =V dc2_avg When the phase voltage reference signal v x In the negative half cycle, that is, v x ≤0; the calculation unit can calculate the average value of the upper bus voltage V dc1_avg Directly used as the bus voltage average command value V dc_x , that is, V dc_x =V dc1_avg .

[0047] It can be understood that the imbalance of bus voltage is the upper bus voltage V dc1 and the lower bus voltage V dc2 imbalance. Figure 6 As shown in (1), when the bus voltage is balanced, the phase current i x The output waveform of (x=a, b, c) is symmetrical up and down. dc2_avg Less than the average value of the upper bus voltage V dc1_avg When the algorithm adjustment module 102 divides the average bus voltage V by the positive half cycle of the phase voltage, dc2_avg , in the negative half cycle, the average bus voltage V dc1_avg , so the phase current i x The output waveform will show a positive deviation, that is, Figure 6 As shown in (2), a forward bias current will flow into the midpoint of the busbar, so that the lower busbar will be charged, thereby balancing the upper and lower busbar voltages.

[0048] Similarly, the current average bus voltage V dc2_avg Greater than the average value of the upper bus voltage Vdc1_avg When the algorithm adjustment module 102 divides the average bus voltage V by the positive half cycle of the phase voltage, dc2_avg , in the negative half cycle, the average bus voltage V dc1_avg , so the phase current i x The output waveform will show a negative offset, that is, Figure 6 As shown in (3), a negative bias current will flow out of the bus midpoint, so that the upper bus will be charged, and the upper and lower bus voltages will reach balance.

[0049] Example 2: For example Figure 7 As shown, this example adds a comparison unit to the calculation unit based on Example 1. The comparison unit can compare the bus voltage V dc1 and the average value of the upper bus voltage V dc1_avg Subtract and get the AC component of the upper bus voltage, that is, the AC value of the upper bus voltage V dc1_ac Similarly, the comparison unit can also compare the lower bus voltage V dc2 and the average value of the lower bus voltage V dc2_avg Subtract and get the AC component of the lower bus voltage, that is, the AC value of the lower bus voltage V dc2_ac Based on the average upper bus voltage V dc1_avg , average value of lower bus voltage V dc2_avg , Upper bus voltage AC value V dc1_ac And the lower bus voltage AC value V dc2_ac , the calculation unit can be based on the phase voltage v x The cycle state is different to output different bus voltage average command value V dc_x .

[0050] Specifically, such as Figure 7 As shown, when the phase voltage reference signal v x In the positive half cycle, that is, v x >0; the calculation unit can calculate the average value of the lower bus voltage V dc2_avg And the upper bus voltage AC value V dc1_ac Added as the bus voltage average command value V dc_x , that is, V dc_x =V dc2_avg +V dc1_ac When the phase voltage reference signal v x In the negative half cycle, that is, v x ≤0; the calculation unit can calculate the average value of the upper bus voltage V dc1_avg And the AC value of the lower bus voltage V dc2_ac Added as the bus voltage average command value V dc_x , that is, V dc_x =V dc1_avg +Vdc2_ac .

[0051] It can be understood that this example separates the DC component and AC component of the busbar; the DC component is crossed, that is, the phase voltage v x The average value of the bus voltage V is used in the positive half cycle dc2_avg , the negative half cycle uses the average value of the upper bus voltage V dc1_avg , to achieve the suppression of bus voltage imbalance; the AC components do not cross, that is, the phase voltage v x The positive half cycle uses the upper bus voltage AC value V dc1_ac , negative half cycle uses the lower bus voltage AC value V dc2_ac Since AC does not affect busbar offset, no cross processing is performed, which can ensure that the phase current i x Output waveform quality.

[0052] Example 3: If Figure 8 As shown, this example adds a comparison unit and a PI controller to the calculation unit based on Example 1. The comparison unit can calculate the average value of the upper bus voltage V output by the filter unit. dc1_avg and the average value of the lower bus voltage V dc2_avg After making a difference and passing through the PI controller and limiting, the DC bus deviation value ΔV can be obtained. dc Based on the obtained upper bus voltage V dc1 , lower bus voltage V dc2 And the DC bus deviation value ΔV dc , the calculation unit can be based on the phase voltage v x The cycle state is different to output different bus voltage average command value V dc_x .

[0053] Specifically, such as Figure 8 As shown, when the phase voltage reference signal v x In the positive half cycle, that is, v x >0; the calculation unit can be the upper bus voltage V dc1 and the lower bus voltage V dc2 The average value of the DC bus deviation value ΔV dc Subtract the average bus voltage command value V dc_x , that is, V dc_x =(V dc1 +V dc2 ) / 2-ΔV dc When the phase voltage reference signal v x In the negative half cycle, that is, v x ≤0; the calculation unit can be the upper bus voltage V dc1 and the lower bus voltage V dc2 The average value of the DC bus deviation value ΔV dcAdded as the bus voltage average command value V dc_x , that is, V dc_x =(V dc1 +V dc2 ) / 2+ΔV dc .

[0054] It is understandable that, compared with Example 1 and Example 2, this example adopts closed-loop control to better achieve bus voltage control. Specifically, the current average bus voltage V dc2_avg Less than the average value of the upper bus voltage V dc1_avg When the DC bus deviation value ΔV is dc According to the working process of the algorithm adjustment module 102, the phase voltage v x The positive half cycle divided by the value is (V dc1 +V dc2 ) / 2-ΔV dc , the value will be too small; in the phase voltage v x The negative half cycle is divided by the value (V dc1 +V dc2 ) / 2+ΔV dc , the value will be too large. So the phase current i x The output waveform will show a positive deviation, which will generate a forward bias current flowing into the midpoint of the busbar, so that the lower busbar will be charged and the upper and lower busbar voltages will reach a balance.

[0055] Similarly, the current average bus voltage V dc2_avg Greater than the average value of the upper bus voltage V dc1_avg When the DC bus deviation value ΔV is dc According to the working process of the algorithm adjustment module 102, the phase voltage v x The value divided by the positive half cycle is (V dc1 +V dc2 ) / 2-ΔV dc , the value will be too large; in the phase voltage v x The negative half cycle is divided by the value (V dc1 +V dc2 ) / 2+ΔV dc , the value will be too small. So the phase current i x The output waveform will show a negative offset, which will generate a bias current flowing out of the midpoint of the bus, so that the upper bus will be charged and the upper and lower bus voltages will reach a balance.

[0056] Example 4: This example is based on the combination of Example 2 and Example 3. Figure 9 As shown, this example adds a comparison unit and a PI controller to the calculation unit based on Example 1. The comparison unit can compare the bus voltage Vdc1 and the average value of the upper bus voltage V dc1_avg Subtract and get the upper bus voltage AC value V dc1_ac Similarly, the comparison unit can also compare the lower bus voltage V dc2 and the average value of the lower bus voltage V dc2_avg Subtract and get the lower bus voltage AC value V dc2_ac At the same time, the comparison unit can convert the average value of the upper bus voltage V output by the filter unit into dc1_avg and the average value of the lower bus voltage V dc2_avg After making a difference and passing through the PI controller and limiting, the DC bus deviation value ΔV can be obtained. dc Based on the obtained upper bus voltage V dc1 , lower bus voltage V dc2 , Upper bus voltage AC value V dc1_ac , lower bus voltage AC value V dc2_ac And the DC bus deviation value ΔV dc , the calculation unit can be based on the phase voltage v x The cycle state is different to output different bus voltage average command value V dc_x .

[0057] Specifically, such as Figure 9 As shown, when the phase voltage reference signal v x In the positive half cycle, that is, v x >0; the calculation unit can be the upper bus voltage V dc1 and the lower bus voltage V dc2 The average value of the upper bus voltage AC value V dc1_ac Add and subtract the DC bus deviation value ΔV dc As the bus voltage average command value V dc_x , that is, V dc_x =(V dc1 +V dc2 ) / 2-ΔV dc +V dc1_ac When the phase voltage reference signal v x In the negative half cycle, that is, v x ≤0; the calculation unit can be the upper bus voltage V dc1 and the lower bus voltage V dc2 The average value of the lower bus voltage AC value V dc2_ac And the DC bus deviation value ΔV dc The sum is used as the bus voltage average command value V dc_x , that is, V dc_x =(V dc1 +V dc2 ) / 2+ΔV dc +V dc2_ac .

[0058] It is understandable that this example can combine the advantages of Example 2 and Example 3 to improve the phase current i while achieving closed-loop control. x The quality of the output waveform.

[0059] In this embodiment, it can be seen from the above content that the enabling module 103 can implement hierarchical control according to the degree of bus voltage imbalance. Figure 10 As shown, the enable signal of the enable module 103 to the algorithm adjustment module 102 can be set to S 102 The enable signal of the enable module 103 to the voltage balancing module 101 is S 101 When the enable signal is high, the corresponding module will work, otherwise when the enable signal is low, the corresponding module will stop the process. When only the algorithm adjustment module 102 is working, the working mode of the enable module 103 can be marked as M3, and the corresponding enable signal is: S 101 =0,S 102 =1; when only the voltage balancing module 101 is working, the working mode of the enabling module 103 can be marked as M2, and the corresponding enabling signal is: S 101 =1,S 102 =0; when the voltage balancing module 101 and the algorithm adjustment module 102 are both working, the working mode of the enabling module 103 can be marked as M1, and the corresponding enabling signal is: S 101 =1,S 102 =1.

[0060] In order to ensure that the enabling module 103 can accurately execute the modes M1 to M3, the bus voltage imbalance degree can be divided. Specifically, two threshold values ​​can be set, namely, the first threshold value V th1 and the second threshold value V th2 ; Among them, V th2 >V th1 Then the upper bus voltage and the lower bus voltage can be filtered to obtain the upper bus voltage average value V dc1_avg and the average value of the lower bus voltage V dc2_avg The average upper bus voltage V dc1_avg and the average value of the lower bus voltage V dc2_avg The difference between the two values ​​is used to judge the degree of bus voltage imbalance.

[0061] When |V dc1_avg -V dc2_avg |<V th1 When , it indicates that the bus voltage imbalance is weak, at this time the enabling module 103 can execute mode M3, and then can send a high level enabling signal S to the algorithm adjustment module 102. 102, so that the algorithm adjustment module 102 works to suppress bus voltage imbalance.

[0062] When V th1 ≤|V dc1_avg -V dc2_avg |≤V th2 When the bus voltage imbalance is high, it indicates that the bus voltage imbalance is serious. At this time, the enabling module 103 can execute mode M2 ​​and then send a high-level enabling signal S to the voltage balancing module 101. 101 , so that the voltage balancing module 101 works to suppress bus voltage imbalance.

[0063] When |V dc1_avg -V dc2_avg |>V th2 When the bus voltage imbalance is very serious, the enabling module 103 can execute mode M1 and then send a high-level enabling signal S to the voltage balancing module 101 and the algorithm adjustment module 102 respectively. 101 and S 102 , so that the voltage balancing module 101 and the algorithm adjustment module 102 work simultaneously to suppress bus voltage imbalance.

[0064] It should be noted that when the bus voltage deviation |V dc1_avg -V dc2_avg | Located at the first threshold V th1 Or the second threshold V th2 When the voltage is close to , the enabling module 103 will frequently switch modes, which may easily damage the algorithm adjustment module 102 and the voltage balancing module 101. In order to avoid frequent mode switching of the enabling module 103, a hysteresis setting can be performed on the enabling module 103.

[0065] Specifically, such as Figure 11 As shown, a hysteresis value ΔV can be set in the enabling module 103; that is, [V th1 -ΔV, V th1 +ΔV] and [V th2 -ΔV, V th2 +ΔV] can be defined as the hysteresis region. dc1_avg -V dc2_avg |<(V th1 -ΔV), the enabling module 103 executes mode M3 to control the algorithm adjustment module 102 to work, and the voltage balancing module 101 does not work. th1 +ΔV)<|V dc1_avg -V dc2_avg |<(V th2 -ΔV), the enabling module 103 executes mode M2 ​​to control the voltage balancing module 101 to work, and the algorithm adjustment module 102 does not work at this time.dc1_avg -V dc2_avg |>(V th2 +ΔV), the enabling module 103 executes the mode M1 to control the algorithm adjustment module 102 and the voltage balancing module 101 to work simultaneously. dc1_avg -V dc2_avg |Located in [V th1 -ΔV, V th1 +ΔV] or [V th2 -ΔV, V th2 +ΔV], the control of the enabling module 103 on the voltage balancing module 101 and the algorithm adjustment module 102 depends on the previous moment.

[0066] It is understandable that if Figure 11 The direction indicated by the thick solid arrow is the mode execution direction of the enabling module 103. dc1_avg -V dc2_avg |Located in the hysteresis region [V th1 -ΔV, V th1 +ΔV], if the enabling module 103 executed mode M3 at the previous moment, then the enabling module 103 still executes mode M3 at the current moment; if the enabling module 103 executed mode M2 ​​at the previous moment, then the enabling module 103 still executes mode M2 ​​at the current moment. dc1_avg -V dc2_avg |Located in the hysteresis region [V th2 -ΔV, V th2 +ΔV], if the enabling module 103 executed the mode M2 ​​at the previous moment, the enabling module 103 still executes the mode M2 ​​at the current moment; if the enabling module 103 executed the mode M1 at the previous moment, the enabling module 103 still executes the mode M1 at the current moment.

[0067] The above describes the basic principles, main features, and advantages of the present application. Those skilled in the art should understand that the present application is not limited to the above-described embodiments. The above-described embodiments and the specification merely illustrate the principles of the present application. Various changes and improvements may be made to the present application without departing from the spirit and scope of the present application. These changes and improvements fall within the scope of the present application for which protection is sought. The scope of protection claimed by the present application is defined by the appended claims and their equivalents.

Claims

1. A three-level bus voltage balancing control system, applied to the control loop of a grid-connected system, characterized in that: include: Voltage balancing module; The voltage balancing module is adapted to add a duty cycle common mode offset to the first duty cycle signal outputted from the previous link, thereby obtaining a second duty cycle signal for suppressing bus voltage imbalance; Algorithm adjustment module; The algorithm adjustment module is located in the previous link of the pressure equalization module; The algorithm adjustment module is adapted to output different bus voltage average command values ​​through non-zero sequence calculation according to the positive and negative cycle states of the phase voltage; and to obtain the first duty cycle signal for suppressing bus voltage imbalance by dividing the phase voltage by the corresponding bus voltage average command value; as well as Enable module; The enabling module is adapted to judge the degree of bus voltage imbalance and control the algorithm adjustment module and / or the voltage balancing module to operate according to the judgment result.

2. The three-level bus voltage balancing control system according to claim 1, characterized in that: The algorithm adjustment module is adapted to receive the upper bus voltage, the lower bus voltage and the phase voltage; the algorithm adjustment module comprises: Filtering unit; the filtering unit filters the upper bus voltage and the lower bus voltage to obtain an average value of the upper bus voltage and an average value of the lower bus voltage; and calculation unit; based on the obtained upper bus voltage average value and the lower bus voltage average value, the calculation unit is adapted to output different bus voltage average command values ​​according to different cycle states of the phase voltage.

3. The three-level bus voltage balancing control system according to claim 2, characterized in that: When the phase voltage is in a positive half cycle, the calculation unit is adapted to directly use the average value of the lower bus voltage as the average bus voltage instruction value; When the phase voltage is in a negative half cycle, the calculation unit is adapted to directly use the upper bus voltage average value as the bus voltage average command value.

4. The three-level bus voltage balancing control system according to claim 2, characterized in that: The calculation unit is adapted to subtract the upper bus voltage and the lower bus voltage from the upper bus voltage average value and the lower bus voltage average value, respectively, to obtain the upper bus voltage AC value and the lower bus voltage AC value; Based on the obtained upper bus voltage average value, lower bus voltage average value, upper bus voltage AC value and lower bus voltage AC value, the calculation unit outputs different bus voltage average command values ​​according to different cycle states of the phase voltages.

5. The three-level bus voltage balancing control system according to claim 4, characterized in that: When the phase voltage is in a positive half cycle, the calculation unit is adapted to add the lower bus voltage average value and the upper bus voltage AC value as the bus voltage average command value; When the phase voltage is in a negative half cycle, the calculation unit is adapted to add the upper bus voltage average value and the lower bus voltage AC value as the bus voltage average command value.

6. The three-level bus voltage balancing control system according to claim 2, characterized in that: The calculation unit is adapted to obtain a DC bus deviation value by subtracting an average value of the upper bus voltage from an average value of the lower bus voltage; Based on the obtained upper bus voltage, lower bus voltage and DC bus deviation value, the calculation unit outputs different bus voltage average command values ​​according to different periodic states of the phase voltages.

7. The three-level bus voltage balancing control system according to claim 6, characterized in that: When the phase voltage is in a positive half cycle, the calculation unit is adapted to subtract the average value of the upper bus voltage and the lower bus voltage from the DC bus deviation value to obtain the average bus voltage command value; When the phase voltage is in a negative half cycle, the calculation unit is adapted to add an average value of the upper bus voltage and the lower bus voltage to the DC bus deviation value as the bus voltage average command value.

8. The three-level bus voltage balancing control system according to claim 2, characterized in that: The calculation unit is adapted to subtract the upper bus voltage and the lower bus voltage from the upper bus voltage average value and the lower bus voltage average value, respectively, to obtain the upper bus voltage AC value and the lower bus voltage AC value; The calculation unit is adapted to obtain a DC bus deviation value by subtracting an average value of the upper bus voltage from an average value of the lower bus voltage; Based on the obtained upper bus voltage, lower bus voltage, upper bus voltage AC value, lower bus voltage AC value and DC bus deviation value, the calculation unit outputs different bus voltage average command values ​​according to different periodic states of the phase voltage.

9. The three-level bus voltage balancing control system according to claim 8, characterized in that: When the phase voltage is in a positive half cycle, the calculation unit is adapted to add the average value of the upper bus voltage and the lower bus voltage to the upper bus voltage AC value and then subtract the DC bus deviation value as the bus voltage average command value; When the phase voltage is in a negative half cycle, the calculation unit is adapted to add the average value of the upper bus voltage and the lower bus voltage to the AC value of the lower bus voltage and the DC bus deviation value as the bus voltage average command value.

10. The three-level bus voltage balancing control system according to any one of claims 1 to 9, characterized in that: The upper bus voltage and the lower bus voltage are filtered to obtain the upper bus voltage average value V dc1_avg and the average value of the lower bus voltage V dc2_avg ; The enabling module is provided with a first threshold value V th1 , the second threshold value V th2 and hysteresis value ΔV; Among them, V th2 >V th1 ; When |V dc1_avg -V dc2_avg |<(V th1 -ΔV), the enabling module controls the algorithm adjustment module to work, and the voltage balancing module does not work at this time; When (V th1 +ΔV)<|V dc1_avg -V dc2_avg |<(V th2 -ΔV), the enabling module controls the voltage balancing module to work, and the algorithm adjustment module does not work at this time; When |V dc1_avg -V dc2_avg |>(V th2 +ΔV), the enabling module controls the algorithm adjustment module and the voltage balancing module to work simultaneously; When |V dc1_avg -V dc2_avg |Located in [V th1 -ΔV, V th1 +ΔV] or [V th2 -ΔV, V th2 +ΔV], the control of the enabling module on the voltage balancing module and the algorithm adjustment module is the same as that at the previous moment.

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