Chip-level hardware timestamp generation method and system based on PTP protocol

Abstract

The present application relates to the field of synchronization technology in data communications, and provides a chip-level hardware timestamp generation method and system based on the PTP protocol. The method includes the following steps: Step 1: receiving a synchronization message and a delay request message from a master clock, evaluating the physical layer signal, and recording a first hardware timestamp; Step 2: responding to the received delay request message, generating and sending a delay response message, obtaining bidirectional transmission delay data by exchanging the delay request and delay response messages, and calculating the clock deviation by combining the first hardware timestamp and the bidirectional transmission delay data; Step 3: adjusting the local clock frequency according to the clock deviation; Step 4: after synchronization is completed, associating the second hardware timestamp with the corresponding data message, and storing the associated data in a buffer inside the chip; Step 5: generating standardized timestamp information, and outputting the standardized timestamp information through the chip interface. This achieves high-precision time synchronization and timestamp generation.

Description

Technical Field

[0001] The present application relates to the field of synchronization technology in data communications, and in particular to a chip-level hardware timestamp generation method and system based on the PTP protocol. Background Art

[0002] With the rapid development of network technology, accurate time synchronization has become increasingly important in many fields, especially in high-precision applications such as industrial control, communications, and financial transactions. To meet the time synchronization needs of these fields, PTP (Precision Time Protocol) has become an important time synchronization standard.

[0003] Existing timestamp generation solutions based on the PTP protocol mostly rely on software or board-level hardware, and have obvious limitations: in terms of accuracy, affected by software protocol stack processing delays, thread scheduling, etc., the timestamp accuracy is mostly in the microsecond level, which is difficult to meet the high-precision requirements of the nanosecond level and below; in terms of efficiency, the association and transmission of timestamps and messages rely on CPU intervention, and are processed through software interrupts or polling, which has high resource overhead and is not suitable for high-throughput scenarios; in terms of synchronization stability, a fixed compensation algorithm is used, which does not consider the clock drift caused by environmental factors such as chip temperature and voltage, and the accumulated error is significant after long-term synchronization; the hardware integration is low, and only simple timestamp recording is implemented at the physical layer or MAC layer. The core logic such as the PTP protocol stack, timestamp processing, and clock adjustment are not integrated into the chip hardware, and require software collaboration, and cannot form an end-to-end hardware closed loop.

[0004] Therefore, the present application provides a chip-level hardware timestamp generation method and system based on the PTP protocol. Summary of the Invention

[0005] This application provides a chip-level hardware-based timestamp generation method and system based on the PTP protocol, which is used to integrate the core logic of the PTP protocol, such as message parsing, timestamp capture, and clock deviation calculation, into the chip hardware. This is implemented through a dedicated hardware state machine, replacing the traditional software protocol stack and eliminating software processing delays. A layered hardware timestamp capture mechanism: at the physical layer, the arrival time of synchronization messages / delay request messages is captured through hardware logic, and at the MAC layer, the transmission and reception time of data messages is recorded through hardware triggering. The associated storage of timestamps and message sequence numbers / IDs is implemented through the chip's internal dual-port RAM and hardware DMA, without the need for CPU intervention. Based on the clock deviation calculated by hardware, the local clock frequency is adjusted in real time through the chip's internal DCO, and dynamic optimization of the feedback correction margin is combined to achieve nanosecond-level synchronization of the local clock and the master clock, solving the cumulative error problem of traditional fixed compensation algorithms. The chip has a built-in dedicated hardware timestamp processing unit to correct the accumulated timestamp error and eliminate outliers in real time, ultimately generating a "second + nanosecond" format timestamp that complies with the PTP protocol standard, replacing the inefficient processing of software algorithms.

[0006] In a first aspect, the present application provides a chip-level hardware timestamp generation method based on the PTP protocol, comprising:

[0007] Step 1: Receive synchronization messages and delay request messages from the master clock through the chip's built-in PTP protocol stack, evaluate the physical layer signal at the instant the synchronization message and delay request message arrive at the physical layer interface's physical layer signal transition edge, and record the first hardware timestamp based on the evaluation result;

[0008] Step 2: In response to the received Delay Request message, generate and send a Delay Response message and record the sending timestamp at the MAC layer. By exchanging the Delay Request and Delay Response messages, obtain the bidirectional transmission delay data, and calculate the clock offset by combining the first hardware timestamp and the bidirectional transmission delay data.

[0009] Step 3: Based on the clock deviation, the local clock frequency is adjusted through the digitally controlled oscillator inside the chip to synchronize the local clock with the master clock;

[0010] Step 4: After synchronization is completed, when the chip receives a data message that needs to be timestamped, it records the second hardware timestamp when the message passes through the MAC layer, associates the second hardware timestamp with the corresponding data message, and stores the associated data in the buffer inside the chip;

[0011] Step 5: The chip's built-in hardware timestamp processing unit performs format conversion and precision calibration on the timestamp data in the buffer to generate standardized timestamp information, which is then output through the chip interface.

[0012] Secondly, this application also provides a chip-level hardware timestamp generation system based on the PTP protocol, including:

[0013] Physical layer timestamp capture module: Receives synchronization messages and delay request messages from the master clock through the chip's built-in PTP protocol stack, and records the first hardware timestamp when the synchronization messages and delay request messages arrive at the physical layer;

[0014] Two-way delay calculation module: In response to the received delay request message, it generates and sends a delay response message and records the sending timestamp at the MAC layer. It obtains two-way transmission delay data by exchanging delay request and delay response messages, and calculates the clock deviation by combining the first hardware timestamp and the two-way transmission delay data.

[0015] Clock synchronization control module: According to the clock deviation, the local clock frequency is adjusted through the digital controlled oscillator inside the chip to synchronize the local clock with the master clock;

[0016] MAC layer timestamp module: After synchronization is completed, when the chip receives a data message that needs to be timestamped, it records the second hardware timestamp when the message passes through the MAC layer, associates the second hardware timestamp with the corresponding data message, and stores the associated data in the buffer inside the chip;

[0017] Timestamp standardization output module: Through the chip's built-in hardware timestamp processing unit, the timestamp data in the buffer is format converted and the accuracy is calibrated to generate standardized timestamp information, which is then output through the chip interface.

[0018] Compared with the prior art, the present invention has the following advantages:

[0019] The chip-level hardware-based timestamp generation method based on the PTP protocol enables high-precision time synchronization and timestamp generation. Core logic for PTP protocol message parsing, timestamp capture, and clock deviation calculation are integrated into the chip hardware and implemented through a dedicated hardware state machine, replacing the traditional software protocol stack and eliminating software processing delays. A layered hardware timestamp capture mechanism uses hardware logic at the physical layer to capture the arrival time of synchronization messages / delay request messages, and hardware triggers at the MAC layer to record the transmission and reception time of data messages. Timestamps are associated with message sequence numbers / IDs and stored using internal dual-port RAM and hardware DMA, eliminating CPU intervention. Based on the hardware-calculated clock deviation, the chip's internal DCO adjusts the local clock frequency in real time. Combined with dynamic optimization of feedback correction margin, this achieves nanosecond-level synchronization between the local clock and the master clock, addressing the cumulative error problem of traditional fixed compensation algorithms. A dedicated hardware timestamp processing unit is built into the chip to correct cumulative timestamp errors and eliminate outliers in real time, ultimately generating timestamps in a "seconds + nanoseconds" format that complies with the PTP protocol standard, replacing the inefficient processing of software algorithms. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0021] Figure 1 1 is a flow chart of a chip-level hardware timestamp generation method based on the PTP protocol provided in an embodiment of the present application;

[0022] Figure 2 Schematic diagram of the structure of the chip-level hardware timestamp generation system based on the PTP protocol provided in an embodiment of the present application. DETAILED DESCRIPTION

[0023] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0024] Example 1

[0025] The embodiment of the present application provides a chip-level hardware timestamp generation method based on the PTP protocol, such as Figure 1 Shown, including:

[0026] Step 1: Receive synchronization messages and delay request messages from the master clock through the chip's built-in PTP protocol stack, and record the first hardware timestamp at the physical layer signal transition edge when the synchronization message and delay request message arrive at the physical layer interface;

[0027] Step 2: In response to the received Delay Request message, generate and send a Delay Response message and record the sending timestamp at the MAC layer. By exchanging the Delay Request and Delay Response messages, obtain the bidirectional transmission delay data, and calculate the clock offset by combining the first hardware timestamp and the bidirectional transmission delay data.

[0028] Step 3: Based on the clock deviation, the local clock frequency is adjusted through the digitally controlled oscillator inside the chip to synchronize the local clock with the master clock;

[0029] Step 4: After synchronization is completed, when the chip receives a data message that needs to be timestamped, it records the second hardware timestamp when the message passes through the MAC layer, associates the second hardware timestamp with the corresponding data message, and stores the associated data in the buffer inside the chip;

[0030] Step 5: The chip's built-in hardware timestamp processing unit performs format conversion and precision calibration on the timestamp data in the buffer to generate standardized timestamp information, which is then output through the chip interface.

[0031] In this embodiment, the chip's built-in PTP protocol stack is a precision time protocol (PTP) protocol processing unit integrated into the chip, a dedicated hardware logic circuit, and a hardware state machine, a dedicated register group, and a high-speed interconnection bus to implement full hardware processing of the core functions of the PTP protocol (IEEE 1588-2019), replacing the traditional implementation method that relies on a CPU or a software protocol stack. Its hardware working logic includes: 1. A hardware protocol parsing and message identification module, which is composed of a dedicated hardware logic circuit and implements real-time parsing of PTP messages in the following ways: Message type identification: The hardware logic pre-solidifies the PTP protocol field features (such as EtherType = 0x88F7 identifies the PTP message, and the MessageType field distinguishes event messages such as Sync messages (0x0) and Delay_Req messages (0x1)). In the message transmission path from the physical layer to the MAC layer, a parallel comparison circuit is used to detect messages that meet the features in real time, and the identification delay is ≤1 clock cycle (when the clock frequency is ≥1GHz, the delay is ≤1ns); Serial number binding: For the identified PTP 1. For event messages, the hardware logic automatically extracts its sequence number (SequenceID) and binds the sequence number to the first hardware timestamp captured by the physical layer through a dedicated bus inside the chip and stores it in the dual-port RAM. The binding process is triggered by the hardware state machine and does not require software interrupts or CPU intervention. 2. Hardware-based timestamp and message association logic. This logic uses hardware circuits to achieve precise association between timestamps and PTP messages. Specifically, it includes: Event-triggered timestamp latching: When the hardware parsing unit detects the start frame delimiter (SFD) of a Sync message or Delay_Req message, it immediately triggers the physical layer high-precision timer (accuracy ≥1ns) to latch the current count value as the first hardware timestamp. The time difference between the latching action and the moment the message is received by the physical layer is ≤10ps. 3. Storage mechanism without CPU intervention: The associated data of the timestamp and message sequence number is directly written into a dedicated buffer inside the chip (independent of the general memory) through hardware. The buffer read and write control is managed by the hardware DMA controller. When the data volume reaches the preset threshold (configurable to 16 / 32 records), the DMA controller Automatically transfers data in batches to designated memory addresses, without consuming CPU resources. 4. Hardware-based clock deviation calculation: PTP protocol clock deviation calculation is implemented through dedicated hardware arithmetic logic (ALU), replacing traditional software algorithms. 5. Hardware-based closed-loop interaction with internal chip modules: This protocol stack forms a closed loop with other hardware modules via the chip's internal high-speed interconnect bus (such as AXI-Stream). The calculated clock deviation is directly sent to the DCO dynamic adjustment module via hardware signals, triggering local clock frequency correction. The raw timestamp data required by the timestamp processing unit is read from a dedicated buffer via a hardware interface, without the need for forwarding through the software protocol stack.Interactions between all modules are controlled by hardware handshake signals, with a response time of ≤5ns, ensuring an end-to-end hardware-closed loop for the entire PTP synchronization process with no software intervention. For example, a dedicated hardware state machine parses Sync / Delay_Req messages in real time (with a parsing delay of ≤1ns), eliminating the need for software intervention. This ensures that timestamp capture deviations for multiple radio frequency units within the base station are ≤50ns, meeting the stringent 3GPP requirements for 5G air interface synchronization. Furthermore, the system supports a throughput of 100,000 messages per second, making it suitable for high-load scenarios.

[0032] In this embodiment, the dedicated hardware logic circuit is the core execution unit of the chip-level timestamp generation system, including: (1) PTP message parsing hardware logic, integrated in the physical layer and MAC layer, and identifies the PTP protocol message in real time through the dedicated hardware circuit: the physical layer hardware logic detects the characteristic fields of the PTP message (such as EtherType=0x88F7, MessageType field distinguishes Sync / Delay_Req, etc.) through the parallel comparison circuit, and completes the identification at the moment the message arrives at the physical layer interface, with an identification delay of ≤1 clock cycle (based on a 1GHz clock, a delay of ≤1ns); the MAC layer hardware logic parses the sequence number (SequenceID) and PTP timestamp request flag of the message header through a dedicated state machine, providing hardware support for the association between the timestamp and the message, and the parsing process does not require software configuration intervention; (2) timestamp capture hardware logic, corresponding to the timestamp generation of the physical layer and MAC layer respectively: the physical layer dedicated trigger circuit: at the PTP synchronization message / When the delay request message arrives at the signal transition edge of the physical layer (such as the start of the preamble), the high-precision timer is immediately triggered to latch the count value (the first hardware timestamp). The latching action is directly controlled by the hardware level signal, and the time difference with the arrival time of the message is ≤10ps; MAC layer dedicated trigger circuit: When the data message passes through the MAC layer, for the message that meets the preset conditions (such as containing the PTP request flag, a specific MAC address), the hardware logic triggers the timer to record the second hardware timestamp. The trigger logic is hard-bound to the MAC layer frame processing process (such as after FCS check) to ensure the synchronization of the timestamp and the message processing time; (3) Timestamp processing hardware logic, integrated into the timestamp processing unit built into the chip, realizes the precise optimization of the timestamp through dedicated hardware circuits: Drift compensation hardware logic: realizes the least squares fitting through dedicated arithmetic units (such as multipliers and adders), calculates the clock drift slope in real time and generates the compensation coefficient, and the fitting process does not require software iterative calculation, and the response time is ≤10 Clock cycles; Filtering hardware logic: Using a sliding window median filter circuit, cache timestamp samples through a hardware register group, and eliminate abnormal values ​​through comparators and selectors. The filtering delay is ≤5ns, ensuring the stability of the output timestamp; (4) Data interaction hardware logic, to achieve efficient transmission and association of timestamp data, including: Dual-port RAM control logic: Dedicated hardware circuit manages the storage of "timestamp-message ID / serial number" associated data, supports parallel reading and writing, and avoids bus contention; Hardware DMA controller: Controls the batch transmission of timestamp data from the chip's internal buffer to the memory through a dedicated state machine. Transmission triggering, address mapping, and verification (such as CRC) are all completed by hardware without CPU intervention. The transmission efficiency is improved by ≥10 times compared with the software method.

[0033] In this embodiment, the synchronization message and delay request message from the master clock are Sync messages (for one-way time synchronization) sent by the master clock node (GrandmasterClock) and Delay_Req messages (for two-way delay measurement) triggered by the slave clock node, both of which comply with the message format and timing requirements defined by the IEEE1588 protocol; Example explanation: Sync message: broadcast periodically by the master clock, containing the estimated value of the master clock's transmission time (if the two-step mode is adopted, the subsequent Follow_Up message carries an accurate timestamp); Delay_Req message: initiated by the slave clock, triggering the master clock to reply with a Delay_Resp message, which is used to calculate the transmission path delay.

[0034] In this embodiment, the physical layer is the chip's physical interface circuitry at the lowest level of the OSI model, including Ethernet PHY, SerDes, or other wired / wireless communication modules. It is responsible for converting electrical signals into digital bit streams and providing hardware trigger signals for message arrival. Example explanation: Trigger point: When the PHY layer detects a message start symbol (such as the preamble in an Ethernet frame), a hardware interrupt records a timestamp. Advantage: Compared to software processing (MAC layer and above), PHY layer timestamps avoid protocol stack processing delays and achieve nanosecond accuracy.

[0035] In this embodiment, the first hardware timestamp is a high-precision time stamp that captures the arrival times of PTP protocol synchronization messages (Sync) and delay request messages (Delay_Req) ​​in real time at the physical layer through hardware logic. Its generation and association process is completely implemented by chip hardware. Specifically, it features the following: Trigger Timing: When the physical layer hardware detects the physical layer signal of a PTP synchronization message or delay request message (such as the starting transition edge of the Ethernet frame preamble), it immediately activates the chip's internal high-precision timer (the timing reference is the chip's global synchronous clock, with an accuracy of ≥1ns and a resolution of 10ps) through a hardware trigger signal (the same source as the physical layer receiving circuit). The timer then latches the current count value as the first hardware timestamp. Zero Software Intervention: The triggering and latching process is performed purely by hardware circuitry, without relying on CPU interrupts, software protocol stack scheduling, or operating system intervention. This ensures that the deviation between the timestamp capture moment and the actual physical layer arrival time of the message is ≤10ps, solving the accuracy loss caused by processing delays in traditional software capture.

[0036] In this embodiment, the association between the first hardware timestamp and the corresponding PTP message is implemented through internal chip hardware logic. Specific features include: Message feature identification: Physical layer hardware parses the message header fields in parallel, identifying the PTP message type (Sync / Delay_Req) ​​and unique sequence number (SequenceID) through hardware matching circuitry, with an identification delay of ≤1 clock cycle (≤1ns based on a 1GHz clock); Hardware binding storage: The identified message sequence number and the latched first hardware timestamp are written directly to the chip's internal dual-port RAM (a dedicated storage unit independent of general-purpose memory) via hardware, forming a "timestamp-sequence number" association record. The dual-port RAM is controlled by a hardware state machine, supporting parallel writes and reads to avoid delays caused by bus contention.

[0037] In this embodiment, the read notification and data transmission of the first hardware timestamp are driven by the chip hardware mechanism. Specifically, the following features are: Hardware interrupt triggering: When the number of "timestamp-sequence number" association records in the dual-port RAM reaches a preset threshold (settable to 8 or 16 records via the chip configuration register), the hardware automatically triggers a dedicated interrupt signal (independent of the general interrupt line) to notify the chip's built-in hardware PTP protocol stack to read the data, with an interrupt response latency of ≤5ns. Direct hardware access: The hardware PTP protocol stack directly reads the association records in the dual-port RAM via the chip's internal high-speed bus (such as AXI-Lite), without transiting through CPU memory or software buffers. This ensures an end-to-end latency of ≤50ns from timestamp data capture to protocol stack processing.

[0038] In this embodiment, the generation of the second hardware timestamp is triggered by dedicated hardware logic in the chip's MAC layer. Specifically, the following features are captured: When a data packet passes the MAC layer, the MAC layer hardware logic detects packet arrival or transmission events in real time (e.g., after passing the Frame Check Sequence (FCS) verification and before the packet enters the transmit queue). For packets that meet preset timestamp marking conditions, the chip's internal high-precision timer (which shares a globally synchronized clock source with the first hardware timestamp, with an accuracy of ≥1ns) is immediately triggered to latch the current count value, which serves as the second hardware timestamp. The time difference between the capture action and the time the packet is processed at the MAC layer is ≤50ps. The triggering logic is implemented purely in hardware, independent of software configuration or CPU scheduling. Preset timestamp marking conditions are hardware-recognized: These preset timestamp marking conditions include: packets containing the PTP timestamp request flag in the protocol field; packets with a user-configured specific source MAC address; monitoring messages generated by internal chip modules that require high-precision timestamps; critical control messages requiring time synchronization by network management protocols; and priority messages with a Time-Sensitive Network (TSN) flag. These conditions are identified in real time by the MAC layer hardware logic through parallel comparison circuits (such as comparing the flag bit in the message header, MAC address field, and priority tag), with an identification delay of ≤ 2 clock cycles (based on a 1GHz clock, delay ≤ 2ns).

[0039] In this embodiment, the association between the second hardware timestamp and the corresponding data message is implemented through an internal chip hardware mechanism. Specific features include: Message ID extraction and binding: The MAC layer hardware logic extracts a unique identifier (such as a message sequence number, flow ID, or hash value, defined as the "message ID") from the data message and directly binds it to the latched second hardware timestamp through hardware, forming a "timestamp-message ID" association record. The binding process is controlled by a hardware state machine, requiring no software intervention, with a binding latency of ≤10ns. Dedicated buffer storage: The association record is written by hardware to a dedicated internal buffer (a dual-port RAM independent of the physical layer timestamp storage, with a configurable capacity of 64 or 128 records) within the chip. This buffer utilizes a first-in-first-out (FIFO) structure to support continuous writes in high-throughput scenarios. Read and write operations are controlled by hardware signals to avoid bus contention with general-purpose memory.

[0040] In this embodiment, the transmission of data associated with the second hardware timestamp is led by the chip's hardware DMA mechanism. Specific features include: Batch, non-interference transfer: When the number of associated records in the dedicated buffer reaches a preset threshold (configurable to 32 / 64 via chip configuration registers), the hardware DMA controller automatically initiates the transfer, moving the records in batches to a preset memory address (specified by the chip initialization configuration). The transfer process does not consume CPU resources, and through direct memory access (DMA), it avoids the delay caused by software copying, resulting in a transfer efficiency improvement of 10 times or more compared to traditional software interrupt methods. Integrity check: DMA-transferred associated records are accompanied by a hardware-generated checksum (e.g., CRC32). The receiving end's hardware logic automatically verifies the checksum to ensure that the association between the timestamp and the message ID has not been tampered with. This addresses the unreliable reliance on software checksums for data integrity in traditional software transmission.

[0041] The above technical solution has the beneficial effect of achieving high-precision time synchronization and timestamp generation through a chip-level hardware-based timestamp generation method based on the PTP protocol. The chip's built-in PTP protocol stack and hardware timestamp mechanism accurately record the times of synchronization and delay request messages, ensuring precise calculation of clock deviation and efficient adjustment of the local clock. Upon message reception, a second hardware timestamp is generated and associated with the data message, effectively improving timestamp precision and accuracy. The built-in timestamp processing unit performs timestamp format conversion and accuracy calibration, ensuring that the generated standardized timestamp information meets high-precision requirements. This can be widely used in applications requiring precise time synchronization, improving overall system performance and reliability.

[0042] Sinking the capture point of the first hardware timestamp to the physical layer and directly triggering it using the physical layer signal transition edge eliminates protocol stack processing delays at the source. This is the core hallmark of chip-level hardware implementation. The entire process is completed by the chip's internal hardware logic (physical layer trigger circuit, high-precision timer, dual-port RAM, dedicated interrupt circuit) without any software intervention, ensuring high timestamp accuracy and real-time performance.

[0043] Example 2:

[0044] The present invention provides a chip-level hardware timestamp generation method based on the PTP protocol. The chip receives synchronization messages and delay request messages from a master clock through the chip's built-in PTP protocol stack. The method evaluates the physical layer signal at the instant when the synchronization message and delay request message arrive at the physical layer interface's physical layer signal transition edge, and records a first hardware timestamp based on the evaluation result, including:

[0045] Detects synchronization messages and delay request messages received by the physical layer and parses the message frame header to identify the message type and unique sequence number;

[0046] At the physical layer signal transition edge when the synchronization message and delay request message arrive at the physical layer interface, the high-precision timer inside the chip is triggered, and the signal sampling window is started at the same time to collect physical layer signal samples within the preset window;

[0047] Calculate signal quality parameters based on signal samples within a preset window before and after the physical layer signal transition edge. Signal quality parameters include: signal jitter variance, signal rise and fall time ratio, transition sharpness factor, and path interference index.

[0048] determining a signal quality evaluation coefficient based on the signal quality parameter;

[0049] The signal level is determined according to the signal quality evaluation coefficient, and the count value of the high-precision timer is latched based on the signal level:

[0050] The latched count value is read as a first hardware timestamp, and the first hardware timestamp is associated with the message type, the sequence number, and the signal quality evaluation coefficient and stored in a dedicated register group inside the chip.

[0051] In this embodiment, latching the count value of the high-precision timer refers to performing different latching operations based on different signal levels.

[0052] Specifically, if it is a high-quality grade, the count value at the center of the transition edge is directly latched;

[0053] If it is good, perform weighted fitting on the count values ​​corresponding to the three sample points before and after the transition edge, where the weight is positively correlated with the signal quality parameter of the sample point, and use the fitting result as the latch value;

[0054] If it is at the calibration level, the chip's built-in historical high-quality signal feature library is called to cache the timing features of nearly 100 high-quality jumps. The actual jump moment is predicted through feature matching, the predicted value is used as the latch value, and the confidence level of the count value is marked.

[0055] In this embodiment, the synchronization message and delay request message types and sequence numbers are Sync messages sent by the master clock node (GrandmasterClock) (for one-way time synchronization) and Delay_Req messages triggered by the slave clock node (for two-way delay measurement), which comply with the message format and timing requirements defined by the IEEE1588 protocol; Message type Synchronization message (Sync): Periodically broadcast by the master clock for one-way time synchronization (PTPv2 protocol definition). If the "two-step synchronization" mode is adopted, the master clock then sends a Follow_Up message carrying an accurate Sync sending timestamp; Delay request message (Delay_Req): Actively sent by the slave clock, the master clock responds with a Delay_Resp message, which is used to calculate the two-way transmission delay (correction of the asymmetry of the network path); Sequence number (SequentialNumber), the PTP message header contains sequenceId (16 bits), and this value is increased by 1 each time a PTP message is sent, which is used to uniquely identify the message and confirm the loss or disorder of the message; Identification method: In the PH The Y / MAC layer parses the message header (EtherType = 0x88F7, PTP message type field messageType) and extracts the sequence ID for recording. Example 1 (Hardware Identification Process): The PHY chip detects the PTP message (EtherType = 0x88F7) → extracts the PTP message Type (Sync = 0x0, Delay_Req = 0x1) and records the sequence ID. FPGA logic circuit detection: If the Sync / Delay_Req type matches, timestamp recording is immediately triggered.

[0056] In this embodiment, the types and sequence numbers of synchronization messages and delay request messages are identified (specific identification method: specific fields of the PTP message are detected in real time through the physical layer (PHY) or MAC layer message parsing logic, including: the EtherType field (0x88F7) identifies the PTP message; the PTP message type field (messageType) distinguishes Sync (0x0) from Delay_Req (0x1); the sequence number field (sequenceId) is used to uniquely identify the message timing; implementation method: PHY chip-level identification (low latency): PHY hardware logic (such as Broadcom / Aquantia chip) detects the Ethernet frame preamble + PTP identifier and completes preliminary filtering at the PHY layer; triggering timestamp moment: detecting the arrival of the first bit of the PTP message, rather than complete parsing (to avoid protocol stack delay); MAC layer hardware parsing (FPGA / ASIC): setting PTP-specific matching logic at the MAC layer.

[0057] In this embodiment, the first hardware timestamp is associated with the sequence numbers of the synchronization message and the delay request message and is stored by establishing a mapping relationship between the timestamp and the PTP message sequence number through a hardware lookup table (LUT) or an on-chip SRAM. Specifically, the following steps are performed: while recording the timestamp, the current sequenceId is latched; the timestamp and sequenceId are written to the dual-port RAM (DPRAM) for the PTP protocol stack to read on demand; if streaming processing is used, a timestamp FIFO buffer can be added to ensure high throughput; and a verification mechanism: a CRC check can be added to ensure that the timestamp-sequenceId binding is correct.

[0058] In this embodiment, notifying the PTP protocol stack to read the first hardware timestamp by means of a hardware interrupt is to send an event notification to the PTP protocol stack core through a low-latency hardware interrupt signal (such as MSI / MSI-X). The specific process includes: after the timestamp recording is completed, the hardware triggers the interrupt controller (such as APIC) to generate an interrupt; the interrupt service routine (ISR) of the PTP protocol stack reads the timestamp buffer and performs clock deviation calculation; a polling + interrupt hybrid mode is adopted to balance real-time performance and CPU load; optimized implementation method: dedicated interrupt pin: such as reserving an independent interrupt line for the PTP timestamp in the SoC design (avoiding shared interrupt delay); DMA direct transmission: timestamp data is written to the protocol stack memory via DMA to reduce CPU intervention (suitable for high-speed network scenarios).

[0059] In this embodiment, the signal quality parameter refers to a set of characteristic indicators used to quantitatively evaluate the quality of physical layer signals and reflect the reliability of timestamp capture.

[0060] Specifically, the signal quality parameters are obtained by performing multi-dimensional analysis on signal samples in a preset window before and after the physical layer signal transition edge, such as the signal samples within 4 clock cycles before and after the transition edge. Each parameter has an independent physical meaning and evaluation dimension.

[0061] In this embodiment, the signal jitter variance reflects the temporal stability of the signal transition edge over multiple cycles, and is obtained by calculating the degree of deviation of n consecutive transition edge moments relative to the average moment, where n ≥ 10. The smaller the variance value, the more concentrated the transition edge time distribution and the higher the timestamp capture accuracy.

[0062] In this embodiment, the signal rise and fall time ratio measures the symmetry of the rising and falling edges of the signal. Ideally, R1 = 1. When R1 deviates from 1, it indicates that the signal has rise and fall edge distortion, which may be caused by factors such as link asymmetry and signal reflection, affecting the accuracy of the transition edge determination.

[0063] In this embodiment, the transition sharpness factor evaluates the steepness of the signal transition edge and is defined as the ratio of the actual time for the signal to transition from 20% amplitude to 80% amplitude to the theoretical minimum transition time. The closer S is to 1, the closer the signal transition is to the ideal state, and the higher the edge certainty captured by the timestamp.

[0064] In this embodiment, the path interference index quantifies the multipath effect and electromagnetic interference degree in the signal transmission path.

[0065] For example, the value of M is obtained by analyzing the power ratio of the third harmonic component in the signal spectrum. A larger value of M indicates more severe signal distortion and a larger deviation may exist in the timestamp.

[0066] Specifically, the signal jitter variance can be obtained in the following manner: Signal jitter variance: The chip's built-in multi-phase sampling circuit samples 16 consecutive transition edges, and the hardware statistics module calculates the mean sum of squares of time offsets in real time, with a calculation period of ≤1μs.

[0067] Specifically, the signal rise and fall time ratio can be obtained by: within the transition edge sampling window, two high-speed comparators are used to detect the moments when the signal amplitude crosses the 20% and 80% thresholds respectively, and the time difference is measured by a hardware timer. The rise / fall time is measured 5 times each and the average value is taken to calculate the ratio.

[0068] Specifically, the transition sharpness factor is a real-time comparison of the actual measured rise and fall times with the theoretical minimum transition time stored in the chip OTP. The hardware divider outputs the ratio result. The theoretical minimum transition time is calculated based on the chip process parameters.

[0069] Specifically, the path interference index can be obtained by performing spectrum analysis on the signal within the sampling window through a 128-point FFT hardware module, and extracting the power ratio of the third harmonic component by a dedicated power calculation unit, with the calculation process taking ≤ 256 clock cycles.

[0070] In this embodiment, the signal jitter variance, signal rise and fall time ratio, transition sharpness factor, and path interference index are normalized to calculate the signal quality evaluation coefficient:

[0071]

[0072] Among them, the standardized parameters include:

[0073] Signal jitter variance:

[0074]

[0075] Rise / Fall Time Ratio:

[0076]

[0077] Transition sharpness factor:

[0078]

[0079] Path interference index:

[0080]

[0081] Among them, Q is the signal quality evaluation coefficient, is the standardized parameter, i=1,2,3,4, is the normalized value of the signal jitter variance, corresponding to the original parameter: signal jitter variance It is an indicator to measure the stability of signal transition time. It calculates the deviation between the transition time of n consecutive times and the average time. The smaller the value, the more concentrated the transition time is and the higher the capture accuracy is. It is the ideal jitter variance benchmark value for chip design, determined by the chip process and physical layer characteristics, and serves as a reference for jitter evaluation. It is the standardized value of the rise and fall time ratio, corresponding to the original parameter rise and fall time ratio R1. R1 is an indicator to measure the symmetry of the rising and falling edges of the signal. Ideally, R1 = 1, and the rising and falling edges are symmetrical. Deviation from 1 indicates signal distortion, such as link asymmetry and edge tilt caused by reflection. It is the standardized value of the transition sharpness factor, corresponding to the original parameter: transition sharpness factor S. S is an indicator to measure the steepness of the signal transition edge. Ideally, S = 1 means the transition edge is the steepest; S > 1 means the transition edge is gentle, which will reduce the edge certainty captured by the timestamp. It is the normalized value of the path interference index, corresponding to the original parameter path interference index M, M = 0, no interference; the larger the M, the more serious the signal distortion, which will introduce timestamp deviation.

[0082] in, is a parametric correlation coefficient matrix; for example, typical values ​​may be:

[0083]

[0084] The rows and columns of the correlation coefficient matrix correspond to the order of the signal quality parameters, as follows:

[0085] Row / column 1: corresponds to signal jitter variance, row / column 2: corresponds to signal rise and fall time ratio, row / column 3: corresponds to jump sharpness factor, row / column 4: corresponds to path interference index, the elements in the matrix The physical meaning of is: the correlation strength between the i-th parameter and the j-th parameter, ranging from [-1, 1]. The larger the absolute value, the stronger the correlation.

[0086] in, is the penalty intensity factor, which controls the intensity of the penalty term for the difference between parameters and adjusts the influence of parameter consistency on Q. When the performance of different parameters is quite different, such as small jitter but strong interference, Amplify the penalty effect and reduce the Q value;

[0087] in, is a dynamic weight coefficient that reflects the importance of different signal quality parameters in a specific link and is dynamically adjusted according to the link type;

[0088] Optionally, the link type can be: optical fiber, copper cable, and wireless;

[0089] Exemplarily, a fiber optic link: =0.4, =0.4, because optical fiber is more sensitive to edge stability; copper cable link: =0.5, because jitter is the main error source in copper cable transmission.

[0090] The beneficial effects of the above technical solution are: through the chip's built-in PTP protocol stack and high-precision timer, the first hardware timestamp can be accurately recorded when synchronization messages and delay request messages arrive at the physical layer interface, avoiding the delays and errors of traditional software timestamp processing. This method notifies the PTP protocol stack to read the timestamp through a hardware interrupt, further improving the real-time performance and accuracy of time synchronization. By associating the timestamp with the message sequence number, the accurate matching of the timestamp and the message is ensured, thereby improving the efficiency and reliability of the entire time synchronization system. It is suitable for applications requiring high precision and high real-time performance.

[0091] Example 3:

[0092] The present invention provides a chip-level hardware timestamp generation method based on the PTP protocol. The method generates and sends a delay response message in response to a received delay request message, obtains bidirectional transmission delay data by exchanging delay request and delay response messages, and calculates clock deviation based on a first hardware timestamp and the bidirectional transmission delay data. The method includes:

[0093] After receiving the delay request message, calculating a reception time of the delay request message based on the first hardware timestamp;

[0094] Generate a delay response message and record the sending time of the message with a MAC layer timestamp;

[0095] Calculate the two-way transmission delay data based on the reception time of the delay request message and the sending time of the delay response message;

[0096] Extract the master clock sending time from the synchronization message, and calculate the one-way delay data of the message transmission according to the first hardware timestamp and the master clock sending time;

[0097] The clock deviation between the master and slave clocks is calculated based on the one-way delay data and the two-way transmission delay data.

[0098] In this embodiment, the reception time of the delay request message is calculated based on the first hardware timestamp (recording the time when Delay_Req arrives at the PHY layer) and the local clock frequency compensation value, and the actual reception time (T2) of the message at the slave clock node is calculated. The calculation formula is:

[0099]

[0100] in, It is the timestamp value recorded by the PHY layer (local clock count); is the estimated deviation of the current local clock from the master clock (from the last synchronization adjustment);

[0101] Hardware timestamp (PHY layer): records the reception time of the message through hardware to avoid jitter caused by the software protocol stack, with an accuracy of nanosecond level (such as Intel I210 network card); Frequency compensation: When the local clock is not fully synchronized, the local clock drift needs to be corrected (based on the adjustment value of the DCO).

[0102] In this embodiment, the generation of the delay response message is performed by the PTP protocol stack hardware module of the slave clock node to generate a Delay_Resp message that complies with the IEEE1588 standard, and includes the following fields: requesting source identifier (requestingPortIdentity): identifies the slave clock that sends the Delay_Req; reception time (T3) recorded by the master clock: the hardware timestamp of the master clock when receiving the Delay_Req; sequenceId: consistent with the sequence number of the Delay_Req message, used for association matching; example process: 1. The slave clock detects the Delay_Req message → records the reception time T2; 2. The master clock receives the Delay_Req → records the reception time T3, and replies with the Delay_Resp; 3. The slave clock receives the Delay_Resp and extracts T3 for two-way delay calculation.

[0103] In this embodiment, the calculation of the two-way transmission delay data is based on the PTP end-to-end (E2E) delay measurement mechanism, and the two-way transmission delay (D) of the message between the master and slave clocks is calculated using the following formula:

[0104]

[0105] in, The time when the master clock sends the Sync message (derived from the Follow_Up message). It is the PHY timestamp of receiving the Sync message from the clock; is the time when the master clock receives Delay_Req (from Delay_Resp); It is the MAC timestamp of sending Delay_Resp from the clock; physical meaning: is the total round trip time (RTT); It is the cumulative effect of the master-slave clock time deviation (Offset); Divide by 2: Assume that the network path is symmetrical. If it is not symmetrical, it needs to be corrected. The correction formula is:

[0106]

[0107]

[0108] in, is the corrected one-way transmission delay, is the comprehensive asymmetry value:

[0109]

[0110] in, is the real-time link load factor (calculated by the chip's built-in link monitoring hardware module, based on the ratio of current throughput to bandwidth, with a hardware update period of ≤1ms), : Real-time chip temperature (collected by built-in temperature sensor hardware, accuracy ≤1°C); : Reference temperature (such as 25°C, pre-stored in the register), is the normalization parameter, It is a fixed asymmetry value calibrated for network devices (such as the delay difference between switch queues). This value is pre-stored in the chip configuration register. The source is a fixed value obtained and pre-stored in the chip through the following methods: Factory calibration: During the chip production phase, the one-way delay difference between the master and slave nodes is measured using a dedicated network tester, and the result is written to the chip configuration register (such as by burning through the JTAG interface); Dynamic configuration: During system initialization, the asymmetric parameters of the current network topology are obtained from the server through a network management protocol (such as SNMP) and updated to the chip register;

[0111] In this embodiment, the one-way delay data is calculated based on the master clock sending time (T1) of the Sync message and the PHY receiving timestamp (T2) of the slave clock to calculate the one-way transmission delay (d):

[0112]

[0113] in, The last calculated clock deviation (cached by the chip configuration register) is used to preliminarily eliminate the impact of historical deviation on one-way delay. The last calculated clock deviation is obtained from the clock deviation of the previous round. After the system starts or the master clock is switched, there is no historical deviation during the first synchronization. The initial clock deviation is determined by the following hardware mechanism: Coarse synchronization stage: After the chip is powered on, the local clock runs based on the built-in crystal oscillator (with low accuracy and may have a large deviation from the master clock). When the Sync message of the master clock is received for the first time, the PHY layer captures the original timestamp , at this time, since there is no historical deviation, then:

[0114] ;

[0115] In this embodiment, the first Delay_Req / Delay_Resp message interaction is completed based on the process of this embodiment, and the , calculate the initial two-way delay:

[0116]

[0117] in, : The hardware timestamp when the clock sends the Sync message is captured by the master clock's local high-precision timer and transmitted to the slave clock through the subsequent Follow_Up message.

[0118] : The timestamp when the master clock receives the Delay_Req message sent by the slave clock. It is recorded by the master clock timer and sent back to the slave clock through the Delay_Resp message. : Timestamp captured by the MAC layer hardware when the slave clock sends the Delay_Resp message;

[0119] Delay the initial two-way delay Corrected for initial one-way delay : , based on the first synchronization 、 as well as Determining the initial clock bias , and store it in the register as the first clock deviation for the next round of synchronization:

[0120]

[0121] In this embodiment, after d is calculated, based on Verify the rationality of d (for example, when the deviation between the two exceeds the threshold, trigger Dynamic updates;

[0122] In this embodiment, the clock deviation between the master and slave clocks is calculated by combining the one-way delay and the two-way delay to obtain the master-slave clock deviation. :

[0123]

[0124] Perform correlation calculation on the associated formula to obtain = , is the direct result of the mathematical connection between the formulas. Its essence is to achieve iterative transmission of clock deviation through the logical closed loop of "stripping historical deviation - extracting current delay - calculating current deviation", ensuring the consistency and high precision of master-slave clock synchronization. This result is not "deviation is not updated", but the precise connection between historical value and current value in the hardware synchronization mechanism, because the previous round of The chip's internal digitally controlled oscillator (DCO) has been used for real-time adjustment to become the "corrected current deviation";

[0125] In this embodiment, Stored in chip-specific registers, it can be directly read by the hardware unit without CPU intervention; the current value Calculations are performed in real time (latency ≤ 1ns) by the hardware arithmetic unit, and the results are directly used to adjust the frequency of the chip's internal digitally controlled oscillator (DCO). This hardware closed-loop of "historical value storage - current value calculation - deviation correction" avoids the delays associated with traditional software synchronization, such as data transfer and thread scheduling, ensuring a synchronization response time of ≤ 10ns, meeting nanosecond-level precision requirements.

[0126] The beneficial effects of this technical solution include: through chip-level layered hardware timestamping, frequency compensation, and dynamic asymmetry calibration, it breaks through the traditional symmetry assumption and corrects asymmetric path delays. Hardware closed-loop synchronization achieves nanosecond-level accuracy, end-to-end computational latency ≤ 10ns, 24-hour deviation ≤ 1μs, and 80% power reduction. This improves synchronization accuracy in asymmetric scenarios, and hardware-based deviation detection improves synchronization precision.

[0127] Example 4:

[0128] The present invention provides a chip-level hardware-based timestamp generation method based on the PTP protocol. According to the clock deviation, the local clock frequency is adjusted by the chip's internal digitally controlled oscillator to synchronize the local clock with the master clock, including:

[0129] converting the calculated clock deviation into a digital control signal for a digitally controlled oscillator;

[0130] Writing a digital control signal into a configuration register of a digitally controlled oscillator via an internal bus of the chip, and adjusting the local clock frequency in the configuration register based on the digital control signal;

[0131] The system detects the stability of the adjusted clock in real time and provides feedback on the correction margin. When the correction margin meets the preset threshold, the local clock synchronization is completed.

[0132] In this embodiment, the calculated clock deviation is converted into a digital control signal for a digitally controlled oscillator by converting the calculated master-slave clock deviation value (Δt) into an adjustable parameter of the digitally controlled oscillator (DCO) through digital control logic (DCO control algorithm), including: frequency adjustment direction (increasing or decreasing the local clock frequency); quantized value of the control word (ControlWord) for accurately correcting the output frequency of the oscillator; examples of conversion methods include: proportional-integral (PI) algorithm: dynamically adjusting the control signal strength based on the accumulated historical deviation value; lookup table (LUT) mapping: pre-stored correspondence between the deviation value and the control word to avoid real-time calculation delays.

[0133] In this embodiment, writing the digital control signal into the configuration register of the digitally controlled oscillator through the internal bus of the chip is to write the digital control signal into the frequency control register of the digitally controlled oscillator (DCO) through the on-chip bus (such as APB / AXI) or the dedicated configuration interface, specifically including: register address mapping: assigning a specific memory mapping address to the DCO; atomic write operation: ensuring the integrity and real-time performance of the control signal; hardware trigger mechanism: automatically triggering the DCO frequency update after the write operation is completed; embodiment: SoC integration scenario: the CPU writes to the DCO configuration register through the APB bus without the need for software polling; FPGA implementation: the hardware state machine directly operates the register to avoid bus competition delay.

[0134] In this embodiment, the local clock frequency is adjusted based on a digital control signal in a configuration register: the frequency synthesis logic of the DCO dynamically adjusts the output clock according to the control word (for example: a 32-bit unsigned integer) of the configuration register, including: discrete tuning of the voltage-controlled oscillator (VCO): adjusting the oscillation frequency through a capacitor array or a current source; a fractional-NPLL: achieving sub-ppm precision compensation; a closed-loop response: ensuring that the frequency adjustment maintains a linear relationship with the control signal; technical features: real-time: effective within 1 to 10 clock cycles after the register is written; resolution: the least significant bit (LSB) of the control word corresponds to a frequency step of ≤0.1ppb (one billionth).

[0135] In this embodiment, the stability of the adjusted clock is detected in real time, and the correction margin is fed back by continuously measuring the performance of the adjusted local clock through the clock monitoring module, which specifically includes: a phase error detector (PED): quantifying the residual deviation between the current clock and the ideal clock; a frequency error integrator: counting the cumulative deviation trend over a long period; a correction margin (RemainingSkew): defined as the difference between the current deviation and the target threshold, used to determine the synchronization completion status; an example of a detection method: a digital time interval counter (TIC): comparing the rising edge interval of the local clock and the reference clock; a Kalman filter: suppressing the impact of short-term jitter on stability evaluation.

[0136] In this embodiment, the preset threshold is a clock deviation tolerance threshold (ε) set in advance based on the synchronization accuracy requirements of the application scenario, including: static threshold: a fixed value (such as ±100ns), suitable for deterministic networks; dynamic threshold: adaptively adjusted with the synchronization stage (such as relaxed to 1μs in the initial convergence stage and tightened to 10ns in the steady-state stage); judgment logic: when the correction margin |Δtcurrent|≤ε, it is determined that the clock synchronization is completed.

[0137] The beneficial effect of the above technical solution is that the local clock is efficiently synchronized with the master clock by adjusting the chip's internal digitally controlled oscillator based on the calculated clock deviation. This method converts the clock deviation into a digital control signal and adjusts the local clock frequency in real time via configuration registers, thereby accurately correcting the clock deviation. Real-time clock stability monitoring and feedback of the correction margin ensures accuracy and stability during the adjustment process. When the correction margin meets a preset threshold, clock synchronization is complete. This solution improves the accuracy and real-time performance of time synchronization and is suitable for high-precision clock synchronization applications.

[0138] Example 5:

[0139] The present invention provides a chip-level hardware timestamp generation method based on the PTP protocol. After synchronization is completed, when the chip receives a data message that needs to be timestamped, it records a second hardware timestamp when the message passes through the MAC layer, associates the second hardware timestamp with the corresponding data message, and stores the associated data in a buffer inside the chip, including:

[0140] Detecting the arrival and sending events of MAC layer data messages, and recording a second hardware timestamp for messages in the arrival and sending events that meet the preset timestamp marking conditions;

[0141] The ID of the message that meets the preset timestamp marking condition is associated with the second hardware timestamp and stored in the corresponding buffer inside the chip, and the second hardware timestamp and the message that meets the preset timestamp marking condition are batch transferred to the memory through the hardware DMA mechanism.

[0142] In this embodiment, the arrival and transmission events of MAC layer data packets are detected by monitoring data packet transmission events through the MAC layer timestamp engine. This includes: packet arrival event detection: capturing the start frame delimiter (SFD) of the input packet at the PHY / MAC interface to trigger first-level timestamp recording; packet transmission event detection: triggering second-level timestamp recording when the MAC layer output queue enable signal is valid; preset timestamp marking condition filtering: determining whether to record timestamps based on the packet type identifier (such as the EtherType field) or the timestamp enable flag; technical features: hardware-level triggering (avoiding delays caused by software polling) and protocol filtering (timestamping only specific protocol packets such as PTP / SyncE). Example scenario: When the MAC layer recognizes a PTP message (EtherType = 0x88F7), it automatically triggers the timestamp recording logic.

[0143] In this embodiment, the ID of the message that meets the preset timestamp marking conditions is associated with the second hardware timestamp and stored in the corresponding buffer inside the chip by performing the following operations through the timestamp association logic: message identifier (ID) extraction: intercepting the unique identification field (such as the sequence number SequenceID or hash value) from the message header; timestamp binding: writing the second hardware timestamp (nanosecond accuracy) generated by the MAC layer and the message ID into a dedicated buffer (TimestampFIFO); memory address mapping: allocating a fixed storage structure (such as 64-bit timestamp + 32-bit message ID) for each record. Example: In the IEEE1588 protocol, the SequenceID of the Delay_Req message is associated with the timestamp and stored for subsequent two-way delay calculation.

[0144] In this embodiment, the second hardware timestamp and the messages that meet the preset timestamp marking conditions are transferred to the memory in batches through the hardware DMA mechanism. This is to achieve efficient data transmission using a direct memory access (DMA) controller, including: buffer to memory mapping: the DMA source address points to the physical base address of the timestamp buffer; burst transfer (Burst Transfer): when the amount of buffer data reaches a preset threshold, DMA batch transfer is triggered; memory aligned storage: ensure that the layout of the timestamp and message ID in the memory meets the software parsing requirements (such as structure alignment); optimized design: double buffer mechanism: when DMA moves the current buffer, the timestamp engine can continue to write to the backup buffer; interrupt notification: after DMA is completed, the host is informed through an interrupt that the timestamp data is ready.

[0145] The beneficial effect of the above technical solution is that by accurately recording the second hardware timestamp as the data message passes through the MAC layer and storing it in association with the message ID, the timestamp is accurately matched to the data message. This method utilizes the hardware DMA mechanism to transfer timestamp data in batches, significantly improving processing efficiency and data transmission speed. Using preset timestamp marking conditions, the system can flexibly select messages requiring timestamps, reducing unnecessary data processing burden and thus improving overall system performance and accuracy. This solution provides strong support for applications requiring efficient and accurate time synchronization.

[0146] Example 6:

[0147] The embodiments of the present application provide a chip-level hardware timestamp generation method based on the PTP protocol. Messages that meet preset timestamp marking conditions include: messages whose protocol fields contain a PTP timestamp request flag, messages with user-configured specific source MAC addresses, monitoring messages generated by internal modules of the chip that require high-precision timestamps, key control messages that require time synchronization by network management protocols, and priority messages with time-sensitive network markings.

[0148] In this embodiment, the protocol field contains a message with a PTP timestamp request flag: the IEEE1588 protocol identification module parses the PTP flag field in the message header (such as the OriginTimestamp field or the flag field), and automatically triggers timestamp recording when a time synchronization request (Sync / Delay_Req) ​​or a time-sensitive message (Follow_Up) is detected. For example: Sync message (PTP header MessageType=0x0): the master clock marks the timestamp when sending a synchronization request to the slave clock; Delay_Req message (MessageType=0x1): the slave clock needs to record the sending time when reversely measuring the link delay.

[0149] In this embodiment, for messages with a specific source MAC address configured by the user, the MAC address matching logic compares the message source MAC address with a pre-stored address list in a programmable register (e.g., 00-1B-19-00-00-00). Timestamp recording is activated upon a successful match. Application scenarios: In industrial automation, only messages from specified devices (e.g., PLC controllers) are timestamped; dedicated probe messages sent by network testers require high-precision latency measurement.

[0150] In this embodiment, the monitoring messages generated by the internal modules of the chip require high-precision timestamps: the messages generated by the on-chip monitoring units (such as traffic statistics counters and error detection modules) request additional timestamps through internal marking bits (such as the Time-Critical flag in Metadata) for chip-level performance analysis. For example: the congestion control signaling messages of the switching chip need to be marked with the occurrence time for QoS optimization; the abnormal event report messages of the security module need to accurately record the triggering time.

[0151] In this embodiment, the network management protocol requires key control messages for time synchronization: identifying the time synchronization instruction field carried in the network management protocol (such as SNMPTrap and NetConfRPC), and forcibly inserting timestamps into key messages involving topology updates and configuration delivery. Typical use cases: flow table update messages sent by the SDN controller need to synchronize the clocks of all network devices; IEEE802.1CM time-sensitive network management frames of 5G base stations.

[0152] In this embodiment, priority messages with time-sensitive network tags are timestamped by parsing the VLAN tag priority bit (such as the PCP field of IEEE802.1Q) or the stream identifier (StreamID) of the time-sensitive network (TSN). Related technical standards include: IEEE802.1AS-Rev: Generalized PTP Protocol for TSN Networks; IETF DetNet: Timestamp Binding Requirements in Deterministic Networks.

[0153] The beneficial effect of the above technical solution is that it can accurately timestamp critical messages by filtering specific messages based on preset timestamp marking conditions. This solution can flexibly filter based on multiple conditions such as protocol fields, specific source MAC addresses, monitoring messages, critical control messages, and priority messages, ensuring that only messages requiring high-precision timestamps are processed. In this way, the system can effectively reduce the burden of unnecessary timestamp recording, improve processing efficiency, and simultaneously ensure the time synchronization accuracy of critical data, meeting the requirements of application scenarios with high precision and high reliability.

[0154] Example 7:

[0155] The present invention provides a chip-level hardware-based timestamp generation method based on the PTP protocol. The chip's built-in timestamp processing unit performs format conversion and precision calibration on the timestamp data in the buffer to generate standardized timestamp information, which is then output through the chip interface. The method includes:

[0156] The chip's built-in timestamp processing unit reads the original timestamp data from the buffer and converts the nanosecond timestamp into the second standard format.

[0157] The clock drift compensation algorithm is applied to correct the accumulated error after synchronization, and the abnormal timestamps are processed by median filtering to obtain the standardized timestamp information;

[0158] The standardized timestamp information is output to the host system through the chip interface.

[0159] In this embodiment, the conversion of the nanosecond timestamp into the second standard format is based on the timestamp conversion engine converting the nanosecond timestamp recorded in the buffer (such as a 64-bit counter value) into the second-nanosecond standard format, including: high-order truncation processing: mapping the high 32 bits of the timestamp counter to the second timestamp (secondsfield); low-order retention processing: retaining the low 32 bits as the nanosecond timestamp (nanosecondsfield); format alignment: adjusting the byte order and field offset according to the target protocol (such as IEEE1588 or POSIX standard). For example: if the original timestamp is 1650000000123456789 (64-bit nanosecond count), after conversion it is: seconds part: 1650000000 (high 32 bits); nanosecond part: 123456789 (low 32 bits).

[0160] In this embodiment, the abnormal timestamp is based on the abnormal detection logic to identify the following invalid timestamp data: time jump abnormality: the interval between adjacent timestamps exceeds the preset threshold (such as ±1 second); counter overflow: 32-bit wrap-around occurs when the timestamp counter is not reset; clock desynchronization mark: the timestamp generated when the chip detects a synchronization failure event (such as the PTP master clock is disconnected). Examples of abnormal scenarios: due to network congestion, the sending timestamp of a certain message is delayed, resulting in disordered timestamps; the system clock source switch (such as switching from GPS to local crystal oscillator) causes discontinuous timestamps.

[0161] Among them, the anomaly detection logic is a timestamp credibility verification mechanism built into the chip. It identifies and marks invalid or unreliable timestamps by performing multi-dimensional analysis on the timing characteristics, value range and synchronization status of the timestamp data. It includes the following core functional units: Timing continuity checker: compares the interval difference between adjacent timestamps. If it exceeds the dynamic threshold range (such as ±1 second), it is marked as a time jump anomaly. For example: the previous timestamp is 12:00:00.000, and the current timestamp is 12:00:01.500 (exceeding the preset ±1ms threshold); counter overflow monitor: detects unexpected wraparound of the 32 / 64-bit timestamp counter (i.e., unreceived timestamps); (For example, the 32-bit nanosecond counter jumps from 0xFFFF_FFFF to 0x0000_0000 (normally it should jump to 0x1_0000_0000)); Synchronization status validator: When the PTP protocol stack reports the Sync_Loss or Holdover state, it forces the subsequent timestamps to be marked as unavailable. Trigger conditions: Master clock disconnection, clock class degradation; Technical implementation details include: 1. Time jump anomaly detection: The dynamic window comparator performs the following operations: Calculate the difference Δ between the current timestamp T(n) and the previous timestamp T(n-1) T; if ΔT > the upward threshold (e.g., +1 second), it is considered a hysteresis exception; if ΔT < the downward threshold (e.g., -100ns), it is considered a rollback exception; the threshold is dynamically adjusted based on the clock accuracy level: normal mode: ±1ms, high-precision mode: ±100ns." Hardware implementation example: Use a subtractor to calculate ΔT and compare the result with the threshold in the register. The threshold is configured by software via the APB bus. 2. Counter overflow detection: The sign bit mutation detection circuit monitors the most significant bit (MSB) of the counter: In continuous increment mode, if the MSB changes from 1 to 0 and no reset signal is received, it is considered an illegal wraparound; an overflow exception flag is generated and the time is triggered. Stamp reconstruction logic (such as switching to the backup counter). Abnormal scenario: 32-bit counter: normal count 0x7FFF_FFFF → 0x8000_0000 (no abnormality), abnormal wraparound: 0xFFFF_FFFF → 0x0000_0000 (missing carry). 3. Clock desynchronization determination: The state machine monitoring unit interacts with the PTP protocol engine and activates the desynchronization flag when the following events occur: three consecutive Sync messages are lost (based on the BMCA algorithm); clock accuracy is degraded (ClockClass ≥ 7 per IEEE 1588); the local oscillator enters holdover mode.

[0162] In this embodiment, median filtering is performed on abnormal timestamps to obtain standardized timestamp information by performing the following operations: sliding window sampling: obtaining N valid samples before and after the current timestamp (e.g., N=5); median filtering: eliminating abnormal values ​​that deviate from the median by more than a threshold; linear interpolation: using adjacent valid timestamps to infer a reasonable value at the current moment. An example of the filtering effect is shown in Table 1:

[0163] Table 1

[0164]

[0165] In this embodiment, the standardized timestamp information is output to the host system through the chip interface, including the following operations: protocol encapsulation: binding the standardized timestamp and the corresponding message ID to a timestamp record structure (such as: {seconds, nanoseconds, message sequence number}); bus transmission: batch uploading to the host memory through a high-speed peripheral interface (such as PCIe or AXI-Stream); interrupt notification: when the timestamp data reaches the preset queue depth, an interrupt signal is triggered to notify the host to read; interface type examples: industrial control scenario: directly mapped to the master station memory through EtherCAT's FMMU (Fieldbus Memory Management Unit); data center scenario: using RDMA (remote direct memory access) to transmit timestamp data across nodes.

[0166] The beneficial effects of this technical solution are: the chip's built-in timestamp processing unit can efficiently convert the format and calibrate the timestamp data in the buffer, ensuring that the timestamp information meets standardization requirements. This not only achieves the conversion of nanosecond timestamps to the second standard format, but also eliminates synchronization errors and abnormal data through clock drift compensation algorithms and median filtering, improving the accuracy and stability of timestamps. Finally, the standardized timestamp information is output to the host system through the chip interface, ensuring high-precision synchronization and reliable transmission of data to meet the needs of high-precision applications.

[0167] Example 8:

[0168] The present embodiment provides a chip-level hardware timestamp generation method based on the PTP protocol. It applies a clock drift compensation algorithm to correct the accumulated error after synchronization and performs median filtering on abnormal timestamps to obtain standardized timestamp information, including:

[0169] Collect timestamp deviation samples within a preset time window to form a timestamp deviation sequence;

[0170] The clock drift slope prediction value is calculated based on the least squares method fitting the timestamp deviation sequence;

[0171] Generate a timestamp compensation coefficient based on the clock drift slope prediction value to compensate the timestamp data;

[0172] The sliding window median filter algorithm is used to eliminate the pulse-type outliers in the timestamp deviation sequence;

[0173] Convert the compensated timestamp data to the preset standard time format.

[0174] In this embodiment, the preset time window is the statistical duration (calibration window) of the time deviation sampling set by the dynamic calibration period configuration unit. Its duration is dynamically adjusted according to the clock stability requirements, ranging from milliseconds (high-precision scenario) to minutes (energy-saving mode). For example, 5G base station synchronization requires a 1ms short window for fast convergence; industrial Internet of Things nodes can use a 10s long window to reduce power consumption.

[0175] In this embodiment, timestamp deviation samples are collected within a preset time window. The timestamp deviation sequence is formed by periodically recording the master-slave clock time difference (offset samples) within the time window to form a time deviation queue containing N consecutive measurement values. Each sample is associated with the local clock value at the time of collection. An example of the data structure is shown in Table 2:

[0176] Table 2

[0177]

[0178] In this embodiment, the clock drift slope prediction value is calculated based on the least squares method to fit the timestamp deviation sequence. The following operations are performed on the time deviation queue: a timestamp-deviation two-dimensional coordinate system is established (X-axis: local time, Y-axis: deviation value); the best straight line is fitted by the least squares method, and its slope is the clock frequency drift rate (unit: ns / s); and the slope is recalculated after eliminating outliers with residuals exceeding 3σ.

[0179] In this embodiment, the timestamp compensation coefficient is generated according to the predicted value of the clock drift slope to compensate the timestamp data. The drift slope is converted into a proportional factor (for example, 1.000025), and a reverse correction is applied to the subsequent timestamps in real time through a hardware multiplier: compensation formula: calibrated timestamp = original timestamp × (1-drift rate). Compensation example: if the predicted drift rate is +100ns / s, 100ns needs to be subtracted from the local time every 1 second to align with the master clock.

[0180] In this embodiment, the timestamp compensation coefficient is a fixed-point number stored in the compensation coefficient register, which represents the time difference to be compensated per unit time (e.g., +32'h0000019A represents +410ns / s). It supports dynamic updates to track clock drift changes caused by ambient temperature. The implementation method is as follows: the upper 32 bits: second-level compensation amount; the lower 32 bits: nanosecond-level compensation amount.

[0181] In this embodiment, a sliding window median filter algorithm is used to eliminate pulse-type outliers in the timestamp deviation sequence. The following steps are used to process data: a sliding window of length K (typical value K=5) is maintained and the latest deviation sample is stored; the data in the window is sorted and the median is taken as the valid output; when the median exceeds the threshold for M consecutive times (for example, M=3), a clock synchronization anomaly alarm is triggered. The filtering effect is shown in Table 3:

[0182] Table 3

[0183]

[0184] In this embodiment, the preset standard time format complies with the binary time code format defined by IEEE1588-2019, including: 48-bit second count (covering a range of >9000 years); 32-bit nanosecond count (accuracy <1ns); 8-bit time zone identifier (supporting UTC / TAI switching), as shown in Table 4 for comparison:

[0185] Table 4

[0186]

[0187] The beneficial effects of this technical solution are as follows: through the clock drift compensation algorithm and least squares fitting, it can effectively correct the clock drift errors accumulated during the synchronization process, improving the accuracy of the timestamp data. By generating a timestamp compensation coefficient and compensating the timestamp data, the accuracy of the synchronization is further improved. At the same time, the sliding window median filter algorithm effectively removes pulse-type outliers, enhancing the system's robustness to abnormal data. Finally, the compensated timestamp data is converted to a standard time format, ensuring the accuracy and consistency of the timestamps and meeting the requirements of high-precision clock synchronization.

[0188] Example 9:

[0189] The present embodiment provides a chip-level hardware timestamp generation method based on the PTP protocol. The method uses the least squares method to fit the timestamp deviation sequence and calculate the clock drift slope prediction value, including:

[0190] A linear regression model of timestamp deviation and time variable is established, and the slope parameter of the linear regression model is solved as the predicted value of clock drift slope.

[0191] In this embodiment, establishing a linear regression model of timestamp offset and time variable includes: constructing a two-dimensional data set of timestamp offset sequence (offset) and sampling time (timestamp), and calculating the best fitting line using the least squares method (LSM). The mathematical expression is:

[0192]

[0193] in: (Independent variable): sampling time (usually the local clock value, unit: seconds or nanoseconds); (Observed value): master-slave clock deviation at the corresponding time (unit: nanosecond); (slope): predicted clock drift rate (unit: ns / s); (Intercept): initial synchronization deviation; Data preprocessing: Remove outliers: If the residual of a point (actual value y_i - fitted value ŷ_i) exceeds ±3σ (standard deviation), it is considered an outlier and excluded, and refitted; Window sliding update: For each new sample, the oldest sample is eliminated to maintain a fixed number of samples (for example, N=50).

[0194] In this embodiment, the slope parameter of the linear regression model is used as the clock drift slope prediction value to solve the k value using the least squares method:

[0195]

[0196] in: : effective sample size; The cumulative sum of all sampling moments; : The cumulative sum of all clock deviations; Cumulative sum of products; : The cumulative sum of the squares at the sampling time, the calculation example data is shown in Table 5: (after eliminating abnormalities):

[0197] Table 5

[0198]

[0199] As shown in Table 5, the calculation process is as follows: number of samples N = 4; numerator: 4×1905-(1+2+4+5)×590=7620-7080=540; denominator: 4×46-(1+2+4+5)²=184-144=40; slope = k=540 / 40=13.5ns / s.

[0200] This embodiment also includes: establishing a dynamic optimization mechanism for a long-term drift feature library: constructing a drift feature matrix based on historical clock drift slope data; using a K-means clustering algorithm to perform pattern recognition on the drift feature matrix to obtain a set of typical drift patterns; establishing a mapping relationship table between drift patterns and network environment parameters; when a change in the current network environment parameters is detected, preloading corresponding drift compensation parameters according to the mapping relationship table; and regularly updating the drift feature matrix and the mapping relationship table to optimize compensation accuracy.

[0201] The drift feature matrix includes the following feature dimensions: clock drift slope mean; drift standard deviation; maximum positive drift; maximum negative drift; drift direction persistence statistics;

[0202] Among them, network environment parameters include: current network topology structure identifier; data transmission link quality coefficient; PTP message transmission path hop count; network delay jitter variance; device temperature parameters.

[0203] This embodiment also includes: a dynamic optimization mechanism, the execution process of which is: (1) periodically collecting clock drift slope and network environment parameter samples; (2) triggering the feature matrix update when the number of samples reaches a threshold; (3) recalculating the K-means clustering center point; (4) updating the mapping relationship between the drift pattern and the environment parameters; (5) verifying the compensation accuracy improvement rate before and after optimization.

[0204] The beneficial effects of this technical solution include: by establishing a linear regression model between timestamp deviation and time variables, it is possible to accurately calculate the predicted clock drift slope value and effectively predict clock drift trends. Least squares fitting of the timestamp deviation sequence ensures the accuracy of the clock drift slope calculation, simplifies the error compensation steps during clock synchronization, and improves synchronization reliability and accuracy. Accurately predicting clock drift can better calibrate the deviation between the local clock and the master clock, ensuring stable operation of high-precision clock synchronization in complex environments.

[0205] Example 10:

[0206] The embodiment of the present application provides a chip-level hardware timestamp generation system based on the PTP protocol, such as Figure 2 Shown, including:

[0207] Physical layer timestamp capture module: Receives synchronization messages and delay request messages from the master clock through the chip's built-in PTP protocol stack, evaluates the physical layer signal at the instant the synchronization message and delay request message reach the physical layer interface's physical layer signal transition edge, and records the first hardware timestamp based on the evaluation result;

[0208] Two-way delay calculation module: In response to the received delay request message, it generates and sends a delay response message and records the sending timestamp at the MAC layer. It obtains two-way transmission delay data by exchanging delay request and delay response messages, and calculates the clock deviation by combining the first hardware timestamp and the two-way transmission delay data.

[0209] Clock synchronization control module: According to the clock deviation, the local clock frequency is adjusted through the digital controlled oscillator inside the chip to synchronize the local clock with the master clock;

[0210] MAC layer timestamp module: After synchronization is completed, when the chip receives a data message that needs to be timestamped, it records the second hardware timestamp when the message passes through the MAC layer, associates the second hardware timestamp with the corresponding data message, and stores the associated data in the buffer inside the chip;

[0211] Timestamp standardization output module: Through the chip's built-in hardware timestamp processing unit, the timestamp data in the buffer is format converted and the accuracy is calibrated to generate standardized timestamp information, which is then output through the chip interface.

[0212] The above technical solution has the beneficial effect of achieving high-precision time synchronization and timestamp generation through a chip-level hardware-based timestamp generation method based on the PTP protocol. The chip's built-in PTP protocol stack and hardware timestamp mechanism accurately record the times of synchronization and delay request messages, ensuring precise calculation of clock deviation and efficient adjustment of the local clock. Upon message reception, a second hardware timestamp is generated and associated with the data message, effectively improving timestamp precision and accuracy. The built-in timestamp processing unit performs timestamp format conversion and accuracy calibration, ensuring that the generated standardized timestamp information meets high-precision requirements. This can be widely used in applications requiring precise time synchronization, improving overall system performance and reliability.

[0213] It is not difficult to find that this embodiment is a system embodiment corresponding to Example 1, and this embodiment can be implemented in conjunction with Example 1. The relevant technical details mentioned in Example 1 are still valid in this embodiment, and to reduce repetition, they are not repeated here. Accordingly, the relevant technical details mentioned in this embodiment can also be applied in Example 1.

[0214] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any person skilled in the art may easily propose variations or substitutions within the technical scope disclosed in the present application, and such variations or substitutions shall be encompassed within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be subject to the scope of protection of the claims, and the above embodiments shall be regarded as exemplary and non-limiting.

Claims

1. A chip-level hardware timestamp generation method based on the PTP protocol, characterized in that: include: Step 1: Receive synchronization messages and delay request messages from the master clock through the chip's built-in PTP protocol stack, evaluate the physical layer signal at the instant the synchronization message and delay request message arrive at the physical layer interface's physical layer signal transition edge, and record the first hardware timestamp based on the evaluation result; Step 2: In response to the received Delay Request message, generate and send a Delay Response message and record the sending timestamp at the MAC layer. By exchanging the Delay Request and Delay Response messages, obtain the two-way transmission delay data, and calculate the clock offset by combining the first hardware timestamp and the two-way transmission delay data. Step 3: Based on the clock deviation, the local clock frequency is adjusted through the digitally controlled oscillator inside the chip to synchronize the local clock with the master clock; Step 4: After synchronization is completed, when the chip receives a data message that needs to be timestamped, it records the second hardware timestamp when the message passes through the MAC layer, associates the second hardware timestamp with the corresponding data message, and stores the associated data in the buffer inside the chip; Step 5: The chip's built-in hardware timestamp processing unit performs format conversion and precision calibration on the timestamp data in the buffer to generate standardized timestamp information, which is then output through the chip interface.

2. The chip-level hardware timestamp generation method based on the PTP protocol according to claim 1, characterized in that: The chip receives synchronization messages and delay request messages from the master clock through the built-in PTP protocol stack. It evaluates the physical layer signal at the instant when the synchronization message and delay request message arrive at the physical layer interface. Based on the evaluation result, it records the first hardware timestamp, including: Detects synchronization messages and delay request messages received by the physical layer and parses the message frame header to identify the message type and unique sequence number; At the physical layer signal transition edge when the synchronization message and delay request message arrive at the physical layer interface, the high-precision timer inside the chip is triggered, and the signal sampling window is started at the same time to collect physical layer signal samples within the preset window; Calculate signal quality parameters based on signal samples within a preset window before and after the physical layer signal transition edge. Signal quality parameters include: signal jitter variance, signal rise and fall time ratio, transition sharpness factor, and path interference index. determining a signal quality evaluation coefficient based on the signal quality parameter; The signal level is determined according to the signal quality evaluation coefficient, and the count value of the high-precision timer is latched based on the signal level: The latched count value is read as a first hardware timestamp, and the first hardware timestamp is associated with the message type, the sequence number, and the signal quality evaluation coefficient and stored in a dedicated register group inside the chip.

3. The chip-level hardware timestamp generation method based on the PTP protocol according to claim 2, characterized in that: In response to the received delay request message, a delay response message is generated and sent, and a sending timestamp is recorded at the MAC layer. Bidirectional transmission delay data is obtained by exchanging the delay request and delay response messages, and a clock deviation is calculated based on the first hardware timestamp and the bidirectional transmission delay data, including: After receiving the delay request message, calculating a reception time of the delay request message based on the first hardware timestamp; Generate a delay response message and record the sending time of the message with a MAC layer timestamp; Calculate the two-way transmission delay data based on the reception time of the delay request message and the sending time of the delay response message; Extract the master clock sending time from the synchronization message, and calculate the one-way delay data of the message transmission according to the first hardware timestamp and the master clock sending time; The clock deviation between the master and slave clocks is calculated based on the one-way delay data and the two-way transmission delay data.

4. The chip-level hardware timestamp generation method based on the PTP protocol according to claim 2, characterized in that: Based on the clock deviation, the local clock frequency is adjusted through the digitally controlled oscillator inside the chip to synchronize the local clock with the master clock, including: converting the calculated clock deviation into a digital control signal for a digitally controlled oscillator; Writing a digital control signal into a configuration register of a digitally controlled oscillator via an internal bus of the chip, and adjusting the local clock frequency in the configuration register based on the digital control signal; The system detects the stability of the adjusted clock in real time and provides feedback on the correction margin. When the correction margin meets the preset threshold, the local clock synchronization is completed.

5. The chip-level hardware timestamp generation method based on the PTP protocol according to claim 2, characterized in that: After synchronization is completed, when the chip receives a data message that needs to be timestamped, it records the second hardware timestamp when the message passes through the MAC layer, associates the second hardware timestamp with the corresponding data message, and stores the associated data in the buffer inside the chip, including: Detecting the arrival and sending events of MAC layer data messages, and recording a second hardware timestamp for messages in the arrival and sending events that meet the preset timestamp marking conditions; The ID of the message that meets the preset timestamp marking condition is associated with the second hardware timestamp and stored in the corresponding buffer inside the chip, and the second hardware timestamp and the message that meets the preset timestamp marking condition are batch transferred to the memory through the hardware DMA mechanism.

6. The chip-level hardware timestamp generation method based on the PTP protocol according to claim 5, characterized in that: Messages that meet the preset timestamp marking conditions include: messages whose protocol field contains the PTP timestamp request flag, messages with specific source MAC addresses configured by the user, monitoring messages generated by internal modules of the chip that require high-precision timestamps, key control messages that require time synchronization by network management protocols, and priority messages with time-sensitive network markings.

7. The chip-level hardware timestamp generation method based on the PTP protocol according to claim 2, characterized in that: The chip's built-in timestamp processing unit converts the timestamp data in the buffer into a format and calibrates its accuracy to generate standardized timestamp information, which is then output through the chip interface. This includes: The chip's built-in timestamp processing unit reads the original timestamp data from the buffer and converts the nanosecond timestamp into the second standard format. The clock drift compensation algorithm is applied to correct the accumulated error after synchronization, and the abnormal timestamps are processed by median filtering to obtain the standardized timestamp information; The standardized timestamp information is output to the host system through the chip interface.

8. The chip-level hardware timestamp generation method based on the PTP protocol according to claim 7, characterized in that: Apply the clock drift compensation algorithm to correct the accumulated error after synchronization, and perform median filtering on abnormal timestamps to obtain standardized timestamp information, including: Collect timestamp deviation samples within a preset time window to form a timestamp deviation sequence; The clock drift slope prediction value is calculated based on the least squares method fitting the timestamp deviation sequence; Generate a timestamp compensation coefficient based on the clock drift slope prediction value to compensate the timestamp data; The sliding window median filter algorithm is used to eliminate the pulse-type outliers in the timestamp deviation sequence; Convert the compensated timestamp data to the preset standard time format.

9. The chip-level hardware timestamp generation method based on the PTP protocol according to claim 8, characterized in that: Based on the least squares method to fit the timestamp deviation sequence, the clock drift slope prediction value is calculated, including: A linear regression model of timestamp deviation and time variable is established, and the slope parameter of the linear regression model is solved as the predicted value of clock drift slope.

10. A chip-level hardware-based timestamp generation system based on the PTP protocol, used to implement the chip-level hardware-based timestamp generation method based on the PTP protocol as described in any one of claims 1 to 9, characterized in that: include: Physical layer timestamp capture module: Receives synchronization messages and delay request messages from the master clock through the chip's built-in PTP protocol stack, and records the first hardware timestamp at the instant the synchronization message and delay request message reach the physical layer interface's physical layer signal transition edge; Two-way delay calculation module: In response to the received delay request message, it generates and sends a delay response message and records the sending timestamp at the MAC layer. It obtains two-way transmission delay data by exchanging delay request and delay response messages, and calculates the clock deviation by combining the first hardware timestamp and the two-way transmission delay data. Clock synchronization control module: According to the clock deviation, the local clock frequency is adjusted through the digital controlled oscillator inside the chip to synchronize the local clock with the master clock; MAC layer timestamp module: After synchronization is completed, when the chip receives a data message that needs to be timestamped, it records the second hardware timestamp when the message passes through the MAC layer, associates the second hardware timestamp with the corresponding data message, and stores the associated data in the buffer inside the chip; Timestamp standardization output module: Through the chip's built-in hardware timestamp processing unit, the timestamp data in the buffer is format converted and the accuracy is calibrated to generate standardized timestamp information, which is then output through the chip interface.

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