Radio frequency synchronization signal circuit and synchronization method

Abstract

The invention discloses a radio frequency synchronization signal circuit and a synchronization method, belongs to the technical field of wireless communication, and solves the problem that the existing equipment with a full-integration self-calibration function is difficult to meet the requirements of miniaturization, low cost and wide frequency range synchronization. The system comprises a radio frequency synchronization signal source, and the radio frequency synchronization signal source comprises a phase detection circuit, an FPGA circuit, a DAC circuit, a radio frequency circuit and an output port which are connected in sequence. The input end of the phase detection circuit is respectively connected in parallel with a first frequency divider circuit and a second frequency divider circuit which are symmetrically arranged. According to the full-integrated circuit and the automatic synchronization method of the radio frequency synchronization signal source, miniaturization, low cost, wide frequency range and high-precision synchronization are achieved, port-to-port synchronous output of multi-channel radio frequency signals is achieved, dependence of external equipment is eliminated, and cable phase deviation is compensated.

Description

Technical Field

[0001] The present invention relates to the technical field of wireless communications, and in particular to a radio frequency synchronization signal circuit and a synchronization method. Background Art

[0002] In modern wireless communications and testing technologies, high-precision, synchronized output of multi-channel RF signals is a core requirement for ensuring system performance. Traditional solutions rely on external calibration instruments (such as network analyzers and phase-locked loop modules) and complex cable connections. Phase error compensation is achieved through periodic reference signal injection or manual calibration, resulting in the following drawbacks: High cost: External high-precision instruments account for 30%-50% of the system cost and require additional configuration of modules such as frequency dividers and temperature-controlled crystal oscillators.

[0003] Bulky size: The cascaded cables, fixtures, and external devices of multiple devices cause the system size and weight to increase dramatically, making it difficult to meet the needs of mobile scenarios.

[0004] Poor frequency adaptability: Existing phase detection chips have a bandwidth of only a few GHz and cannot directly measure higher frequency RF signals. In addition, the asymmetric circuit design introduces phase errors such as temperature drift and routing delay. Summary of the Invention

[0005] In response to the above problems in the prior art, the present invention provides a radio frequency synchronization signal circuit and synchronization method, which solves the problem that existing devices with fully integrated self-calibration functions are difficult to meet the requirements of miniaturization, low cost and wide frequency range synchronization.

[0006] In order to achieve the above object, the technical solution adopted by the present invention is as follows: On the one hand, a radio frequency synchronization signal circuit is provided, including a radio frequency synchronization signal source, the radio frequency synchronization signal source including a phase detection circuit, an FPGA circuit, a DAC circuit, a radio frequency circuit and an output port connected in sequence; the input end of the phase detection circuit is respectively connected in parallel with two symmetrically arranged first frequency divider circuits and second frequency divider circuits, the input ends of the first frequency divider circuit and the second frequency divider circuit are respectively electrically connected to a first synchronization port and a second synchronization port, the first synchronization port is electrically connected to the output port, and the second synchronization port is electrically connected to an external radio frequency signal source.

[0007] In this solution, by symmetrically arranging the first and second divider circuits, high-frequency RF signals are converted into low-frequency signals detectable by the phase detection circuit, thereby covering a wider RF band and expanding the frequency adaptability range. Simultaneously, the FPGA circuit's built-in synchronization control algorithm enables real-time adjustment of signal frequency and phase, as well as processing and feedback control of phase detection data. The DAC circuit can generate an analog voltage based on the control signal output by the FPGA, adjusting the output phase of the RF circuit. Thus, the FPGA and DAC circuits can synchronize the RF synchronization signal source with the high-frequency signal of an external RF signal source, achieving a fully integrated self-calibration function and reducing reliance on external calibration instruments (such as network analyzers or phase-locked loop modules), thereby significantly reducing system costs. Furthermore, the FPGA and DAC circuits are compact, easy to integrate, and support miniaturized designs.

[0008] Furthermore, multiple RF synchronization signal sources are connected in series, with two adjacent RF synchronization signal sources acting as the master and slave, respectively. The output port of the master is signal-connected to the second synchronization port of the slave. A pairwise synchronization strategy can be employed between the RF synchronization signal sources. First, two devices are calibrated by establishing a master-slave relationship through their first and second synchronization ports. The calibrated master is then cascaded to other slaves, creating a multi-channel synchronization network.

[0009] Furthermore, cable clamps are provided on the connection cable between the output port of the master and the second synchronization port of the slave, and on the connection cable between the first synchronization port of the slave and the output port of the slave. The cable clamps ensure the mechanical stability and electrical consistency of the connecting cables, expanding their use cases. Furthermore, the circuitry of the RF synchronization signal source calibrates errors caused by cable differences, achieving port-to-port signal synchronization.

[0010] On the other hand, a synchronization method of a radio frequency synchronization signal circuit is provided, comprising the following steps: A1, respectively, generates a divided signal S2 and a divided signal S4 by passing the output signal S1 of the external RF signal source and the output signal S3 of the first synchronization port of the RF synchronization signal source through the second frequency divider circuit and the first frequency divider circuit; A2. Receive the voltage quantization value output by the phase detection circuit in real time through the FPGA circuit, and calculate the phase difference between the detection frequency division signal S2 and the frequency division signal S4. ; A3, through FPGA circuit and DAC circuit Adjust to the optimal detection range of the phase detection circuit; A4. Calculate the original phase difference between the output signal S1 and the output signal S3 through the FPGA circuit and the DAC circuit. , achieving phase synchronization of the output signal S1 and the output signal S3.

[0011] In this solution, indirect and precise synchronization of high-frequency RF signals is achieved through frequency division and phase difference adjustment, overcoming the limitations of direct measurement of high-frequency signals and expanding the frequency range. The FPGA circuit and DAC circuit cooperate to achieve port-to-port synchronous output of multi-channel RF signals, eliminating dependence on external devices and compensating for cable phase offsets. At the same time, an automated synchronization process is implemented, significantly reducing operating costs and time overhead.

[0012] Furthermore, step A3 includes: A31. Judgment Is it in the optimal detection range? If so, go to step A4, otherwise go to the next step; A32. Within 100 / M cycles, the DDS control word M% is increased by the DDS controller in the FPGA circuit to adjust the output frequency cycle of the FPGA circuit. ; Where M is the set value, and , is an integer and the number of A33. Calculate and adjust time offset ;

[0013] in, is the period of the output signal S1; A34, will Convert to angular phase adjustment ; ; ;in, is the period of the frequency division signal S2; N is the frequency division ratio, , is the operating frequency range of the phase detection circuit, is the frequency of the output signal S1; A35, will As a control signal input to the DAC circuit, the phase of the frequency division signal S4 is changed to make Close to the optimal detection interval; A36. Return to step A31.

[0014] In this plan, It is the execution core of the synchronization algorithm, and its function is to offset the time Convert it into an operational phase angle and directly control the RF circuit through the DAC circuit to make The system quickly converges to the optimal detection interval of the phase detection circuit. And this scheme limits the number of operation cycles. Changing the cycle by changing the DDS control word in a cycle will not affect the original cycle in subsequent cycles. Make changes.

[0015] Furthermore, in step A4, the original phase difference is calculated The steps include: A41, according to calculate The corresponding frequency division signal time difference , .

[0016] A42, according to calculate The corresponding original signal time difference , , where m is an integer, , mod is the modulo operation.

[0017] A43, according to Get calculated , .

[0018] In this solution, the distortion introduced by frequency division is compensated through the time difference conversion mechanism, ensuring that the synchronization result truly reflects the original signal state and improving the system reliability.

[0019] Furthermore, the phase detection circuit uses the AD8302 phase detector, with the optimal detection range being -120° to -60° and 60° to 120°. The AD8302 phase detector is a mature device with high cost-effectiveness and easy integration without adding additional design complexity. Furthermore, the frequency division link delays of the frequency division signal S2 and the frequency division signal S4 are equal, thereby eliminating the phase error introduced by the inconsistent frequency division link delays, ensuring the fairness of the frequency division signal comparison, and improving the synchronization accuracy.

[0020] The present invention discloses a radio frequency synchronization signal circuit and synchronization method, which have the following beneficial effects: The present invention achieves miniaturization, low cost, wide frequency range and high-precision synchronization through a fully integrated circuit of the RF synchronization signal source and an automated synchronization method, realizes port-to-port synchronous output of multi-channel RF signals, eliminates dependence on external devices and compensates for cable phase offset. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a connection diagram of the radio frequency synchronization signal circuit; Figure 2 Schematic diagram of signal frequency division; DETAILED DESCRIPTION The specific embodiments of the present invention are described below to facilitate understanding of the present invention by those skilled in the art. However, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those skilled in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the appended claims, these changes are obvious, and all inventions and creations utilizing the concepts of the present invention are protected.

[0022] Example 1 This embodiment provides a radio frequency synchronization signal circuit for solving the problem that existing devices with fully integrated self-calibration functions are difficult to meet the requirements of miniaturization, low cost and wide frequency range synchronization. It is described in detail below.

[0023] refer to Figure 1 A radio frequency synchronization signal circuit includes a radio frequency synchronization signal source, which includes a phase detection circuit, an FPGA circuit, a DAC circuit, a radio frequency circuit and an output port connected in sequence.

[0024] Specifically, the FPGA circuit is used to implement a built-in synchronization control algorithm to achieve real-time adjustment of signal frequency and phase, as well as processing and feedback control of phase detection data.

[0025] Specifically, the DAC circuit generates an analog voltage based on the control signal output by the FPGA circuit, adjusting the output phase of the RF circuit. The FPGA and DAC circuits work together to synchronize the RF synchronization signal source with the high-frequency signal of an external RF signal source, enabling fully integrated self-calibration. This reduces reliance on external calibration instruments (such as network analyzers or phase-locked loop modules), significantly reducing system costs. Furthermore, the FPGA and DAC circuits are compact and easy to integrate, supporting miniaturized designs.

[0026] Specifically, the radio frequency circuit is used to generate a radio frequency signal of a target frequency and output it through an output port.

[0027] The input end of the phase detection circuit is connected in parallel with two symmetrically arranged first and second frequency divider circuits. By symmetrically arranging the first and second frequency divider circuits, the high-frequency RF signal is converted into a low-frequency signal that can be detected by the phase detection circuit, which can cover a wider RF frequency band and expand the frequency adaptation range. Input ends of the first frequency divider circuit and the second frequency divider circuit are electrically connected to the first synchronization port and the second synchronization port respectively. The first synchronization port is electrically connected to the output port, and the second synchronization port is electrically connected to an external radio frequency signal source.

[0028] In order to build a multi-channel synchronization network, a pairwise synchronization strategy is adopted. Multiple RF synchronization signal sources can be connected in series in sequence, where two adjacent RF synchronization signal sources serve as the master and slave respectively, and the output port in the master is signal-connected to the second synchronization port of the slave.

[0029] Preferably, to expand usage scenarios, cable clamps can be provided on both the connection line between the output port of the master and the second synchronization port of the slave, and the connection line between the first synchronization port of the slave and the output port of the slave. Errors caused by cable differences are calibrated by the circuit of the RF synchronization signal source to achieve port-to-port signal synchronization.

[0030] Preferably, the phase detection circuit uses an AD8302 phase detector to detect the phase difference between the divided host and slave signals, output a voltage signal representing the phase difference, and transmit it to the FPGA circuit after ADC sampling.

[0031] Example 2 This embodiment is further limited on the basis of the embodiment 1. The specific improvement lies in providing a synchronization method of a radio frequency synchronization signal circuit. For other parts not mentioned, refer to the embodiment 1 or the prior art.

[0032] This embodiment provides a synchronization method for a radio frequency synchronization signal circuit, including the following steps: A1. Reference Figure 2 , the output signal S1 of the external RF signal source and the output signal S3 of the first synchronization port of the RF synchronization signal source are respectively passed through the second frequency divider circuit and the first frequency divider circuit to generate the divided signal S2 and the divided signal S4 respectively. Among them, the divided signal S2 and the divided signal S4 frequency link delay are respectively and ,in, Eliminate the phase error introduced by the inconsistent delay of the frequency division link, ensure the fairness of the frequency division signal comparison, and improve the synchronization accuracy.

[0033] A2. Receive the voltage quantization value output by the phase detection circuit in real time through the FPGA circuit, and calculate the phase difference between the detection frequency division signal S2 and the frequency division signal S4. .

[0034] A3, through FPGA circuit and DAC circuit Adjust to the optimal detection range of the phase detection circuit.

[0035] Step A3 includes: A31. Judgment Is it in the optimal detection interval? If so, go to step A4, otherwise go to the next step.

[0036] A32. Within 100 / M cycles, the DDS control word M% is increased by the DDS controller in the FPGA circuit to adjust the output frequency cycle of the FPGA circuit. ; Where M is the set value, and , is an integer. Preferably, the range of M is 1 / 1000 to 1 / 10000. By limiting the number of operation cycles, the change of the DDS control word only occurs when If the adjustment exceeds this range within a cycle, stop adjusting immediately to ensure stability.

[0037] A33. Calculate and adjust time offset ;

[0038] in, is the period of the output signal S1.

[0039] A34, will Convert to angular phase adjustment ; ; ;in, is the period of the frequency division signal S2; N is the frequency division ratio, , is the operating frequency range of the phase detection circuit, is the frequency of the output signal S1. It is the execution core of the synchronization algorithm, and its function is to offset the time Convert it into an operational phase angle and directly control the RF circuit through the DAC circuit to make Rapidly converge to the optimal detection interval of the phase detection circuit.

[0040] A35, will As a control signal input to the DAC circuit, the phase of the frequency division signal S4 is changed to make Close to the optimal detection range.

[0041] A36. Return to step A31.

[0042] A4. Calculate the original phase difference between the output signal S1 and the output signal S3 through the FPGA circuit and the DAC circuit. , achieving phase synchronization of the output signal S1 and the output signal S3.

[0043] Calculate the original phase difference in step A4 The steps include: A41, according to calculate The corresponding frequency division signal time difference , .

[0044] A42, according to calculate The corresponding original signal time difference , , where m is an integer, , mod is the modulo operation.

[0045] A43, according to Get calculated , At the same time, the time difference conversion mechanism is used to compensate for the distortion introduced by frequency division, ensuring that the synchronization result truly reflects the original signal state and improving the system reliability.

[0046] In summary, this solution achieves indirect and precise synchronization of high-frequency RF signals through frequency division and phase difference adjustment, overcoming the limitations of directly measuring high-frequency signals and expanding the frequency range. The FPGA circuit and DAC circuit cooperate to achieve port-to-port synchronous output of multi-channel RF signals, eliminating dependence on external devices and compensating for cable phase offsets. It also implements an automated synchronization process, significantly reducing operating costs and time overhead.

[0047] Although the specific embodiments of the invention are described in detail in conjunction with the accompanying drawings, this should not be construed as limiting the scope of protection of this patent. Within the scope described by the claims, various modifications and variations that can be made by those skilled in the art without creative work still fall within the scope of protection of this patent.

Claims

1. A radio frequency synchronization signal circuit, characterized in that: The radio frequency synchronization signal source includes a phase detection circuit, an FPGA circuit, a DAC circuit, a radio frequency circuit and an output port connected in sequence; The input end of the phase detection circuit is respectively connected in parallel with two symmetrically arranged first frequency divider circuits and second frequency divider circuits, the input ends of the first frequency divider circuit and the second frequency divider circuit are respectively electrically connected to a first synchronization port and a second synchronization port, the first synchronization port is electrically connected to the output port, and the second synchronization port is electrically connected to an external RF signal source.

2. The radio frequency synchronization signal circuit according to claim 1, wherein: The plurality of radio frequency synchronization signal sources are sequentially connected in series, wherein two adjacent radio frequency synchronization signal sources serve as a master and a slave respectively, and the output port of the master is signal-connected to the second synchronization port of the slave.

3. The radio frequency synchronization signal circuit according to claim 2, wherein: A cable clamp is provided on a connecting line between the output port of the host and the second synchronization port of the slave and a connecting line between the first synchronization port of the slave and the output port of the slave.

4. The synchronization method of the radio frequency synchronization signal circuit according to claim 1, characterized in that: The following steps are involved: A1, respectively, generates a divided signal S2 and a divided signal S4 by passing the output signal S1 of the external RF signal source and the output signal S3 of the first synchronization port of the RF synchronization signal source through the second frequency divider circuit and the first frequency divider circuit; A2. Receive the voltage quantization value output by the phase detection circuit in real time through the FPGA circuit, and calculate the phase difference between the detection frequency division signal S2 and the frequency division signal S4. ; A3, through FPGA circuit and DAC circuit Adjust to the optimal detection range of the phase detection circuit; A4. Calculate the original phase difference between the output signal S1 and the output signal S3 through the FPGA circuit and the DAC circuit. , achieving phase synchronization of the output signal S1 and the output signal S3.

5. The synchronization method of the radio frequency synchronization signal circuit according to claim 4, characterized in that: Step A3 includes: A31. Judgment Is it in the optimal detection range? If so, go to step A4, otherwise go to the next step; A32. Within 100 / M cycles, the DDS control word M% is increased by the DDS controller in the FPGA circuit to adjust the output frequency cycle of the FPGA circuit. ; Where M is the set value, and , is an integer and the number of A33. Calculate and adjust time offset ; in, is the period of the output signal S1; A34, will Convert to angular phase adjustment ; in, is the period of the frequency division signal S2; N is the frequency division ratio, , is the operating frequency range of the phase detection circuit, is the frequency of the output signal S1; A35, will As a control signal input to the DAC circuit, the phase of the frequency division signal S4 is changed to make Close to the optimal detection interval; A36. Return to step A31.

6. The synchronization method of the radio frequency synchronization signal circuit according to claim 5, characterized in that: Calculate the original phase difference in step A4 The steps include: A41, according to calculate The corresponding frequency division signal time difference , ; A42, according to calculate The corresponding original signal time difference , , where m is an integer, ;mod is the modulo operation; A43, according to Get calculated , .

7. The synchronization method of the radio frequency synchronization signal circuit according to claim 5, characterized in that: The phase detection circuit uses the AD8302 phase detector, and the optimal detection range is -120°~-60° and 60°~120°.

8. The synchronization method of the radio frequency synchronization signal circuit according to claim 5, characterized in that: The frequency division link delays of the frequency division signal S2 and the frequency division signal S4 are equal.

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