Printed circuit board

Abstract

The present disclosure relates to a printed circuit board including: a first insulating layer; the through via hole penetrates through at least one part of a region between the upper surface and the lower surface of the first insulating layer and is provided with one or more gap parts; the one or more gap parts separate at least one part of one or more of the side surfaces of the upper part and / or the lower part of the through via hole from the first insulating layer; and a second insulating layer disposed on the first insulating layer, covering at least a portion of one or more of the side surface of the upper portion and / or the side surface of the lower portion of the through via, and filling at least a portion of each of the one or more gap portions.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2024-0029618 filed on February 29, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present disclosure relates to a printed circuit board. Background Art

[0003] Recently, large-area, highly stacked multilayer structures and miniaturization have become indispensable for the high performance of package substrates. In addition, copper-clad laminates (CCLs) are generally used as core substrates included in package substrates. However, in the case of CCLs, warping may occur due to low modulus and high thermal expansion coefficient, and there are limitations in realizing microcircuits. Therefore, warping can be suppressed by having a high modulus and a low thermal expansion coefficient. In addition, core substrates including new materials such as inorganic materials are needed, which allow for easier realization of microcircuits due to their smooth surfaces. However, in the case of core substrates including inorganic materials, when forming through vias, some defects may occur at the entrance portions of the upper and lower ends during the processing of the through vias, which may be the starting point of cracks after productization. Summary of the Invention

[0004] An aspect of the present disclosure is to provide a printed circuit board that can prevent cracks from occurring due to thermal shock even when a through via is formed in a core layer including an inorganic material, such as a glass substrate.

[0005] One of the various solutions disclosed in the present disclosure is to provide a printed circuit board having a structure that is advantageous in preventing thermal shock from a stress perspective by forming one or more gap portions (spaces between the through-via and a core layer) on a side surface of an upper portion and / or a side surface of a lower portion of a through-via and filling the gap portions with an insulating material.

[0006] For example, a printed circuit board according to an example embodiment includes: a first insulating layer; a through via that penetrates at least a portion of an area between an upper surface and a lower surface of the first insulating layer and has one or more gap portions, the one or more gap portions respectively separating at least a portion of one or more of the upper side surface and / or the lower side surface of the through via from the first insulating layer; and a second insulating layer disposed on the first insulating layer, covering at least a portion of one or more of the upper side surface and / or the lower side surface of the through via, and filling at least a portion of each of the one or more gap portions.

[0007] For example, a printed circuit board according to an example embodiment includes: a glass substrate; a through hole extending between an upper surface and a lower surface of the glass substrate; a metal via filling at least a portion of the through hole; one or more gap portions respectively arranged between a side surface of an upper portion of the metal via and a wall surface of the through hole and between a side surface of a lower portion of the metal via and the wall surface of the through hole; and an insulating layer provided on the glass substrate and filling at least a portion of each of the one or more gap portions.

[0008] For example, a printed circuit board according to an example embodiment includes: a first insulating layer; a plurality of through vias arranged in a grid pattern, each through via penetrating the first insulating layer and having one or more gap portions, the one or more gap portions respectively separating at least a portion of one or more side surfaces of the through via from the first insulating layer; a second insulating layer disposed on the first insulating layer; and a conductive layer disposed on the second insulating layer and electrically connected to at least one of the through vias.

[0009] For example, a printed circuit board according to an example embodiment includes: a first insulating layer including an inorganic material; a through via penetrating the first insulating layer, wherein the through via includes an upper portion, a lower portion and a central portion, and wherein the upper portion and the lower portion of the through via are respectively recessed inward from the upper surface and the lower surface of the first insulating layer to form a dish shape or a pit; one or more gap portions, respectively separating at least a portion of the side surface of the upper portion and / or the lower portion of the through via from the first insulating layer; a second insulating layer disposed on the first insulating layer and filling at least a portion of the one or more gap portions; and an interconnect layer disposed on the second insulating layer and electrically connected to the through via.

[0010] For example, a printed circuit board according to an example embodiment includes: a frame having a through portion; a glass substrate at least partially disposed in the through portion; an insulating layer including a first insulating portion, a second insulating portion, and a filling portion, the first insulating portion covering at least a portion of each of an upper surface of the frame and an upper surface of the glass substrate, the second insulating portion covering at least a portion of each of a lower surface of the frame and a lower surface of the glass substrate, and the filling portion filling at least a portion of a space between the frame and the glass substrate in the through portion; a through via penetrating at least a portion of a space between the upper surface and the lower surface of the glass substrate; a first connecting via penetrating a portion of the first insulating portion and directly connected to an upper side of the through via; and a second connecting via penetrating a portion of the second insulating portion and directly connected to a lower side of the through via.

[0011] One of various effects of the present disclosure is to provide a printed circuit board that can prevent cracks from occurring due to thermal shock even when a through via is formed in a core layer including an inorganic material, such as a glass substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 is a block diagram schematically illustrating an example of an electronic device system; Figure 2 is a perspective view schematically showing an example of an electronic device; Figure 3 is a cross-sectional view schematically showing an example of a printed circuit board; Figure 4 It is schematically shown Figure 3 An enlarged cross-sectional view of a region A of a printed circuit board shown in FIG. Figure 5A and Figure 5B They are schematically shown along Figure 4 Plan views of various examples of an area A of a printed circuit board cut along line II'; 6A to 6I is a schematic diagram showing the fabrication Figure 3 A process cross-sectional view of an example of a printed circuit board shown in FIG; Figure 7 is a cross-sectional view schematically showing another example of a printed circuit board; and Figure 8 is a cross-sectional view schematically showing another example of a printed circuit board. DETAILED DESCRIPTION

[0013] Hereinafter, the present disclosure will be described with reference to the accompanying drawings. In the accompanying drawings, the shapes and sizes of elements may be exaggerated or reduced for clarity of description.

[0014] electronic devices Figure 1 is a block diagram schematically illustrating an example of an electronic device system.

[0015] Reference Figure 1 , a mainboard 1010 is housed in the electronic device 1000. Chip-related components 1020, network-related components 1030, and other components 1040 are physically and / or electrically connected to the mainboard 1010. These components are also connected to other electronic components described below via various signal lines 1090.

[0016] Chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory), etc.; application processor chips, such as central processing units (e.g., central processing units (CPUs)), graphics processors (e.g., graphics processing units (GPUs)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (ADCs) and application-specific integrated circuits (ASICs). However, chip-related components 1020 are not limited to these and may also include other types of chip-related components. Furthermore, chip-related components 1020 may be combined with one another. Chip-related components 1020 may be in the form of a package that includes the aforementioned chips.

[0017] The network-related components 1030 may include components that are compatible with or operate according to protocols such as: Wireless Fidelity (Wi-Fi) (such as the Institute of Electrical and Electronics Engineers (IEEE) 802.11 series), Worldwide Interoperability for Microwave Access (WiMAX) (such as the IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Evolution-Data Optimized (Ev-DO), High-Speed ​​Packet Access Plus (HSPA+), High-Speed ​​Downlink Packet Access Plus (HSDPA+), High-Speed ​​Uplink Packet Access Plus (HSUPA+), Global System for Mobile Communications (GSM), Enhanced Data Rates for GSM Evolution (EDGE), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Bluetooth, third generation mobile communication technology (3G) protocols, fourth generation mobile communication technology (4G) protocols, and fifth generation mobile communication technology (5G) protocols, as well as any other wireless standards or protocols and wired standards or protocols specified after the above protocols. However, the network-related components 1030 are not limited thereto and may also include components that are compatible with or operate according to any of a plurality of other wireless standards or protocols and wired standards or protocols. In addition, the network-related components 1030 may be combined with the chip-related components 1020 described above.

[0018] Other components 1040 may include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, low-temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCCs), and the like. However, other components 1040 are not limited thereto and may also include passive components in the form of chip components for various other purposes. Furthermore, other components 1040 may be combined with chip-related components 1020 and / or network-related components 1030.

[0019] Depending on the type of electronic device 1000, the electronic device 1000 may include other electronic components that may or may not be physically and / or electrically connected to the mainboard 1010. These other electronic components may include, for example, a camera 1050, an antenna 1060, a display 1070, and a battery 1080. However, these other electronic components are not limited thereto and may also include an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g., a hard drive), a compact disc (CD) drive, a digital versatile disc (DVD) drive, and the like. Furthermore, depending on the type of electronic device 1000, the electronic device 1000 may further include other electronic components for various purposes.

[0020] The electronic device 1000 may be a smartphone, a personal digital assistant, a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game console, a smart watch, or an automotive component. However, the electronic device 1000 is not limited thereto and may be any other electronic device capable of processing data.

[0021] Figure 2 is a perspective view schematically showing an example of an electronic device.

[0022] Reference Figure 2 The electronic device may be, for example, a smartphone 1100. A mainboard 1110 may be housed in smartphone 1100, and various components 1120 may be physically and / or electrically connected to mainboard 1110. Furthermore, other electronic components (such as a camera module 1130 and / or a speaker 1140) may be housed in smartphone 1100, either physically and / or electrically connected to mainboard 1110 or not. Some of components 1120 (e.g., component package 1121) may be the aforementioned chip-related components, but the present disclosure is not limited thereto. Component package 1121 may take the form of a printed circuit board on which electronic components (including active and / or passive components) are surface-mounted. Alternatively, component package 1121 may take the form of a printed circuit board in which electronic components (including active and / or passive components) are embedded. On the other hand, the electronic device is not necessarily limited to smartphone 1100 and may also be other electronic devices as described above.

[0023] printed circuit boards Figure 3 is a cross-sectional view schematically showing an example of a printed circuit board.

[0024] Figure 4 It is schematically shown Figure 3An enlarged cross-sectional view of a region A of a printed circuit board is shown in FIG.

[0025] Referring to the drawings, a printed circuit board 100A according to an example embodiment may include: a first insulating layer 111; a through-hole 135 extending through at least a portion of a region between an upper surface and a lower surface of the first insulating layer 111 and having one or more gaps G1 and / or G2 separating at least a portion of an upper side surface and / or a lower side surface from the first insulating layer 111; and a second insulating layer 112 disposed on the first insulating layer 111 and covering at least a portion of an upper portion and / or a lower portion of the through-hole 135 and filling at least a portion of each of the one or more gaps G1 and / or G2. For example, the second insulating layer 112 may be disposed on the upper and lower surfaces of the first insulating layer 111 to cover at least a portion of each of the upper and lower portions of the through-hole 135 and may fill at least a portion of each of the one or more first gaps G1 formed on the upper side surface of the through-hole 135 and the one or more second gaps G2 formed on the lower side surface of the through-hole 135. The upper portion of the through-hole 135 may include a portion of the through-hole 135 extending downward from an upper surface of the through-hole 135. The lower portion of the through-hole 135 may include another portion of the through-hole 135 extending upward from a lower surface of the through-hole 135.

[0026] In this manner, in the printed circuit board 100A according to the exemplary embodiment, one or more gaps G1 and / or G2, which are spaces between the first insulating layer 111 and the through-via 135, may be formed on the upper and / or lower side surfaces of the through-via 135 that penetrates the first insulating layer 111, and at least a portion of each of the one or more gaps G1 and G2 may be filled with the second insulating layer 112. Therefore, even when the first insulating layer 111 includes an inorganic material as a core layer (such as a glass substrate), the printed circuit board 100A may have a structure that facilitates thermal shock prevention in terms of stress. Consequently, cracks caused by thermal shock may be prevented from occurring.

[0027] For example, when a through-hole (TGV) is formed in a glass substrate, then filled with copper (Cu) plating to form a through-glass via (TGV), an insulating layer is stacked thereon, and a reflow process is performed from room temperature to approximately 260°C. Comparing the shrinkage stress applied to the upper and lower entrance portions of the TGV, the shrinkage stress can be significantly lower when a gap is formed and then filled with an insulating material, compared to when no gap is formed. More specifically, when gaps are formed on the upper and lower side surfaces of the Cu-filled TGV and then filled with an Ajinomoto deposited film (ABF) (Inventive Example 2) and when gaps are formed on the upper and lower side surfaces of the Cu-filled TGV and then filled with prepreg (PPG) (Inventive Example 3), the shrinkage stress ratios are approximately 1:0.02:0.11, respectively (Comparative Example 1: Inventive Example 2: Inventive Example 3). Therefore, cracks due to stress applied by thermal shock can be suppressed by the structure in which the gap portion is formed and then filled with an insulating material.

[0028] Furthermore, the upper and / or lower surfaces of the first insulating layer 111 may have a step difference relative to the upper and / or lower surfaces of the through-via 135. For example, the upper surface of the first insulating layer 111 may be positioned above the upper surface of the through-via 135, and the lower surface of the first insulating layer 111 may be positioned below the lower surface of the through-via 135. For example, the upper and lower surfaces of the through-via 135 may be recessed toward the interior of the through-via 135 relative to the upper and lower surfaces of the first insulating layer 111, respectively. At least a portion of the recessed space may also be filled with the second insulating layer 112. This structure may therefore be more advantageous for preventing thermal shock. Furthermore, the reliability of the through-via 135 may be further improved.

[0029] Furthermore, the first insulating layer 111 may include an inorganic insulating material. In another example, the first insulating layer 111 may include a glass substrate. For example, the first insulating layer 111 may include flat glass. However, the present disclosure is not limited thereto, and other materials besides glass substrates may be used as long as they can form one or more of the gaps G1 and G2 described above. On the other hand, the second insulating layer 112 may include an organic insulating material, and since the organic insulating material fills one or more of the gaps G1 and G2, it may be more advantageous from a stress perspective. The second insulating layer 112 may include a prepreg (PPG) or an Ajinomoto built-up film (ABF), but the present disclosure is not limited thereto, and the second insulating layer 112 may include other organic insulating materials.

[0030] Furthermore, the through-hole 135 may be a metal via 135 configured to fill at least a portion of a through-hole h extending between the upper and lower surfaces of the first insulating layer 111. One or more first gaps G1 may be formed between the side surface of the upper portion of the metal via 135 and the wall surface of the through-hole h, and one or more second gaps G2 may be formed between the side surface of the lower portion of the metal via 135 and the wall surface of the through-hole h. The metal via 135 may include a seed layer m1 disposed on a portion of the wall surface of the through-hole h and a metal layer m2 filling at least a portion of the through-hole h. The one or more first gaps G1 and at least a portion of the one or more second gaps G2 may be disposed in another portion of the wall surface of the through-hole h, for example, between a portion of the wall surface of the through-hole h on which the seed layer m1 is not formed and the side surface of the metal layer m2. In some areas where one or more first gaps G1 and one or more second gaps G2 are formed, a portion of the seed layer m1 may be separated from the wall surface of the through-hole h and may remain on the side surface of the metal layer m2. In this way, the metal via 135 can be formed by forming a seed layer in the through-hole h and then performing fill plating thereon. Then, when a portion of the seed layer and the fill plating layer are removed in a subsequent polishing process, one or more first gaps G1 and one or more second gaps G2 can be formed. In this case, the above-mentioned recessed space, such as a dish or pit, can also be formed. Based on this structure, a structure that is advantageous in terms of thermal stress can be achieved.

[0031] Furthermore, in the through-hole 135, the maximum width in each of the upper and lower portions of the through-hole 135 may be wider than the minimum width in the central portion between the upper and lower portions of the through-hole 135. Figure 3 and Figure 4 In a cross section along the thickness direction of the printed circuit board 100A, the maximum width in each of the upper and lower portions of the through-hole 135 may be greater than the minimum width in the central portion of the through-hole 135. For example, the through-hole h at least partially filled with the through-hole 135 may have a shape similar to an hourglass, and thus the through-hole 135 may have a structure approximately corresponding thereto. This structure may be more advantageous for stress distribution.

[0032] Furthermore, the printed circuit board 100A according to the exemplary embodiment may further include a frame 118 having a through-portion H. At least a portion of the first insulating layer 111 may be disposed within the through-portion H of the frame 118. The second insulating layer 112 may cover at least a portion of the frame 118 and may fill at least a portion of the through-portion H. The frame 118 may serve as a jig during processing, thereby providing advantages in terms of warpage control during processing. Furthermore, multiple through-portions H may be formed in the large-area frame 118. By utilizing these through-portions H, multiple printed circuit boards 100A may be manufactured through the same process and then separated during a cutting process, thereby improving production efficiency.

[0033] In addition, the printed circuit board 100A according to the example embodiment may further include: a first interconnection layer 121 disposed on the upper surface of the second insulating layer 112; a second interconnection layer 122 disposed on the lower surface of the second insulating layer 112; a first connection via 131 penetrating a portion of the second insulating layer 112 and connecting at least a portion of the first interconnection layer 121 to the upper surface of the through-via 135; and a second connection via 132 penetrating another portion of the second insulating layer 112 and connecting at least a portion of the second interconnection layer 122 to the lower surface of the through-via 135. The first connection via 131 and the second connection via 132 may be directly connected to the upper surface and the lower surface of the through-via 135, respectively. The first connection via 131 and the second connection via 132 may be tapered in opposite directions. For example, referring to Figure 3 and Figure 4 In a cross-section of printed circuit board 100A along the thickness direction, first connection via 131 and second connection via 132 may taper downward and upward, respectively. This structure allows second insulating layer 112 to more easily cover the upper and / or lower portions of through-hole 135 and fill one or more gaps G1 and / or G2. Consequently, a structure that facilitates stress protection against thermal shock can be easily achieved.

[0034] In addition, the printed circuit board 100A according to the example embodiment may include: a third insulating layer 113 disposed on the upper surface of the second insulating layer 112 and covering at least a portion of the first interconnection layer 121; a fourth insulating layer 114 disposed on the lower surface of the second insulating layer 112 and covering at least a portion of the second interconnection layer 122; a third interconnection layer 123 disposed on the upper surface of the third insulating layer 113; a fourth interconnection layer 124 disposed on the lower surface of the fourth insulating layer 114; and a third connection via 133 penetrating a portion of the third insulating layer 113 and connecting the first interconnection layer 121 to the third insulating layer 114. 121 and at least a portion of each of the third interconnection layer 123 are connected to each other; a fourth connection via 134 penetrates a portion of the fourth insulating layer 114 and connects at least a portion of each of the second interconnection layer 122 and the fourth interconnection layer 124 to each other; a first resist layer 115 is provided on the upper surface of the third insulating layer 113 and has a first opening o1 exposing at least a portion of the third interconnection layer 123; and a second resist layer 116 is provided on the lower surface of the fourth insulating layer 114 and has a second opening o2 exposing at least a portion of the fourth interconnection layer 124. The third connection via 133 and the fourth connection via 134 may be tapered in opposite directions. For example, referring to Figure 3 and Figure 4 In a cross section of the printed circuit board 100A along the thickness direction, the third connection via 133 and the fourth connection via 134 may taper downward and upward, respectively. For example, the printed circuit board 100A according to the exemplary embodiment may have a multilayer printed circuit board structure. Thus, the printed circuit board 100A may be used as a flip chip board (FCB), a ball grid array (BGA), an interposer, a package board, etc. However, the present disclosure is not limited thereto and may be applied to various other types of boards.

[0035] Hereinafter, components of the printed circuit board 100A according to example embodiments will be described in more detail with reference to the accompanying drawings.

[0036] The first insulating layer 111 may include a glass substrate. The glass substrate may include glass that is an amorphous solid. Glass may include, for example, pure silica (approximately 100% SiO2), soda-lime glass, borosilicate glass, and aluminosilicate glass. However, the present disclosure is not limited thereto, and alternative glass materials such as fluoride glass, phosphate glass, and chalcogenide glass may also be used. Furthermore, other additives may be included to impart specific physical properties to the glass. These additives may include calcium carbonate (e.g., lime) and sodium carbonate (e.g., soda), as well as magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, and antimony, and their carbonates and / or oxides. The glass substrate may be different from organic insulating materials (e.g., copper-clad laminate (CCL), prepreg (PPG), etc.) that include glass fibers (e.g., glass fabric, such as glass cloth). For example, the glass substrate may include flat glass. However, the present disclosure is not limited thereto, and other materials besides a glass substrate may be used as long as they can form one or more of the gaps G1 and G2 described above. For example, a silicon substrate, a ceramic substrate, etc. may also be considered as a material for the first insulating layer 111 .

[0037] Each of the second insulating layer 112, the third insulating layer 113, the fourth insulating layer 114, the first resist layer 115, and the second resist layer 116 may include an organic insulating material. The organic insulating material may include a thermosetting resin (such as epoxy resin), a thermoplastic resin (such as polyimide), or a material prepared by impregnating a core material (such as glass fiber (for example, glass fabric, for example, glass cloth)) with a thermosetting resin or thermoplastic resin along with an inorganic filler. For example, the organic insulating material may be prepreg (PPG), Ajinomoto built-up film (ABF), photosensitive dielectric (PID), solder resist (SR), etc., but the present disclosure is not limited thereto. If desired, each of the second insulating layer 112, the third insulating layer 113, the fourth insulating layer 114, the first resist layer 115, and the second resist layer 116 may be formed using multiple layers. The first resist layer 115 and the second resist layer 116 may have a first opening o1 and a second opening o2, respectively, and each of the first opening o1 and the second opening o2 may be provided in plural. The pad pattern of each of the third interconnection layer 123 and the fourth interconnection layer 124 exposed through the first opening o1 and the second opening o2, respectively, may be in the form of solder mask definition (SMD) and / or non-solder mask definition (NSMD).

[0038] The frame 118 may be made of various materials. For example, the frame 118 may be made of an organic insulating material, such as a copper-clad laminate (CCL). Alternatively, the frame 118 may be made of an inorganic insulating material, such as silicon or ceramic. Alternatively, the frame 118 may be made of a metal, such as copper (Cu). The present disclosure is not limited thereto. The frame 118 may have a through-portion H. The through-portion H may extend between the upper and lower surfaces of the frame 118. The through-portion H may have a shape corresponding to the first insulating layer 111. If desired, the through-portion H may be formed in the form of a blind cavity. The through-portion H may continuously surround the side surface of the first insulating layer 111. For example, in a plan view, the through-portion H may have an approximately quadrilateral shape. If desired, the frame 118 may be formed using multiple units, and the number of the multiple units is not particularly limited.

[0039] Each of the first interconnect layer 121, the second interconnect layer 122, the third interconnect layer 123, and the fourth interconnect layer 124 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. The metal may preferably include copper (Cu), but the present disclosure is not limited thereto. Each of the first interconnect layer 121, the second interconnect layer 122, the third interconnect layer 123, and the fourth interconnect layer 124 may perform various functions depending on the design. For example, the first interconnect layer 121, the second interconnect layer 122, the third interconnect layer 123, and the fourth interconnect layer 124 may include signal patterns, power patterns, and ground patterns. These patterns may each have various shapes, such as lines, planes, and pads. Each of the first interconnect layer 121, the second interconnect layer 122, the third interconnect layer 123, and the fourth interconnect layer 124 may include a seed layer and a plating layer. The seed layer can be formed by electroless plating (or chemical copper plating), and if necessary, can be formed by sputtering. Alternatively, the first interconnect layer 121, the second interconnect layer 122, the third interconnect layer 123, and the fourth interconnect layer 124 can be formed using both electroless plating and sputtering processes. The plated layer can be formed by electrolytic plating (or electrolytic copper). When each of the second insulating layer 112, the third insulating layer 113, and the fourth insulating layer 114 is formed using multiple layers, the first interconnect layer 121, the second interconnect layer 122, the third interconnect layer 123, and the fourth interconnect layer 124 can also be formed using multiple layers. The first interconnect layer 121, the second interconnect layer 122, the third interconnect layer 123, and the fourth interconnect layer 124 can protrude above the second insulating layer 112, the third insulating layer 113, and the fourth insulating layer 114, respectively, but can also be embedded in the second insulating layer 112, the third insulating layer 113, and the fourth insulating layer 114, respectively.

[0040] Each of the first connection via 131, the second connection via 132, the third connection via 133, and the fourth connection via 134 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. The metal may preferably include copper (Cu), but the present disclosure is not limited thereto. Each of the first connection via 131, the second connection via 132, the third connection via 133, and the fourth connection via 134 may perform various functions depending on the design. For example, the first connection via 131, the second connection via 132, the third connection via 133, and the fourth connection via 134 may include a signal via, a power via, and a ground via. Each of the first connection via 131, the second connection via 132, the third connection via 133, and the fourth connection via 134 may include a filled via in which a via hole is filled with metal, but may also include a conformal via in which metal is provided along a wall surface of the via hole. Each of the first connection via 131, the second connection via 132, the third connection via 133, and the fourth connection via 134 may have a tapered shape. For example, referring to Figure 3 and Figure 4 In a cross-section of the printed circuit board 100A along the thickness direction, each of the first connection via 131, the second connection via 132, the third connection via 133, and the fourth connection via 134 may have a tapered shape along the thickness direction. For example, the first connection via 131 and the third connection via 133 may be configured so that the width of their upper ends in the cross-section is wider than the width of their lower ends, and the second connection via 132 and the fourth connection via 134 may be configured so that the width of their upper ends in the cross-section is narrower than the width of their lower ends. Each of the first connection via 131, the second connection via 132, the third connection via 133, and the fourth connection via 134 may include the same seed layer and plating layer as those included in the first interconnect layer 121, the second interconnect layer 122, the third interconnect layer 123, and the fourth interconnect layer 124. The first connection via 131 , the second connection via 132 , the third connection via 133 , and the fourth connection via 134 may each be provided in plural.

[0041] The through via 135 may comprise a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. The metal may preferably include copper (Cu), but the present disclosure is not limited thereto. The through via 135 may include a metal via 135 that fills at least a portion of the through hole h. The metal via 135 may perform various functions depending on the design. For example, the through via 135 may include a signal via, a power via, and a ground via. One or more first gaps G1 may be formed between the side surface of the upper portion of the metal via 135 and the wall surface of the through hole h, and one or more second gaps G2 may be formed between the side surface of the lower portion of the metal via 135 and the wall surface of the through hole h. The metal via 135 may include a seed layer m1 disposed on a portion of the wall surface of the through hole h and a metal layer m2 that fills at least a portion of the through hole h. One or more first gaps G1 and second gaps G2 may be provided between another portion of the through-hole h (e.g., a portion where the seed layer m1 is not formed) and the side surface of the metal layer m2. For example, the metal via 135 may be formed by forming a seed layer in the through-hole h and then performing fill plating. When a portion of the seed layer and a portion of the fill plating layer are removed during a subsequent polishing process, the one or more first gaps G1 and one or more second gaps G2 may be formed. Furthermore, a recessed space, such as a dished or pit-shaped space, may be formed. Multiple metal vias 135 may be provided.

[0042] Figure 5A and Figure 5B They are schematically shown along Figure 4 1 and 2 are plan views of various examples of a region A of a printed circuit board cut along line II′.

[0043] Reference Figure 5A , the first gap portion G1 may be provided in a plurality. For example, the first gap portion G1 may include a first-first gap portion G1-1 and a first-second gap portion G1-2, which may be spaced apart from each other. The first-first gap portion G1-1 and the first-second gap portion G1-2 may have different sizes, for example, different widths, depths, etc. The first gap portion G1 may include a greater number of gap portions than those shown in the accompanying drawings. The above content may be applied to the second gap portion G2 in substantially the same manner. In this way, gap portions of various sizes may be formed at various locations, and gap portions of various sizes may be filled with insulating material, thereby increasing the degree of design freedom while achieving a structure that is conducive to preventing thermal shock.

[0044] Reference Figure 5BThe first gap portion G1 can be a single, continuous component. For example, the first gap portion G1 can include a first to third gap portion G1-3 that continuously surrounds the side surface of the upper portion of the through hole 135. The above description can also be applied to the second gap portion G2. In this way, the gap portion can be formed wider and continuously, thus achieving a structure that is conducive to preventing thermal shock.

[0045] 6A to 6I is a schematic diagram showing the fabrication Figure 3 is a process cross-sectional view of an example of a printed circuit board shown in .

[0046] Reference Figure 6A , a first insulating layer 111 may be prepared. The first insulating layer 111 may be a glass substrate such as flat glass as described above, but the present disclosure is not limited thereto. Next, a through hole h may be formed through the first insulating layer 111. Depending on the material of the first insulating layer 111, the through hole h may be formed using a chemical method or a mechanical method. For example, etching, sandblasting, laser, plasma, etc. may be used as a method for forming the through hole h.

[0047] Reference Figure 6B A seed layer m1 covering the through hole h and the first insulating layer 111 may be formed on the wall surface of the through hole h and the upper and lower surfaces of the first insulating layer 111. The seed layer m1 may be formed by electroless plating (or chemical copper plating), but the present disclosure is not limited thereto. If desired, the seed layer m1 may be formed in multiple layers.

[0048] Reference Figure 6C A metal layer m2 may be formed on the seed layer m1. The metal layer m2 may be formed by fill plating. The fill plating may be electrolytic plating (or electroplating), but the present disclosure is not limited thereto. The metal layer m2 may fill the through hole h and may also be formed on the upper and lower surfaces of the first insulating layer 111.

[0049] Reference Figure 6D At least a portion of the seed layer m1 and at least a portion of the metal layer m2 disposed on the upper and lower surfaces of the first insulating layer 111 may be removed. Furthermore, a through-via 135 and one or more first gaps G1 and one or more second gaps G2 may be formed. For example, a portion of the seed layer m1 and a portion of the metal layer m2 formed on the surface of the first insulating layer 111 may be removed during a polishing process such as chemical mechanical planarization (CMP), thereby forming the through-via 135. In this case, relatively more of the through-via 135 may be removed at the entrance portion of the upper and / or lower portion of the through-via 135 than at the first insulating layer 111, thereby forming the one or more first gaps G1 and / or second gaps G2. Furthermore, the upper and / or lower surfaces of the through-via 135 may be recessed inward as a whole, thereby forming a dished shape or a concave pit.

[0050] Reference Figure 6E , a frame 118 having a through-hole H can be prepared. Furthermore, a first insulating layer 111 having a through-hole 135 formed in the through-hole H of the frame 118 can be set using a tape 119. The frame 118 can be used as a jig. A plurality of through-holes H can be provided, and a first insulating layer 111 having a through-hole 135 formed in each through-hole H can be provided.

[0051] Reference Figure 6F , the second-first insulating layer 112-1 may be stacked on the upper sides of the frame 118 and the first insulating layer 111. In this case, one or more first gap portions G1 may be filled with the second-first insulating layer 112-1.

[0052] Reference Figure 6G , tape 119 may be removed. Alternatively, a second-second insulating layer 112-2 may be laminated on the underside of frame 118 and first insulating layer 111. In this case, one or more second gaps G2 may be filled with second-second insulating layer 112-2. Furthermore, after the curing process, second-first insulating layer 112-1 and second-second insulating layer 112-2 may be integrated to form second insulating layer 112.

[0053] Reference Figure 6H , first and second interconnect layers 121 and 122 may be formed on the upper and lower sides of the second insulating layer 112, respectively, and first and second connection vias 131 and 132 may be formed in the second insulating layer 112. For example, after machining via holes at desired locations in the second insulating layer 112 using a laser drill or the like, a circuit process such as via sealing (TT), an additive process (AP), a semi-additive process (SAP), or a modified semi-additive process (MSAP) may be performed to form the first and second interconnect layers 121 and 122 and the first and second connection vias 131 and 132.

[0054] Reference Figure 6I, a stacking process may be additionally performed. For example, the third insulating layer 113 and the fourth insulating layer 114 may be stacked on the upper and lower sides of the second insulating layer 112, respectively. Furthermore, using the above-described via hole forming process and circuit process, the third connection vias 133 and the fourth connection vias 134 may be formed in the third insulating layer 113 and the fourth insulating layer 114, respectively, and the third interconnection layer 123 and the fourth interconnection layer 124 may be formed on the third insulating layer 113 and the fourth insulating layer 114, respectively. Next, a first resist layer 115 and a second resist layer 116 may be formed on the third insulating layer 113 and the fourth insulating layer 114, respectively, and a photolithography process or a laser process may be used to form the first opening o1 and the second opening o2. Through a series of processes, the printed circuit board 100A according to the example embodiment may be manufactured.

[0055] Other descriptions may be substantially the same as those described in the printed circuit board 100A according to the above-described example embodiment, and thus, duplicate descriptions will be omitted.

[0056] Figure 7 is a cross-sectional view schematically showing another example of a printed circuit board.

[0057] Reference Figure 7 Compared to the printed circuit board 100A according to the above-described exemplary embodiment, a printed circuit board 100B according to another exemplary embodiment may further include a first electrical connection metal 151 and a second electrical connection metal 152. The first electrical connection metal 151 is disposed on the first opening o1 of the first resist layer 115 and connected to at least a portion of the exposed third interconnect layer 123. The second electrical connection metal 152 is disposed on the second opening o2 of the second resist layer 116 and connected to at least a portion of the exposed fourth interconnect layer 124. The first electrical connection metal 151 and the second electrical connection metal 152 may connect the printed circuit board 100B to another substrate, an electronic component, or the like. The first electrical connection metal 151 and the second electrical connection metal 152 may be formed using a conductive material such as solder, but this is merely an example and the materials are not particularly limited thereto. Each of the first electrical connection metal 151 and the second electrical connection metal 152 may be a pad, a ball, a pin, or the like. Each of the first electrical connection metal 151 and the second electrical connection metal 152 may be formed using multiple layers or a single layer. When the first electrical connection metal 151 and the second electrical connection metal 152 are formed using multiple layers, the first electrical connection metal 151 and the second electrical connection metal 152 may include copper pillars and solder formed on the copper pillars, and when the first electrical connection metal 151 and the second electrical connection metal 152 are formed using a single layer, the first electrical connection metal 151 and the second electrical connection metal 152 may include tin-silver solder or copper, but the present disclosure is not limited thereto. Each of the first electrical connection metal 151 and the second electrical connection metal 152 may be formed in plural.

[0058] Other descriptions may be substantially the same as those described in the printed circuit board 100A according to the above-described example embodiment, and thus, duplicate descriptions will be omitted.

[0059] Figure 8 is a cross-sectional view schematically showing another example of a printed circuit board.

[0060] Reference Figure 8 Compared with the printed circuit board 100B according to the above-mentioned other example embodiment, the printed circuit board 100C according to another example embodiment may further include a first under bump metal 161 and a second under bump metal 162, the first under bump metal 161 being arranged between at least a portion of the exposed third interconnection layer 123 and the first electrical connection metal 151, and the second under bump metal 162 being arranged between at least a portion of the exposed fourth interconnection layer 124 and the second electrical connection metal 152.

[0061] The first and second UBMs 161 and 162 can improve the connection reliability of the first and second electrical connection metals 151 and 152. Each of the first and second UBMs 161 and 162 can include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. The metal may preferably include copper (Cu), but the present disclosure is not limited thereto. Each of the first and second UBMs 161 and 162 can include a seed layer and a plating layer. The seed layer can be formed by electroless plating (or chemical copper plating) and, if desired, by sputtering. Alternatively, the seed layer can be formed using both electroless plating and sputtering processes. The plating layer can be formed by electrolytic plating (or electrolytic copper). Each of the first and second UBMs 161 and 162 may be formed using a via portion and a pad portion, but the present disclosure is not limited thereto, and each of the first and second UBMs 161 and 162 may be formed using only a via portion. For example, each of the first and second UBMs 161 and 162 may have a structure in which a via protrudes onto the first and second resist layers 115 and 116 without a pad. Each of the first and second UBMs 161 and 162 may be provided in plural.

[0062] Other descriptions may be substantially the same as those described above in the printed circuit board 100A according to the example embodiment and the printed circuit board 100B according to another example embodiment, and thus, repeated descriptions will be omitted.

[0063] In the present disclosure, the expression "covering" may include the case of covering a part as well as the case of covering the whole, and may also include the case of direct covering and indirect covering. In addition, the expression "filling" may include not only the case of complete filling but also the case of partial filling, or may also include the case of approximately filling. For example, the expression "filling" may include the case where there are some pores or gaps therein. In addition, the expression "surrounding" may include not only the case of complete surrounding but also the case of partial surrounding, as well as the case of approximately surrounding. In addition, exposing may include the case of partial exposure as well as the case of complete exposure, and exposing may refer to the exposure of an element from the corresponding component that embeds the element. For example, exposing a pad through an opening may be exposing the pad from the resist layer, and a surface treatment layer or the like may be further provided on the exposed pad.

[0064] In the present disclosure, in a cross section, "being disposed in a through-portion or through-hole" may include not only a case where the object is completely disposed in the through-portion or through-hole, but also a case where the object partially protrudes upward or downward from the through-portion or through-hole. For example, when an object is disposed in a through-portion or through-hole in a plan view, this can be determined in a broader sense.

[0065] In the present disclosure, "substantially" may be determined by taking into account process errors, positional deviations, and measurement errors that may occur during the manufacturing process. For example, "substantially perpendicular" may include not only completely perpendicular but also approximately perpendicular. Furthermore, "substantially coplanar" may include not only elements being completely on the same plane but also elements being approximately on the same plane.

[0066] In the present disclosure, the same insulating material may refer to not only the same insulating material but also the same type of insulating material. Therefore, the composition of the insulating material may be substantially the same, but its specific composition ratio may vary slightly.

[0067] In the present disclosure, the term "cross section" may refer to the cross-sectional shape when an object is cut vertically or the shape when the object is viewed from a side perspective. In addition, the term "plane" may refer to the shape when an object is cut horizontally or the shape when the object is viewed from a top or bottom perspective.

[0068] In this disclosure, for the sake of convenience, the lower side, lower portion, and lower surface are used to refer to the downward direction relative to the cross section of the drawings, and the upper side, upper portion, and upper surface are used to refer to the direction opposite to the downward direction. However, the above directions are defined for the convenience of explanation, and the scope of the claims is not particularly limited by the description of the directions, and the concepts of upper and lower portions may be changed at any time.

[0069] In the present disclosure, the meaning of "connected" includes not only direct connection but also indirect connection through an adhesive layer or the like. In addition, the meaning of "electrically connected" includes both physical connection and non-physical connection. In addition, expressions such as "first" and "second" are used to distinguish one component from another and do not limit the order and / or importance of the components. In some cases, without departing from the scope of the claims, a first component may be referred to as a second component, or similarly, a second component may be referred to as a first component.

[0070] In the present disclosure, thickness, width, length, depth, line width, gap, pitch, separation distance, surface roughness, etc. can be measured using a scanning electron microscope, an optical microscope, etc. based on a cross section of a polished or cut printed circuit board. The cross section can be a vertical cross section or a horizontal cross section, and each value can be measured based on the desired cross section. For example, the width of the upper and / or lower portion of the via can be measured in a cross section cut along the central axis of the via. In this case, when these values ​​are not constant, they can be determined as the average of the values ​​measured at five arbitrary points.

[0071] The term "exemplary embodiment" used in this disclosure does not necessarily mean the same embodiment, but is provided to illustrate different unique features. However, the exemplary embodiments presented above do not exclude implementation in combination with features of other exemplary embodiments. For example, even if the content described in a particular exemplary embodiment is not described in other exemplary embodiments, it can be understood as an explanation related to the other exemplary embodiments unless there is an interpretation that is contrary to or contradictory to the content in other exemplary embodiments.

[0072] The terms used in the present disclosure are only used to describe example embodiments and are not intended to limit the present disclosure. In this case, unless they are clearly stated otherwise in the context, the singular meaning includes the plural meaning.

[0073] While example embodiments have been shown and described above, it will be readily apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A printed circuit board, comprising: a first insulating layer; a through via penetrating at least a portion of a region of the first insulating layer between the upper surface and the lower surface and having one or more gap portions, wherein the one or more gap portions respectively separate at least a portion of one or more side surfaces of the upper portion and / or the lower portion of the through via from the first insulating layer; as well as A second insulating layer is provided on the first insulating layer, covers at least a portion of the one or more side surfaces of the upper portion and / or the lower portion of the through-via, and fills at least a portion of each of the one or more gap portions.

2. The printed circuit board according to claim 1, in, The upper surface and / or the lower surface of the first insulating layer has a step difference with respect to an upper surface and / or a lower surface of the through via.

3. The printed circuit board according to claim 2, in, The upper surface of the first insulating layer is disposed above the upper surface of the through via, and Wherein, the lower surface of the first insulating layer is arranged below the lower surface of the through via.

4. The printed circuit board according to claim 1, in, The first insulating layer includes an inorganic insulating material, and Wherein, the second insulating layer comprises an organic insulating material.

5. The printed circuit board according to claim 4, in, The first insulating layer includes a glass substrate, and Wherein, the second insulating layer includes a prepreg or an Ajinomoto deposited film.

6. The printed circuit board according to claim 1, in, In the through-via, a maximum width in each of the upper portion and the lower portion of the through-via is wider than a minimum width in a center portion between the upper portion and the lower portion of the through-via.

7. The printed circuit board according to claim 1, further comprising: A frame having a through portion, wherein at least a portion of the first insulating layer is disposed in the through portion, and Wherein, the second insulating layer fills at least a portion of the through portion.

8. The printed circuit board according to claim 1, further comprising: a first interconnection layer disposed on an upper surface of the second insulating layer; a second interconnection layer disposed on a lower surface of the second insulating layer; a first connecting via penetrating a portion of the second insulating layer and connecting at least a portion of the first interconnect layer to an upper surface of the through via; as well as a second connecting via penetrating another portion of the second insulating layer and connecting at least a portion of the second interconnect layer to a lower surface of the through via, Wherein, the first connecting via and the second connecting via taper in opposite directions.

9. The printed circuit board according to claim 8, further comprising: a third insulating layer disposed on the upper surface of the second insulating layer and covering at least a portion of the first interconnection layer; a fourth insulating layer disposed on the lower surface of the second insulating layer and covering at least a portion of the second interconnect layer; a third interconnection layer, disposed on an upper surface of the third insulating layer; a fourth interconnection layer, disposed on the lower surface of the fourth insulating layer; a third connection via penetrating a portion of the third insulating layer and connecting at least a portion of each of the first interconnect layer and the third interconnect layer; as well as a fourth connecting via penetrating a portion of the fourth insulating layer and connecting at least a portion of each of the second interconnection layer and the fourth interconnection layer, Wherein, the third connecting via hole and the fourth connecting via hole are tapered in opposite directions.

10. The printed circuit board according to claim 9, further comprising: a first resist layer disposed on the upper surface of the third insulating layer and having a first opening exposing at least a portion of the third interconnect layer; as well as A second resist layer is disposed on the lower surface of the fourth insulating layer and has a second opening exposing at least a portion of the fourth interconnection layer.

11. The printed circuit board according to claim 10, further comprising: a first electrical connection metal disposed on the first opening and connected to the exposed at least a portion of the third interconnect layer; as well as A second electrical connection metal is disposed on the second opening and connected to the at least one portion of the exposed fourth interconnect layer.

12. The printed circuit board according to claim 11, further comprising: a first under bump metallurgy disposed between the exposed at least a portion of the third interconnect layer and the first electrical connection metallurgy; as well as A second under bump metallurgy is disposed between the at least one exposed portion of the fourth interconnect layer and the second electrical connection metallurgy.

13. A printed circuit board comprising: Glass substrate; a through hole extending between the upper surface and the lower surface of the glass substrate; a metal via filling at least a portion of the through hole; One or more gaps are respectively provided between the side surface of the upper portion of the metal via and the wall surface of the through hole and between the side surface of the lower portion of the metal via and the wall surface of the through hole; as well as An insulating layer is provided on the glass substrate and fills at least a portion of each of the one or more gaps.

14. The printed circuit board according to claim 13, in, The upper surface and the lower surface of the metal via are respectively recessed toward the inside of the metal via relative to the upper surface and the lower surface of the glass substrate.

15. The printed circuit board according to claim 13, in, The metal via includes a seed layer provided on a portion of the wall surface of the through hole and a metal layer filling at least a portion of the through hole, and Here, each of the one or more gap portions is at least partially provided between another portion of the wall surface of the through hole and a side surface of the metal layer.

16. The printed circuit board according to claim 13, further comprising: a connecting via, penetrating a portion of the insulating layer and directly connected to the metal via; as well as An interconnection layer is provided on the insulating layer and is directly connected to the connection via.

17. A printed circuit board comprising: a first insulating layer; a plurality of through vias arranged in a grid pattern, each through via penetrating the first insulating layer and having one or more gaps, the one or more gaps respectively separating at least a portion of one or more side surfaces of the through via from the first insulating layer; a second insulating layer, disposed on the first insulating layer; as well as A conductive layer is disposed on the second insulating layer and is electrically connected to at least one of the through vias.

18. The printed circuit board according to claim 17, in, The one or more gaps are filled with an insulating material.

19. The printed circuit board according to claim 17, in, The through hole has wider diameters at the upper and lower portions and a narrower diameter at the center portion.

20. A printed circuit board comprising: a first insulating layer comprising an inorganic material; a through via extending through the first insulating layer, wherein the through via comprises an upper portion, a lower portion, and a central portion, and wherein the upper portion and the lower portion of the through via are respectively recessed inward from an upper surface and a lower surface of the first insulating layer to form a dish or a pit; one or more gaps, respectively separating at least a portion of a side surface of the upper portion and / or the lower portion of the through-hole from the first insulating layer; a second insulating layer disposed on the first insulating layer and filling at least a portion of the one or more gaps; and An interconnection layer is disposed on the second insulating layer and electrically connected to the through via.

21. A printed circuit board comprising: a frame having a through portion; a glass substrate, at least partially disposed in the through portion; an insulating layer comprising a first insulating portion, a second insulating portion, and a filling portion, wherein the first insulating portion covers at least a portion of each of an upper surface of the frame and an upper surface of the glass substrate, the second insulating portion covers at least a portion of each of a lower surface of the frame and a lower surface of the glass substrate, and the filling portion fills at least a portion of a space between the frame and the glass substrate in the through portion; a through hole penetrating at least a portion of the space between the upper surface and the lower surface of the glass substrate; a first connecting via hole penetrating a portion of the first insulating portion and directly connected to an upper side of the through via hole; as well as The second connecting via penetrates a portion of the second insulating portion and is directly connected to a lower side of the through via.

22. The printed circuit board according to claim 21, in, A thickness of the glass substrate between the upper surface and the lower surface is thicker than a thickness of the through-hole between the upper surface and the lower surface.

23. The printed circuit board according to claim 21, in, The through hole includes: a seed layer provided on a wall surface of the through hole passing between the upper surface and the lower surface of the glass substrate; and a metal layer provided on the seed layer and filling at least a portion of the through hole, and The seed layer includes multiple layers.

24. The printed circuit board according to claim 21, in, The through hole has a substantially hourglass shape, The first connection via has a generally tapered shape with an upper portion thereof being wider than a lower portion thereof, and The second connection via has a generally tapered shape with a lower portion thereof being wider than an upper portion thereof.

25. The printed circuit board according to claim 21, further comprising: a first interconnection layer disposed on an upper surface of the first insulating portion and connected to the first connection via; as well as A second interconnection layer is provided on a lower surface of the second insulating portion and connected to the second connection via.

26. The printed circuit board according to claim 21, wherein The first insulating portion, the second insulating portion, and the filling portion are integrated with each other.

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