Manufacturing method of stacked hole structure and circuit board

Abstract

The invention discloses a manufacturing method of a stacked hole structure and a circuit board. The manufacturing method of the stacked hole structure comprises the following steps: filling anti-plating ink at a position where a blind hole needs to be drilled of a first core board; the first core plate is laminated into a multi-layer plate, and the first core plate is located on the outermost layer of the multi-layer plate; a blind hole is formed in the multilayer board, and anti-plating ink is arranged on the peripheral side of one end of the blind hole; copper deposition processing is carried out on the multilayer board, and the hole walls of the blind holes and the surface of the anti-plating ink are covered with copper; washing the multilayer board to remove the anti-plating ink so as to obtain a plug hole; filling a conducting medium in the plug hole; carrying out lamination layer adding on the multilayer board; stacking holes are formed in the positions, corresponding to the plug holes, of the layer-added circuit board; and filling a conductive medium in the stacked hole and curing to obtain an internally interconnected stacked hole structure. The plug holes and the stacked holes are filled with conductive media which are made of the same material, so that layered hole blasting caused by thermal expansion in the stacked hole structure can be avoided, the reliability of the circuit board is ensured, and the wiring area of the circuit board is ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of printed circuit boards, and in particular to a manufacturing method of a stacked hole structure and a circuit board. Background Art

[0002] With the ultimate pursuit of performance in electronic products, multifunctional miniaturization has become the mainstream design method for many products. As the basic carrier board for all devices to perform their functions, PCB is also constantly improving its wiring density for more assembly. Therefore, high-density interconnected PCB design is becoming more and more one of the ideal solutions.

[0003] One of the hallmarks of high density is the multi-level design of blind, buried, and stacked vias. In stacked via design, a through-hole is first fabricated, then electroplated and filled with resin, followed by a copper cover. Finally, a laser blind via is created above the hole. This stacked via structure carries the risk of delamination and cracking at the junction between the resin and the copper cover, due to the high CTE of the resin filling the through-hole. Summary of the Invention

[0004] The present invention aims to address at least one of the technical problems existing in the prior art. To this end, the present invention proposes a method for fabricating a stacked via structure, wherein both the plugged via and the stacked via are filled with a conductive medium. The same material prevents thermal expansion and delamination of the stacked via structure, thereby ensuring the reliability of the circuit board and the wiring area of ​​the circuit board.

[0005] The embodiment of the present invention also provides a circuit board According to the first aspect of the present invention, the manufacturing method of the stacked hole structure includes the following steps: S1: filling the position of the blind hole to be drilled in the first core board with anti-plating ink; S2: laminating the first core board into a multi-layer board, and the first core board is located at the outermost layer of the multi-layer board; S3: making a blind hole in the multi-layer board, and the circumference of one end of the blind hole is provided with anti-plating ink; S4: performing copper plating processing on the multi-layer board, and the hole wall of the blind hole and the surface of the anti-plating ink are covered with copper; S5: stripping and washing the multi-layer board to remove the anti-plating ink to obtain a plugged hole; S6: filling the plugged hole with a conductive medium; S7: laminating and adding layers on the multi-layer board; S8: opening a stacked hole at the position of the plugged hole on the circuit board after the addition of layers; S9: filling the stacked hole with a conductive medium and curing it to obtain an internally interconnected stacked hole structure.

[0006] According to the manufacturing method of the stacked via structure of the embodiment of the present invention, both the plug via and the stacked via are filled with a conductive medium. The same material can prevent the stacked via structure from expanding due to heat and causing delamination and explosion, thereby ensuring the reliability of the circuit board.

[0007] According to some embodiments of the present invention, before S7, the process further includes: curing the conductive medium in the plug hole, and forming an inner layer pattern on the surface of the multilayer board.

[0008] According to some embodiments of the present invention, before step S8, the method further includes: opening a window at a position of the multilayer board corresponding to the plug hole.

[0009] According to some embodiments of the present invention, before step S6, the step further includes: performing thickening copper plating on the hole wall of the blind hole.

[0010] According to some embodiments of the present invention, a size of the plating resist ink is larger than a size of the blind hole.

[0011] According to some embodiments of the present invention, filling the anti-plating ink at the position where the blind hole needs to be drilled in the first core board includes: opening a filling groove at the position where the blind hole needs to be drilled in the first core board, and filling the anti-plating ink in the filling groove.

[0012] According to some embodiments of the present invention, filling the first core board with anti-plating ink at the location where the blind hole needs to be drilled includes: opening a filling hole at the location where the blind hole needs to be drilled in the first core board, and filling the anti-plating ink in the filling hole.

[0013] According to some embodiments of the present invention, the multilayer board includes: a prepreg, a copper foil, a first core board and a second core board, and the first core board and the second core board are provided with inner layer circuits.

[0014] The circuit board according to the embodiment of the second aspect of the present invention includes: a stacked hole structure, which is manufactured using the above-mentioned manufacturing method.

[0015] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments with reference to the following drawings, in which: Figure 1 is a flow chart of a method for manufacturing a printed circuit board according to an embodiment of the present invention; Figure 2 is a schematic diagram of a first core plate having a filling hole according to an embodiment of the present invention; Figure 3 The first core board is filled with anti-plating ink according to an embodiment of the present invention Figure 4 is a schematic diagram of laminating a first core board into a multilayer board according to an embodiment of the present invention; Figure 5is a schematic diagram of drilling blind vias in a multilayer board according to an embodiment of the present invention; Figure 6 is a schematic diagram of copper deposition for a multilayer board according to an embodiment of the present invention; Figure 7 is a schematic diagram of removing the plating resist ink according to an embodiment of the present invention; Figure 8 Schematic diagram of thickening copper plating on the wall of a blind hole according to an embodiment of the present invention; Figure 9 is a schematic diagram of filling a plug hole with a conductive medium according to an embodiment of the present invention; Figure 10 is a schematic diagram of laminating and adding layers to a multilayer board according to an embodiment of the present invention; Figure 11 is a schematic diagram of drilling stacked holes in a multilayer board according to an embodiment of the present invention; Figure 12 Schematic diagram of filling a conductive medium in a stacked via according to an embodiment of the present invention.

[0017] Reference numerals: 11. First core board; 111. Insulation layer; 112. Copper layer; 113. Filling hole; 12. Anti-plating ink; 13. Multilayer board; 14. Blind hole; 15. Plug hole; 16. Conductive medium; 17. Stacked hole; 18. Stacked hole structure. DETAILED DESCRIPTION

[0018] The embodiments of the present invention will be described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. The embodiments of the present invention will be described in detail below.

[0019] Reference below Figures 1-12 The following describes a method for manufacturing the stacked hole structure 18 according to an embodiment of the present invention, and a circuit board manufactured by the method for manufacturing the stacked hole structure 18 .

[0020] like Figure 1 As shown, the method for manufacturing the stacked hole structure 18 includes the following steps: S1: Filling the anti-plating ink 12 at the position where the blind hole 14 is to be drilled on the first core board 11 .

[0021] like Figure 3 As shown, the first core board 11 includes an insulating layer 111 and copper layers 112 on both sides. The upper and lower surfaces of the insulating layer 111 are both covered with copper layers 112, that is, the upper and lower surfaces of the insulating layer 111 are both covered with copper foil. After determining which locations on the first core board 11 require blind vias 14, grooves or holes are formed in the locations of the first core board 11 where backdrilling is required, and the grooves or holes are filled with plating resist ink 12.

[0022] The resist ink 12 has good adhesion and corrosion resistance and can maintain stable performance under various electroplating conditions. The resist ink 12 can form a stable chemical bond or physical barrier with the metal surface during the electroplating process, thereby preventing the electroplating solution from corroding the resist ink 12.

[0023] S2 : laminating the first core board 11 into a multilayer board 13 , with the first core board 11 being located at the outermost layer of the multilayer board 13 .

[0024] like Figure 4 As shown, the first core board 11 is laminated with other core boards to form a multilayer board 13. The multilayer board 13 can be layered, with the signal routing of different functional modules arranged on different board layers. This can improve circuit performance and reduce signal interference. Through the lamination method, signal lines, power lines, and ground lines can be laid out between different layers, forming a good signal loop and improving the rigidity and durability of the circuit board.

[0025] Figure 2-Figure 12 In the example, the first core board 11 is located on the uppermost layer of the multilayer board 13.

[0026] S3: A blind hole 14 is made on the multilayer board 13 , and a plating resist ink 12 is provided around one end of the blind hole 14 .

[0027] like Figure 5 As shown, a blind hole 14 is drilled on the multilayer board 13, the first core board 11 is located on the side of the back-drilled through hole, and the anti-plating ink 12 corresponds to the blind hole 14. The size of the anti-plating ink 12 is larger than the blind hole 14, and a part of the anti-plating ink 12 arranged opposite to the through hole is removed, and the remaining part of the anti-plating ink 12 is arranged around the circumference of one end of the through hole.

[0028] S4: copper plating is performed on the multilayer board 13 , and the hole walls of the blind holes 14 and the surface of the plating resist ink 12 are covered with copper.

[0029] like Figure 6 As shown, in step S4, the surface of the multilayer board 13 is subjected to overall copper plating processing, copper is plated on the inner wall of the blind hole 14, and copper is plated on the surface of the anti-plating ink 12, so that the hole wall of the blind hole 14 and the surface of the anti-plating ink 12 are covered with copper.

[0030] The holes formed by mechanical drilling or laser drilling have walls primarily composed of non-conductive materials. If electroplating is performed directly, current cannot flow through these hole walls, making copper plating impossible. Therefore, it is necessary to first deposit copper on the walls of the blind via 14 through a copper deposition process to achieve adhesion of the electroplated copper.

[0031] S5: The multilayer board 13 is stripped to remove the plating resist ink 12 to obtain the plug hole 15.

[0032] like Figure 7As shown, the method of removing the plating resist ink 12 can be chemical washing or physical washing.

[0033] The plating resist ink 12 can be removed in an alkaline environment. When the plating resist ink 12 is removed, the copper on the surface of the plating resist ink 12 is also removed, exposing the area of ​​the first core board 11 filled with the plating resist ink 12. The plug hole 15 includes the blind hole 14 and the opening on the first core board 11.

[0034] S6: Fill the plug hole 15 with a conductive medium 16 .

[0035] like Figure 9 As shown, the conductive medium 16 can be conductive ink, conductive copper paste, or other conductive materials with low CTE (coefficient of thermal expansion) fillers. After the conductive medium 16 is filled in the plug hole 15 and cured, the surface of the conductive medium 16 is flush with the surface of the first core board 11.

[0036] A vacuum plugging machine can be used to fill the plug hole 15 with the conductive medium 16. Vacuum filling of the conductive medium 16 can prevent air from entering the plug hole 15 to generate voids and affect the density of the conductive medium 16 filling.

[0037] S7: Laminating and building up the multilayer board 13.

[0038] like Figure 10 As shown, the two surfaces of the multilayer board 13 are laminated and added layers are added. First, the surface of the first core board 11 is roughened, and then the copper foil is pressed to the multilayer board 13 with an adhesive using a hot press. After pressing, the adhesive serves as a new insulating medium layer, and the outer copper foil serves as a new upper copper layer 112.

[0039] The adhesive may be a prepreg or a thermosetting adhesive.

[0040] S8: Open overlapping holes 17 at positions corresponding to plug holes 15 on the circuit board.

[0041] according to Figure 11 As shown, the multilayer board 13 obtained in step S7 is drilled, and a laser drilling method can be used to drill stacked holes 17 at positions corresponding to the blind holes 14 in the multilayer board 13 after the added layers. The opening of the stacked hole 17 is in the new upper copper layer 112, and the bottom of the hole is the surface of the first core board 11, and the bottom of the hole is the conductive medium 16 in the plug hole 15.

[0042] S9: Filling the stacked holes 17 with a conductive medium 16 and curing the conductive medium to obtain an internally interconnected stacked hole structure 18 .

[0043] like Figure 12As shown, the same conductive medium 16 as in the plug hole 15 is filled in the stacked hole 17 and solidified, so that the conductive medium 16 in the stacked hole 17 is electrically connected to the conductive medium 16 in the plug hole 15, thereby obtaining an internally interconnected stacked hole structure 18.

[0044] Because plugged via 15 and stacked via 17 are made of the same material, their CTE (coefficient of thermal expansion) is consistent, eliminating the risk of delamination and explosion due to thermal expansion. Furthermore, bubbles and voids in plugged via 15 are negligible, as the inner layer is already electroplated with copper layer 112, ensuring the foundation for internal interconnection. This allows the creation of stacked via structure 18 that saves wiring and eliminates reliability risks. The non-staggered design of plugged via 15 and stacked via 17 fully preserves the wiring area on the circuit board.

[0045] According to some embodiments of the present invention, before S7 , the process further includes: curing the conductive medium 16 in the plug hole 15 , and forming an inner layer pattern on the multilayer board 13 .

[0046] That is, in step S6, after the conductive medium 16 is filled into the plug hole 15, the conductive medium 16 in the plug hole 15 is cured, and the upper surface of the conductive medium 16 is flush with the first core board 11. The inner layer pattern is formed on the upper and lower surfaces of the multilayer board 13, and the inner layer pad is formed at the location of the plug hole 15. After the inner layer pattern is formed, the surface of the inner layer pattern is roughened, and then the copper foil is pressed to the multilayer board 13 using an adhesive using a hot press. After pressing, the adhesive serves as a new insulating dielectric layer, and the outer copper foil serves as a new upper copper layer 112.

[0047] According to some embodiments of the present invention, before step S8, the process further includes: opening a window at a position on the multilayer board 13 corresponding to the plug hole 15. Before drilling the stacked via 17, a window is first opened at a position on the multilayer board 13 corresponding to the plug hole 15 to facilitate subsequent drilling of the stacked via 17 on the multilayer board 13.

[0048] like Figure 8 As shown, before step S6, it also includes: thickening the hole wall of the blind hole 14 with copper plating. Before performing step S6, the hole wall of the blind hole 14 needs to be thickened with copper plating. After copper deposition in step S4, a thin copper layer 112 is attached to the hole wall of the blind hole 14, but it is easy to cause the inner layer circuit of the multilayer board 13 to be partially disconnected. After thickening the hole wall with copper plating, the reliability of the inner layer circuit interconnection can be improved, which can meet the inter-layer interconnection requirements of the circuit board and greatly increase the flexibility of the inter-layer interconnection density. When there are bubbles and voids in the conductive medium 16, the thickened copper layer 112 on the hole wall of the blind hole 14 can avoid the open circuit reliability risk of the inner layer interconnection.

[0049] Furthermore, the size of the plating resist 12 is larger than that of the blind via 14. Specifically, the size of the plating resist 12 is the size of the upper surface of the conductive medium 16 filled in the plug hole 15. The upper surface of the conductive medium 16 is used to form the inner layer pad. The size of the inner layer pad needs to be larger than that of the blind via 14 to facilitate the soldering operation.

[0050] In some embodiments, filling the first core board 11 with the resist ink 12 at the location where the blind hole 14 is to be drilled includes: opening a filling groove at the location where the blind hole 14 is to be drilled on the first core board 11, and filling the filling groove with the resist ink 12. Specifically, a filling groove can be opened at the location of the first core board 11 corresponding to the blind hole 14, the depth of the filling groove being greater than the thickness of the copper foil on the surface of the first core board 11 and less than the thickness of the first core board 11, filling the filling groove with the resist ink 12, and curing the resist ink 12. After curing, the resist ink 12 is substantially flush with the upper surface of the first core board 11, thereby facilitating copper deposition processing of the multilayer board 13.

[0051] Furthermore, the filling groove can be in a regular shape or an irregular shape. In order to facilitate the manufacturing process, the filling groove can be in a regular shape, such as a rectangle, a circle or an ellipse.

[0052] The filling slot is larger than the blind hole 14, so that the size of the plating resist ink 12 is larger than the blind hole 14, facilitating the formation of inner-layer solder pads on the conductive medium 16 within the filling slot. The projection of the filling slot onto the first core board 11 can be circular, with a diameter larger than the diameter of the through hole, thereby reducing the amount of plating resist ink 12 used in the circuit board manufacturing process and lowering manufacturing costs.

[0053] In addition, the projection of the filling groove on the first core board 11 can be an ellipse. Since the size of the dry film is larger than the through hole and the anti-plating ink 12 is larger than the size of the dry film, the minimum diameter of the ellipse needs to be larger than the diameter of the through hole to ensure that the etching solution will not enter the through hole and corrode the copper during the exposure and development process, thereby avoiding open circuits in the inner layer of the multilayer board 13.

[0054] like Figure 1 As shown, the location of the blind hole 14 to be drilled on the first core board 11 is filled with the plating resist ink 12, including: opening a filling hole 113 at the location of the blind hole 14 to be drilled on the first core board 11, and filling the plating resist ink 12 in the filling hole 113. Specifically, the filling hole 113 can be opened at the location of the first core board 11 corresponding to the blind hole 14, the depth of the filling hole 113 is greater than the thickness of the copper foil on the surface of the first core board 11 and less than the thickness of the first core board 11, the plating resist ink 12 is filled in the filling hole 113, and the plating resist ink 12 is cured. After curing, the plating resist ink 12 is roughly flush with the upper surface of the first core board 11, which facilitates the copper plating processing of the multilayer board 13.

[0055] The filling hole 113 may be in a regular shape or an irregular shape. To facilitate manufacturing, the filling hole 113 may be in a regular shape, such as a rectangle, a circle, or an ellipse.

[0056] Combine Figure 2-Figure 12 As shown, multilayer board 13 includes: prepreg, copper foil, first core board 11 and second core board, and inner layer circuits are provided on the first core board 11 and second core board. Multilayer board 13 is a multilayer board 13 in which the first core board 11, the second core board and the copper foil are pressed together by prepreg, and the first core board 11 and the second core board are already provided with inner layer circuits before pressing together.

[0057] The circuit board according to the embodiment of the second aspect of the present invention includes: a stacked hole structure 18, and the stacked hole structure 18 is manufactured by using the above-mentioned manufacturing method.

[0058] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0059] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "example," "specific example," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example.

[0060] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the claims and their equivalents.

Claims

1. A method for manufacturing a stacked hole structure, characterized in that: The following steps are involved: S1: Filling the first core board (11) with anti-plating ink (12) at the location where the blind hole (14) needs to be drilled; S2: laminating the first core board (11) into a multilayer board (13), with the first core board (11) being located at the outermost layer of the multilayer board (13); S3: making a blind hole (14) on the multilayer board (13), wherein a plating-resistant ink (12) is provided around one end of the blind hole (14); S4: copper plating is performed on the multilayer board (13), and the hole wall of the blind hole (14) and the surface of the anti-plating ink (12) are covered with copper; S5: washing the multilayer board (13) to remove the resist ink (12) to obtain a plug hole (15); S6: Filling the plug hole (15) with a conductive medium (16); S7: laminating the multilayer board (13); S8: Opening a stacking hole (17) at a position corresponding to the plug hole (15) of the multilayer board (13) after the added layers; S9: Filling the stacked holes (17) with a conductive medium (16) and curing the stacked holes to obtain an internally interconnected stacked hole structure (18).

2. The method for manufacturing a stacked hole structure according to claim 1, wherein: Before S7, the process also includes: curing the conductive medium (16) in the plug hole (15), and producing an inner layer pattern on the surface of the multilayer board (13).

3. The method for manufacturing a stacked hole structure according to claim 1, wherein: Before the step S8, the step further includes: opening a window at a position of the multilayer board (13) corresponding to the plug hole (15).

4. The method for manufacturing a stacked hole structure according to claim 1, wherein: Before step S6, the method further includes: The hole wall of the blind hole (14) is thickened and copper plated.

5. The method for manufacturing a stacked hole structure according to claim 1, wherein: The size of the anti-plating ink (12) is larger than the size of the blind hole (14).

6. The method for manufacturing a stacked hole structure according to claim 1, wherein: The method of filling the anti-plating ink (12) at the position of the blind hole (14) to be drilled on the first core board (11) comprises: A filling groove is provided at a position of the first core plate (11) where a blind hole (14) is to be drilled, and the filling groove is filled with anti-plating ink (12).

7. The method for manufacturing a stacked hole structure according to claim 1, wherein: The method of filling the anti-plating ink (12) at the position of the blind hole (14) to be drilled on the first core board (11) comprises: A filling hole (113) is opened at a position of the first core plate (11) where a blind hole (14) needs to be drilled, and anti-plating ink (12) is filled in the filling hole (113).

8. The method for manufacturing a stacked hole structure according to claim 1, wherein: The multilayer board (13) comprises: a prepreg, a copper foil, a first core board (11) and a second core board, wherein the first core board (11) and the second core board are provided with inner layer circuits.

9. A circuit board, characterized in that: include: A stacked hole structure (18), wherein the stacked hole structure (18) is manufactured using the manufacturing method described in any one of claims 1 to 8.

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