Ferroelectric field effect transistor, manufacturing method thereof and manufacturing method of transistor

Abstract

A method of manufacturing a device according to an embodiment of the present invention includes forming a first layer. The first layer may be a ferroelectric layer when the device is a ferroelectric field effect transistor, or the first layer may be a gate dielectric layer when the device is a transistor. Optionally, the first layer may be a channel for a device. A metal layer is deposited on the first layer by physical vapor deposition, and then the metal layer is exposed to ozone or an ozone plasma to form a metal oxide layer on the first layer. A second layer is formed on the metal oxide layer. Forming the metal oxide layer may further include exposing the first layer to ozone or an ozone plasma prior to depositing the metal layer. The metal layer may be a titanium layer.

Description

Technical Field

[0001] The embodiments of the present invention relate to a ferroelectric field effect transistor, a manufacturing method thereof, and a manufacturing method of a transistor. Background Art

[0002] Including a thin metal oxide interfacial layer on the channel of various types of transistors, such as thin film transistors (TFTs) or ferroelectric field effect transistors (FeFETs), can provide certain performance advantages. Summary of the Invention

[0003] A method for manufacturing a ferroelectric field-effect transistor (FeFET) according to an embodiment of the present invention includes: forming a first layer, wherein the first layer is one of the first ferroelectric layer and the channel of the FeFET; depositing a first metal layer on the first layer by physical vapor deposition, and then exposing the first metal layer to ozone or ozone plasma to form a first metal oxide layer on the first layer; and forming a second layer on the first metal oxide layer, wherein the second layer is the other of the first ferroelectric layer and the channel of the FeFET.

[0004] A ferroelectric field-effect transistor (FeFET) according to an embodiment of the present invention comprises: a ferroelectric layer; a channel; and a first titanium oxide layer disposed between the ferroelectric layer and the channel and in contact with the ferroelectric layer and the channel; wherein the FeFET has an on-state current (Ion) of at least 50 microamperes per micrometer.

[0005] A method for manufacturing a transistor according to an embodiment of the present invention includes: forming a first layer, wherein the first layer is one of a gate dielectric layer and a channel of the transistor; depositing a metal layer on the first layer by physical vapor deposition, and then exposing the metal layer to ozone or ozone plasma to form a metal oxide layer on the first layer; and forming a second layer on the metal oxide layer, wherein the second layer is the other of the gate dielectric layer and the channel of the transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 A side cross-sectional view of a ferroelectric field effect transistor (FeFET) including two titanium oxide layers is schematically illustrated, and a process for forming each titanium oxide layer is further schematically depicted.

[0008] Figure 2 Schematically illustrates Figure 1Top view of the FeFET shown.

[0009] Figure 3 The workflow for fabricating FeFETs is schematically illustrated.

[0010] Figure 4A 、 4B , 4C and 4D schematically illustrate the Figure 3 Side cross-sectional views of FeFETs being fabricated at successive stages of the workflow shown, including the use of Figure 1 The schematically depicted process forms two titanium oxide layers.

[0011] Figure 5 Schematic diagram of a side cross-section of a bottom-gate thin-film transistor (TFT) comprising two titanium oxide layers, each of which is formed using Figure 1 Schematic depiction of the process of formation.

[0012] Figure 6 Schematic illustration of a bottom-gate FeFET comprising two titanium oxide layers, each of which is fabricated using Figure 1 Schematic depiction of the process of formation.

[0013] Figure 7 Schematic illustration of a top-gate TFT, including the use of Figure 1 Schematic depiction of the process for forming the titanium oxide layer.

[0014] Figure 8 Schematic illustration of a top-gate FeFET, which includes a ferroelectric layer and uses Figure 1 Schematic depiction of the process for forming the titanium oxide layer.

[0015] Figure 9 Schematic illustration of a dual-gate TFT comprising two titanium oxide layers, each of which is formed using Figure 1 Schematic depiction of the process of formation.

[0016] Figure 10 Schematic illustration of a dual-gate FeFET consisting of two titanium oxide layers, each made using Figure 1 Schematic depiction of the process of formation.

[0017] Figure 11 Schematically illustrates a three-dimensional (3D) or vertical field effect transistor (FET), which can be a TFT or FeFET, and includes the use of Figure 1 Schematic depiction of the process for forming the titanium oxide layer. DETAILED DESCRIPTION

[0018] The following disclosure provides many different embodiments or examples for implementing different features of the provided objects. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature above or on a second feature may include embodiments in which the first feature and the second feature are formed to be in direct contact, and may also include embodiments in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. In addition, the disclosure may reuse reference numbers and / or letters in various examples. Such repetition is for the purpose of brevity and clarity and does not itself represent a relationship between the various embodiments and / or configurations discussed.

[0019] Furthermore, for ease of description, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," and the like, may be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0020] Including a thin metal oxide interfacial layer on the channel of various types of transistors, such as thin-film transistors (TFTs) or ferroelectric field-effect transistors (FeFETs), can offer certain performance advantages. For example, a thin titanium oxide interfacial layer between the ferroelectric layer and the channel of a FeFET can improve device endurance (number of program / erase cycles, or PRG / ERS cycles), increase memory margin (MW) and ferroelectric polarization (2Pr), and increase on-current (Ion).

[0021] However, the formation of the titanium oxide layer increases the complexity and time of the transistor manufacturing workflow. Atomic layer deposition (ALD) is used to form the titanium oxide layer. A monolayer of titanium oxide is deposited by first forming a titanium monolayer using a titanium precursor (such as high purity tetra(diethylamine)titanium(IV), tetra(dimethylamine)titanium(IV), tetra(ethylmethylamine)titanium(IV), diisopropoxybis(2,2,6,6-tetramethyl-3,5-heptanedione)titanium(IV), isopropoxytitanium(IV) or titanium tetrachloride) by chemical vapor deposition. Titanium deposition by CVD is self-limiting to produce a monolayer of titanium. Ozone treatment is then performed to oxidize the titanium monolayer, followed by a nitrogen purge. This ALD cycle of titanium monolayer deposition, ozone treatment, and nitrogen purge is repeated to form each successive monolayer of titanium oxide until the final titanium oxide layer of the desired thickness is obtained. As a result, ALD deposition of titanium oxide is costly and time-consuming due to low deposition rates (due to many ALD cycles providing monolayer-by-monolayer deposition) and difficulty controlling the titanium to oxygen (Ti-O) ratio, which significantly impacts transistor performance.

[0022] In the embodiments disclosed herein, different methods are used to form a titanium oxide layer (or other metal oxide interface layer) for a TFT, FeFET, or other transistor. In this method, a titanium layer is formed by physical vapor deposition (PVD), and then the titanium layer is converted into a titanium oxide layer. In a suitable method, a titanium layer is formed by PVD and then exposed to ozone or ozone plasma. Advantageously, this only requires a cycle, i.e., a single titanium layer (or other metal layer) is deposited by PVD and then oxidized by exposure to ozone or ozone plasma. Such a simple process is possible because the physical vapor deposition of titanium is not limited to a monolayer of titanium. Instead, a thicker titanium layer (compared to a titanium monolayer obtained in a single ALD cycle) can be deposited by physical vapor deposition (thickness is controlled by controlling the PVD deposition time), followed by ozone or ozone plasma exposure, and the thicker titanium layer is oxidized to provide a final titanium oxide interface layer. In addition, the Ti-O ratio can be precisely controlled by controlling the time of ozone or ozone plasma exposure.

[0023] Reference Figure 1, schematically illustrates a side cross-sectional view of an exemplary ferroelectric field effect transistor (FeFET) 10 that advantageously utilizes a titanium oxide interfacial layer formed as disclosed herein. The exemplary FeFET 10 includes a gate 12, a ferroelectric layer 14, and a channel 16. In this exemplary embodiment, the channel 16 includes a bilayer stack including a first channel layer 17 and a second channel layer 18. A first titanium oxide layer 20 is disposed between the ferroelectric layer 14 and the channel 16 and in contact with each thereof. A second titanium oxide layer 22 is disposed between the ferroelectric layer 14 and the gate 12 and in contact with each thereof. The FeFET 10 also includes a source region including a conductive metal oxide 24, a barrier metal 26, and a source electrode 28; and a drain region including a conductive metal oxide 30, a barrier metal 32, and a drain electrode 34. A dielectric material 36 is disposed over the channel 16, and a dielectric material 38 is disposed outside the source and drain regions.

[0024] Reference Figure 2 , showing Figure 1 1 is a simplified top view of an exemplary FeFET 10, comprising: a channel 16; a source region comprising a conductive metal oxide 24, a barrier metal 26, and a source electrode 28; a drain region comprising a conductive metal oxide 30, a barrier metal 32, and a drain electrode 34; and a dielectric material 36 disposed on the channel 16. Figure 2 Also indicated are the channel length Ch_L, channel width Ch_W, source / drain length EL_L, and source / drain width Ch_W. In some non-limiting exemplary embodiments, the channel length Ch_L may be in the range of 3 nm to 1,000 nm; the channel width Ch_W may be in the range of 100 nm to 10,000 nm; the electrode length EL_L may be in the range of 30 nm to 10,000 nm; and the electrode width EL_W may be in the range of 100 nm to 10,000 nm. It should be understood that these are non-limiting exemplary embodiment ranges, and other ranges may be used depending on factors such as the technology node and the specific integrated circuit (IC) design.

[0025] The ferroelectric layer 14 is made of ferroelectric material, such as Hf x Zr 1-x O2, where 0≤x≤1, or more generally, hafnium oxide (Hf2) doped with an element A such as zirconium, silicon, aluminum, yttrium, gadolinium, lanthanum, strontium, scandium, titanium or tantalum. x A 1-x O2), and similarly, 0≤x≤1. These are just some non-limiting exemplary embodiments, and other types of ferroelectric materials can also be considered for the ferroelectric layer 14.

[0026] In the embodiment shown, the channel 16 includes a schematic double-layer stack of a first channel layer 17 and a second channel layer 18. In some non-limiting exemplary embodiments, the first channel layer 17 can be indium zinc oxide (IZO) and the second channel layer 18 can be indium gallium zinc oxide (InGaZnO), with IZO serving as the primary electron transport layer. This is merely an illustrative example, and more generally, the channel 16 can include one or more layers of conductive metal oxides, such as ZnO, InO, SnO, InSnO (ITO), fluorine-doped tin oxide (FTO), and the like. Other contemplated materials for the channel 16 include one or more layers including InP, GaP, GaN, GaSb, GaAs, AlAs, InAs, InSb, AlGaAs, Si, Ge, SiGe, InGaZnO, InO x 、GaZnO x 、InGaSnO x , GaInAs, GaInP, InAlAs, InGaAs, AlInGaP, SnO x Etc. Again, these are merely non-limiting illustrative examples.

[0027] Some suitable materials for the conductive metal oxide 24 of the source region and the conductive metal oxide 30 of the drain region include ZnO, InO, IZO, InSnO, x (ITO) or InGaZnO with high electron carrier concentration. Some suitable materials for the barrier metal 26 in the source region and the barrier metal 32 in the drain region include TiN, WCN, WN, Ta, TaN, Co, CoSi x Etc. Again, these are just some non-limiting illustrative examples.

[0028] The gate 12, source 28, and drain 34 are suitably made of a conductive material, such as tungsten (W), titanium nitride (TiN), copper (Cu), aluminum (Al), gold (Au), platinum (Pt), etc. Again, these are merely some non-limiting illustrative examples; furthermore, different gates 12, sources 28, and drains 34 may generally be made of different materials.

[0029] The dielectric material 36 disposed over the channel 16 may include, for example, a low-k dielectric material such as AlO. x , SiO2, aC, Si3N4, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), etc. Dielectric material 38 disposed outside the source and drain regions may be the same material as dielectric material 36, or may be a different dielectric material.

[0030] In the illustrative examples herein, the interfacial metal oxide layers 20 and 22 are titanium oxide layers, sometimes also denoted herein as TiOx Layers (where x represents the titanium-oxygen ratio, i.e., the Ti-O ratio, e.g., TiO2 has a stoichiometric Ti-O ratio of 1:2). However, more generally, the interfacial metal oxide layers 20 and 22 may include an oxide of another type of metal, such as hafnium (Hf), zirconium (Zr), niobium (Nb), or cerium (Ce).

[0031] Reference Figure 1 , a process 40 for forming each titanium oxide layer 20 and 22 is also schematically depicted in the figure. The process 40 includes an optional initial ozone or ozone plasma exposure 42 of a first layer on which titanium oxide is to be formed (e.g., for forming titanium oxide layer 20, the first layer is ferroelectric layer 14; or for forming titanium oxide layer 22, the first layer is the layer of gate 12). This is followed by deposition 44 of a titanium layer on the first layer by physical vapor deposition. The titanium layer is then exposed to ozone or ozone plasma 46. The duration of the initial ozone or ozone plasma exposure 42 is time interval T1. The duration of the deposition 44 of the titanium layer is time interval T2. The duration of the subsequent ozone or ozone plasma exposure 46 is time interval T3.

[0032] Advantageously, process 40 has a number of process variables that collectively control the thickness and Ti-O ratio of the resulting titanium oxide layer 20 or 22. These process variables include (but are not necessarily limited to): time intervals T1, T2, and T3; the titanium deposition rate of deposition 44; the ozone or ozone plasma flow rate or partial pressure of exposure 42; and the process temperature. Because titanium deposition 44 by physical vapor deposition is not a self-limiting process, for a given titanium deposition rate R (in angstroms per second), the thickness of the resulting titanium layer is R×T2. For a given ozone or ozone plasma flow rate or partial pressure, the Ti-O ratio can also be continuously controlled by time interval T3 (and perhaps to a lesser extent by time interval T1) and the thickness of the titanium layer deposited during deposition 44.

[0033] Also advantageously, process 40 includes only a single cycle, namely, an optional ozone or ozone plasma exposure 42, followed by titanium layer deposition 44, followed by ozone or ozone plasma exposure 46. That is, forming a titanium oxide layer on the first layer in deposition 44 does not include depositing another titanium layer after exposing the titanium layer to ozone or ozone plasma 46. In contrast, forming a titanium oxide layer by atomic layer deposition (ALD) would require N cycles, where N is the number of monolayers comprising the titanium oxide layer, and each cycle would include the self-limiting formation of a single titanium monolayer by CVD (thus, there would be N titanium depositions in an N-cycle ALD process).

[0034] As previously mentioned, in the exemplary embodiment, metal oxide layers 20 and 22 are titanium oxide layers. More generally, each of these layers may include another metal oxide, such as hafnium oxide (HfO x ), zirconium oxide (ZrO x ), niobium oxide (NbO x ) or cerium oxide (CeO x ). For these further non-limiting embodiments, depositing 44 suitably deposits a hafnium (Hf) layer, a zirconium (Zr) layer, a niobium (Nb) layer, or a cerium (Ce) layer, respectively.

[0035] Reference Figure 3 and Figures 4A-4D , describes a method suitable for making Figure 1 and Figure 2 The method of the FeFET 10 is shown. Figure 3 shows a flow chart of the method, and Figure 4A 、 4B 4C and 4D schematically show the Figure 3 16. A side cross-sectional view of a FeFET being fabricated at successive stages of the workflow of FIG. 16. In operation S1, a layer stack is formed, including the layers of gate 12, ferroelectric layer 14, channel 16, and first dielectric layer 36a (which will eventually form the lower portion of dielectric material 36 located above channel 16). The resulting layer stack is shown in FIG. Figure 4A Please note that Figure 4A The channel 16 is shown to comprise a double layer stack of a lower channel layer 17 and an upper channel layer 18; however, subsequent Figures 4B-4D Only the channel 16 is shown without being subdivided into a schematic two-layer stack. The deposition of each of the gate 12 layers, the ferroelectric layer 14, the channel 16, and the first dielectric layer 36a can use any deposition technique suitable for depositing the material of that layer, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma deposition, etc.

[0036] In the formation of the first titanium oxide layer 20, the titanium oxide layer 20 is disposed between the ferroelectric layer 14 and the channel 16 and in contact with both, and is preferably formed using a Figure 1 The process 40 shown is formed by: optional ozone or ozone plasma exposure 42 of the ferroelectric layer 14, followed by deposition of a titanium layer on the ferroelectric layer 14 by physical vapor deposition, followed by exposure 46 of the titanium layer to ozone or ozone plasma to oxidize the titanium layer to form TiO x .

[0037] The second titanium oxide layer 22 disposed between and in contact with the ferroelectric layer 14 and the gate 12 can also be formed using a method such as Figure 1The process 40 shown is an optional ozone or ozone plasma exposure 42 of the gate 12 layer, followed by deposition of a titanium layer on the gate 12 layer by physical vapor deposition, followed by exposure 46 of the titanium layer to ozone or ozone plasma to oxidize the titanium layer to form TiO x .

[0038] Reference Figure 3 And further refer to Figure 4B In operation S2, lithography is used to define and cut channels, producing Figure 4B The structure shown, wherein the channel 16, the titanium oxide layer 20 and the overlying first dielectric layer 36a are patterned.

[0039] Reference Figure 3 And further refer to Figure 4C In operation S3, an interlayer dielectric (IMD) deposition is performed to deposit the upper portion 36b of the overlying dielectric material 36 and the dielectric material 38, and these layers are patterned to form openings 48 corresponding to the source and drain regions. The resulting structure is as shown in FIG. Figure 4C shown.

[0040] Reference Figure 3 And further refer to Figure 4D In operation S4, U-shaped conductive metal oxide layers 24 and 30 of the source and drain regions are deposited to line the inner surface of the opening 48; then, barrier metal layers 26 and 32 of the source and drain regions are deposited on the corresponding conductive metal oxide layers 24 and 30. The U-shaped tunneling layer provides lateral electron migration. The remaining portion of the opening 48 is then filled with tungsten or other conductive materials (such as TiN, Cu, Al, Au, Pt, etc.) to form the source 28 and drain 34. The formation of the source 28 and drain 34 may overfill the opening 48, so a final chemical mechanical polishing (CMP) operation S5 is performed to flatten the surface of the FeFET, thereby producing a FeFET as shown in FIG. Figure 4D The final FeFET shown.

[0041] According to Figure 3 and Figures 4A-4D The process flow manufacturing has reference Figure 1 and Figure 2 The FeFET test device of the structure described above. In the FeFET test device, the ferroelectric layer is Hf 0.5 Zr 0.5O2 (HZO) with a thickness of approximately 75-80 angstroms; the first channel layer 17 is InZnO (IZO) and the second channel layer 18 is InGaZnO, with a total channel thickness ranging from approximately 35-50 angstroms. These FeFET test devices were fabricated using different variable values ​​of process 40 for forming titanium oxide layers 20 and 22. When fabricating the FeFET test devices, the time interval T1 of the first ozone exposure 42 is in the range of 0.1 seconds to 30 seconds; the time interval T3 of the second ozone exposure 46 is in the range of 0.1 seconds to 30 seconds; the deposition temperature range is approximately 150°C to 500°C; and the time interval T2 of the titanium layer deposition is sufficient to produce a titanium layer with a thickness ranging from approximately 0.1 angstroms to approximately 30 angstroms (where the sub-monolayer thickness value corresponds to a small fraction of a monolayer).

[0042] The test results show that a lower temperature for forming the titanium oxide layer 20 and a shorter time interval T3 of the second ozone exposure 46 can result in a larger memory margin (MW) of up to about 1 volt and a higher thermal conductivity of about 15 μC / cm 2 The results show that the 2Pr value is higher and the FeFET durability value is greater than 1 million cycles. It is found that reducing the second ozone exposure time interval T3 from 9 seconds to 3 seconds mainly increases Ion. Table 1 summarizes the tuning rules derived from the FeFET test device.

[0043] Table 1

[0044]

[0045] For FeFETs, higher MW and 2Pr values ​​are desirable, as are higher Ion and greater durability. Based on the results from the FeFET test setup, the preferred thickness range for the PVD-deposited titanium layer is approximately 0.1 angstroms to 10 angstroms, and the preferred deposition temperature is 300°C or less. The time interval T1 of the first ozone exposure 42 was observed to be at least 3 seconds. The time interval T3 of the second ozone exposure 46 was observed to be in the range of approximately 1 second to approximately 6 seconds to improve Ion.

[0046] It should be noted that although the FeFET test device is designed for Figure 1 and Figure 2 The specific FeFET configuration shown, but Figure 1 These optimal process variable value ranges for process 40 may be optimized differently for other types of FeFET transistor configurations and different TFT transistors. For a given transistor design, the controllable variables (e.g., time intervals T1, T2, and T3, and titanium oxide formation temperature) can be directly optimized by fabricating a test device with a matrix of these parameter values ​​and performing measurements of relevant device parameters (e.g., Ion, MW, 2Pr, and durability).

[0047] In addition, to test Figure 1 The composition of the titanium oxide film produced by process 40 is shown. X-ray photoelectron spectroscopy (XPS) of the titanium oxide layer deposited on silicon dioxide was performed, and the results showed that process 40 can be adjusted to form a stoichiometric TiO2 layer.

[0048] refer to Figures 5 to 11 , schematically illustrating the benefits of using Figure 1 Some examples of FeFET and TFT transistors are shown in Figure 40. Each exemplary transistor is formed on a substrate 49 and includes a gate G, a source S, a drain D, and a channel 16. The gate G, the source S, and the drain D are suitably made of a conductive material, such as tungsten (W), titanium nitride (TiN), copper (Cu), aluminum (Al), gold (Au), platinum (Pt), etc. Again, these are only non-limiting examples; in addition, different gates G, sources S, and drains D can generally be made of different materials. The channel 16 may generally include any suitable carrier transport material, such as indium gallium zinc oxide (IGZO), Si, Ge, C, SiC, SiGe, SiGeC, GaAs, InP, GaP, GaN, GaSb, GaAs, AlAs, InAs, InSb, AlGaAs, GaInAs, GaInP, InAlAs, InGaAs, AlInGaP, CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, PbS, PbTe, HgTe, etc. These are just some non-limiting examples, and other types of channel materials may also be used for the channel 16.

[0049] Reference Figure 5 , schematically illustrating a bottom gate thin film transistor (TFT) 50. The bottom gate TFT 50 includes a bottom gate dielectric layer 52, which may include, for example, silicon dioxide (SiO2) or a high-k dielectric material such as HfO2, zirconium-doped HfO2, aluminum-doped HfO2, etc. These are only some non-limiting examples, and other types of high-k dielectric materials may also be used for the bottom gate dielectric layer 52. The titanium oxide layer 54 is disposed between the channel 16 and the gate dielectric layer 52 and contacts both, and thus functionally corresponds to Figure 1 and Figure 2 The titanium oxide layer 20 of the FeFET. Another titanium oxide layer 56 is configured between the channel 16 and the source S and contacts both, while another titanium oxide layer 58 is configured between the channel 16 and the drain D and contacts both. Each titanium oxide layer 54, 56 and 58 can be used Figure 1 The schematically depicted process 40 is formed.

[0050] Reference Figure 6, schematically illustrating a bottom gate ferroelectric field effect transistor (FeFET) 60. The bottom gate FeFET 60 includes a bottom ferroelectric layer 62, which includes a ferroelectric material, such as Hf x Zr 1-x O2, where 0≤x≤1, or hafnium oxide (Hf) doped with an element A (such as zirconium, silicon, aluminum, yttrium, gadolinium, lanthanum, strontium, scandium, titanium or tantalum) x A 1-x O2), and similarly, 0≤x≤1. These are just some non-limiting examples, and other types of ferroelectric materials can also be used for the ferroelectric layer 62. The titanium oxide layer 64 is disposed between the channel 16 and the bottom ferroelectric layer 62 and contacts both, thus functionally corresponding to Figure 1 and Figure 2 The titanium oxide layer 20 of the FeFET. Another titanium oxide layer 66 is configured between the channel 16 and the source S and contacts both, while another titanium oxide layer 68 is configured between the channel 16 and the drain D and contacts both. Each titanium oxide layer 64, 66 and 68 can be used Figure 1 The schematically depicted process 40 is formed.

[0051] Reference Figure 7 , showing a top gate thin film transistor (TFT) 70. The top gate TFT 70 includes a top gate dielectric layer 72, which is configured on the channel 16 and can include, for example, SiO2 or a high dielectric constant (high-k) dielectric material such as HfO2, zirconium-doped HfO2, aluminum-doped HfO2, etc. These are just some non-limiting examples, and other types of high dielectric constant dielectric materials can also be used for the top gate dielectric layer 72. A titanium oxide layer 74 is configured between the channel 16 and the gate dielectric layer 72 and contacts both. The titanium oxide layer 74 also extends between the source S and the gate dielectric layer 72 and contacts both. The titanium oxide layer 74 also extends between the drain D and the gate dielectric layer 72 and contacts both. The titanium oxide layer 74 can be used Figure 1 The schematically depicted process 40 is formed.

[0052] Reference Figure 8 , showing a top gate ferroelectric field effect transistor (FeFET) 80. The top gate FeFET 80 includes a top ferroelectric layer 82, which is disposed on the channel 16 and includes a ferroelectric material, such as Hf x Zr 1-x O2, where 0≤x≤1, or hafnium oxide doped with element A (Hf x A 1-xO2), element A such as zirconium, silicon, aluminum, yttrium, gadolinium, lanthanum, strontium, scandium, titanium or tantalum, and similarly, 0≤x≤1. These are just some non-limiting examples, and other types of ferroelectric materials can also be used for the ferroelectric layer 82. The titanium oxide layer 84 is configured between the channel 16 and the ferroelectric layer 82 and contacts both. The titanium oxide layer 84 also extends between the source S and the ferroelectric layer 82 and contacts both. The titanium oxide layer 84 also extends between the drain D and the ferroelectric layer 82 and contacts both. The titanium oxide layer 84 can be used Figure 1 The schematically depicted process 40 is formed.

[0053] Reference Figure 9 , showing a dual-gate thin film transistor (TFT) 90. The dual-gate TFT 90 includes a top layer 92 configured on the channel 16 and a bottom layer 94 configured below the channel 16. The top layer 92 and the bottom layer 94 can, for example, include SiO2 or a high dielectric constant gate dielectric material such as HfO2, zirconium-doped HfO2, aluminum-doped HfO2, etc. These are just some non-limiting examples, and other types of high dielectric constant dielectric materials can also be used for layers 92 and 94. The top layer 92 is contacted by the top gate TG and the bottom layer 94 is contacted by the bottom gate BG. At the device level, the top gate TG and the bottom gate BG can be selectively electrically connected. A titanium oxide layer 96 is configured between the channel 16 and the layer 94 of the bottom gate and contacts both. Another titanium oxide layer 98 is configured between the channel 16 and the layer 92 of the top gate and contacts both. The titanium oxide layer 98 also extends above the source S and extends above the drain D. The titanium oxide layers 96 and 98 can each be used Figure 1 The schematically depicted process 40 is formed.

[0054] Reference Figure 10 , showing a dual-gate ferroelectric field effect transistor (FeFET) 100. The dual-gate FeFET 100 includes a top ferroelectric layer 102 disposed on a channel 16 and a bottom ferroelectric layer 104 disposed below the channel 16. The top ferroelectric layer 102 and the bottom ferroelectric layer 104 each include a ferroelectric material, such as Hf x Zr 1-x O2, where 0≤x≤1, or hafnium oxide doped with element A (Hf x A 1- xO2), where A can be zirconium, silicon, aluminum, yttrium, gadolinium, lanthanum, strontium, scandium, titanium or tantalum, and similarly, 0≤x≤1. These are just some non-limiting examples, and other types of ferroelectric materials can also be used for the ferroelectric layers 102 and 104. The top ferroelectric layer 102 is contacted by the top gate TG, and the bottom ferroelectric layer 104 is contacted by the bottom gate BG. At the device level, the top gate TG and the bottom gate BG can be selectively electrically connected. A titanium oxide layer 106 is configured between the channel 16 and the bottom ferroelectric layer 104 and contacts both. Another titanium oxide layer 108 is configured between the channel 16 and the top ferroelectric layer 102 and contacts both. The titanium oxide layer 108 also extends above the source S and extends above the drain D. The titanium oxide layers 106 and 108 can each be used Figure 1 The schematically depicted process 40 is formed.

[0055] Reference Figure 11 , shows a three-dimensional (3D) or vertical device 110, which can be a thin film transistor (TFT) or a ferroelectric field effect transistor (FeFET). Device 110 includes a 3D or vertical channel 16, which is supported on one side by an oxide 112. Layer 114 is disposed over the top and sides of channel 16, wherein a titanium oxide layer 116 is disposed between channel 16 and layer 114 and contacts each. In embodiments where device 110 is a TFT, layer 114 suitably includes a gate dielectric layer such as SiO2 or a high dielectric constant (high-k) dielectric material such as HfO2, zirconium-doped HfO2, aluminum-doped HfO2, etc. These are only some non-limiting examples, and other types of high dielectric constant dielectric materials can also be used for layer 114. In embodiments where device 110 is a FeFET, layer 114 is suitably a ferroelectric material such as Hf x Zr 1-x O2, where 0≤x≤1, or hafnium oxide doped with element A (Hf x A 1-x O2), where A can be zirconium, silicon, aluminum, yttrium, gadolinium, lanthanum, strontium, scandium, titanium or tantalum, and similarly, 0≤x≤1. These are just some non-limiting examples, and other types of ferroelectric materials can also be considered. The titanium oxide layer 116 can be made of Figure 1 The schematically depicted process 40 is formed.

[0056] More generally, for various device embodiments employing one or more titanium oxide interfacial layers, wherein Figure 1-2 and Figure 5-11 The gate dielectric layer or ferroelectric layer (e.g., the ferroelectric layer 14, 62, 82, 102, 104, 114 or the gate dielectric layer 52, 72, 92, 94, 114 in the various non-limiting example embodiments described herein) may include HfO x 、ZrO x 、LaHfOx , LaHfZrO, La2O3, HfSiO, HfAlO, HfNO, ErTiO5, SrTiO3, LaScO3, LaAlO3, GdScO3, LaLuO3, La2Hf2O7, Gd2O3, La2SiO5, SrHfO3, Ce-O x 、BeO x 、InO x 、GaO x 、AlO x 、SnO x , VO x , WO x 、TiO x 、ZrO x 、NbO x , HfO x 、SiO x or TaO x . The channel can generally include any suitable carrier transport material, such as indium gallium zinc oxide (IGZO), Si, Ge, C, SiC, SiGe, SiGeC, GaAs, InP, GaP, GaN, GaSb, GaAs, AlAs, InAs, InSb, AlGaAs, GaInAs, GaInP, InAlAs, InGaAs, AlInGaP, CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, PbS, PbTe, HgTe, etc. Although a titanium oxide interfacial layer is described by way of example, more generally, the interfacial layer can be a metal oxide interfacial layer formed by depositing a metal layer by physical vapor deposition (PVD) and converting the metal layer into a metal oxide layer. For example, the metal oxide layer can be formed by optional ozone or ozone plasma exposure, followed by PVD deposition of a metal layer, and then ozone or ozone plasma exposure of the metal layer. The metal layer may be, for example, a hafnium (Hf) layer, a zirconium (Zr) layer, a niobium (Nb) layer, a cerium (Ce) layer, or the like.

[0057] The disclosed transistors may be used in substantially any type of transistor circuit, such as, by way of non-limiting example embodiments, dynamic random access memory (DRAM) circuits, static random access memory (SRAM) circuits, FeRAM 1T-1C ferroelectric capacitor structures, and / or the like.

[0058] Some further embodiments are described below.

[0059] In a non-limiting exemplary embodiment, a method for manufacturing a ferroelectric field effect transistor (FeFET) includes: forming a first layer, wherein the first layer is one of a ferroelectric layer and a channel of the FeFET; depositing a metal layer on the first layer by physical vapor deposition, and then exposing the metal layer to ozone or ozone plasma to form a metal oxide layer on the first layer; and forming a second layer on the metal oxide layer, wherein the second layer is the other of the ferroelectric layer and the channel of the FeFET.

[0060] In one embodiment, forming the first metal oxide layer further comprises: exposing the first layer to ozone or ozone plasma before depositing the first metal layer.

[0061] In one embodiment, the first metal layer is a titanium layer.

[0062] In one embodiment, the thickness of the first metal layer is less than or equal to 10 angstroms.

[0063] In one embodiment, the first metal layer is exposed to ozone or ozone plasma for a time period ranging from 0.1 seconds to 30 seconds.

[0064] In one embodiment, the step of forming the first metal oxide layer is performed at a temperature of 300° C. or lower.

[0065] In one embodiment, forming the first metal oxide layer on the first layer does not include depositing another metal layer after exposing the first metal layer to ozone or ozone plasma.

[0066] In one embodiment, the first layer is the first ferroelectric layer of the FeFET, and the second layer is the channel of the FeFET.

[0067] In one embodiment, the first ferroelectric layer is Hf x Zr 1-x O2, where 0≤x≤1, or doped hafnium oxide (Hf x A 1-x O2), wherein 0≤x≤1, and element A is selected from the group consisting of zirconium, silicon, aluminum, yttrium, gadolinium, lanthanum, strontium, scandium, titanium and tantalum.

[0068] In one embodiment, the method further includes: forming a gate before forming the first ferroelectric layer of the FeFET; and before forming the first ferroelectric layer of the FeFET, depositing a second metal layer on the gate by physical vapor deposition, and then exposing the second metal layer to ozone or ozone plasma to form a second metal oxide layer on the gate.

[0069] In one embodiment, the method further comprises depositing a metal layer on the channel of the FeFET by physical vapor deposition, and then exposing the first metal layer to ozone or ozone plasma to form a second metal oxide layer on the channel.

[0070] In one embodiment, the method further includes forming a source region and a drain region of the FeFET on the second metal oxide layer.

[0071] In one embodiment, the method further includes: forming a second ferroelectric layer on the second metal oxide layer.

[0072] In one embodiment, the first layer is the channel of the FeFET, and the second layer is the first ferroelectric layer of the FeFET.

[0073] In one embodiment, the first metal oxide layer is formed on the top and sides of the channel.

[0074] In a non-limiting exemplary embodiment, a ferroelectric field-effect transistor (FeFET) includes a ferroelectric layer, a channel, and a titanium oxide layer disposed between and in contact with the ferroelectric layer and the channel, wherein the FeFET has an on-state current (Ion) of at least 50 microamperes per micrometer.

[0075] In one embodiment, the device further comprises: a gate; and a second titanium oxide layer disposed between the ferroelectric layer and the gate and in contact with the gate and the second titanium oxide layer.

[0076] In a non-limiting exemplary embodiment, a method for fabricating a ferroelectric field-effect transistor includes: forming a ferroelectric layer; depositing a titanium layer on the ferroelectric layer by physical vapor deposition, and then exposing the titanium layer to ozone or ozone plasma to form a titanium oxide layer on the ferroelectric layer; and forming a channel layer on the titanium oxide layer. In some such embodiments, the method further includes forming a gate electrode, depositing a titanium layer on the gate electrode by physical vapor deposition, and then exposing the titanium layer to ozone or ozone plasma to form a titanium oxide layer on the gate electrode; wherein the ferroelectric layer is formed on the titanium layer formed on the gate electrode. In some embodiments, when forming the titanium oxide layer on the ferroelectric layer: the titanium layer deposited on the ferroelectric layer by physical vapor deposition has a thickness of 30 angstroms or less; the exposure time of the titanium layer deposited on the ferroelectric layer to ozone or ozone plasma is in the range of 0.1 seconds to 30 seconds; and the process of forming the titanium oxide layer on the ferroelectric layer is performed at a temperature of 300°C or less.

[0077] In a non-limiting exemplary embodiment, a method for manufacturing a transistor includes: forming a first layer, the first layer being one of a gate dielectric layer and a channel of the transistor; depositing a metal layer on the first layer by physical vapor deposition, and then exposing the metal layer to ozone or ozone plasma to form a metal oxide layer on the first layer; and forming a second layer on the metal oxide layer, wherein the second layer is the other of the gate dielectric layer and the channel of the transistor. Forming the metal oxide layer further includes: exposing the first layer to ozone or ozone plasma before depositing the metal layer. The metal layer may be a titanium layer.

[0078] In a non-limiting exemplary embodiment, a method for manufacturing a device includes forming a first layer. When the device is a FeFET, the first layer may be a ferroelectric layer, or when the device is a transistor, the first layer may be a gate dielectric layer. Alternatively, the first layer may be a channel of the device. A metal layer is deposited on the first layer by physical vapor deposition to form a metal oxide layer on the first layer, and then the metal layer is exposed to ozone or ozone plasma. A second layer is formed on the metal oxide layer. Forming the metal oxide layer may further include exposing the first layer to ozone or ozone plasma before depositing the metal layer. The metal layer may be a titanium layer.

[0079] The features of several embodiments have been summarized above so that those skilled in the art may better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use this disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for manufacturing a ferroelectric field effect transistor, characterized in that: include: forming a first layer, the first layer being one of a first ferroelectric layer and a channel of the ferroelectric field effect transistor; depositing a first metal layer on the first layer by physical vapor deposition, and then exposing the first metal layer to ozone or ozone plasma to form a first metal oxide layer on the first layer; as well as A second layer is formed on the first metal oxide layer, wherein the second layer is the other of the first ferroelectric layer and the channel of the ferroelectric field effect transistor.

2. The method according to claim 1, characterized in that The forming of the first metal oxide layer further comprises: exposing the first layer to ozone or ozone plasma before depositing the first metal layer.

3. The method according to claim 1, characterized in that The first metal layer is a titanium layer.

4. The method according to claim 1, wherein The thickness of the first metal layer is less than or equal to 10 angstroms.

5. The method according to claim 1, wherein The first metal layer is exposed to ozone or ozone plasma for a time ranging from 0.1 seconds to 30 seconds.

6. The method according to claim 1, characterized in that The step of forming the first metal oxide layer is performed at a temperature of 300° C. or lower.

7. A ferroelectric field effect transistor, characterized in that: include: ferroelectric layer; aisle; as well as a first titanium oxide layer disposed between the ferroelectric layer and the channel and in contact with the ferroelectric layer and the channel; The ferroelectric field effect transistor has an on-state current of at least 50 microamperes per micrometer.

8. The ferroelectric field effect transistor according to claim 7, wherein: Further including: gate; as well as The second titanium oxide layer is disposed between the ferroelectric layer and the gate and is in contact with the gate and the second titanium oxide layer.

9. A method for manufacturing a transistor, characterized in that: include: forming a first layer, the first layer being one of a gate dielectric layer and a channel of the transistor; forming a metal oxide layer on the first layer by depositing a metal layer on the first layer by physical vapor deposition and then exposing the metal layer to ozone or ozone plasma; as well as A second layer is formed on the metal oxide layer, wherein the second layer is the other of the gate dielectric layer and the channel of the transistor.

10. The method according to claim 9, characterized in that The forming of the metal oxide layer further comprises: exposing the first layer to ozone or ozone plasma before depositing the metal layer.

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