Semiconductor device and semiconductor device control method

Abstract

The embodiment of the invention relates to a semiconductor device and a control method of the semiconductor device. According to one embodiment, a semiconductor device includes: a first electrode; a second electrode; a transistor including an n-type first semiconductor region provided between the first electrode and the second electrode, a p-type second semiconductor region provided between the first semiconductor region and the first electrode, an n-type third semiconductor region provided between the second semiconductor region and the first electrode, and a gate electrode; a detector that detects the voltage of the first electrode or the current flowing from the first electrode to the second electrode in a state where the voltage of the first electrode is a positive voltage higher than the voltage of the second electrode; a comparison circuit that compares a measurement value measured by the detector with a first threshold value; and a gate driver circuit that applies a first positive voltage higher than the threshold voltage of the transistor to the gate electrode, and that applies a first negative voltage to the gate electrode when the measured value exceeds the first threshold value as a result of the comparison by the comparison circuit.

Description

[0001]

Citation of related applications

[0002] This application is based on Japanese Patent Application No. 2024-029014 (filing date: February 28, 2024) and claims the benefit of priority from that application, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device and a method for controlling the semiconductor device. Background Art

[0004] Silicon carbide is an example of a material for next-generation semiconductor devices. Compared to silicon, silicon carbide has excellent physical properties, including a band gap three times greater, a breakdown electric field strength approximately 10 times greater, and a thermal conductivity approximately three times greater. Utilizing these properties, for example, it is possible to realize MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) with high withstand voltage, low loss, and high-temperature operation.

[0005] Vertical MOSFETs using silicon carbide have a pn junction diode as a built-in diode. For example, MOSFETs are used as switching elements connected to inductive loads. In this case, the built-in diode allows return current to flow even when the MOSFET is off.

[0006] Sometimes, a large surge current flows through the MOSFET, exceeding the steady state momentarily. When a large surge current flows, the MOSFET heats up and breaks down. The maximum allowable peak current value (I FSM ) is also called surge current withstand capacity. In MOSFET, it is desired to improve the surge current withstand capacity. Summary of the Invention

[0007] An object of the present invention is to provide a semiconductor device having improved surge current tolerance.

[0008] A semiconductor device according to an embodiment comprises: a first electrode; a second electrode; a transistor including an n-type first semiconductor region disposed between the first electrode and the second electrode and electrically connected to the second electrode, a p-type second semiconductor region disposed between the first semiconductor region and the first electrode and electrically connected to the first electrode, an n-type third semiconductor region disposed between the second semiconductor region and the first electrode and electrically connected to the first electrode, and a gate electrode facing the second semiconductor region; a detector for detecting the voltage of the first electrode or the current flowing from the first electrode to the second electrode when the voltage of the first electrode is a positive voltage higher than the voltage of the second electrode; a comparator circuit for comparing a measurement value measured by the detector with a first threshold value in the state; and a gate driver circuit for applying a first positive voltage higher than the threshold voltage of the transistor to the gate electrode in the state, and applying a first negative voltage to the gate electrode when the measurement value exceeds the first threshold value as a result of the comparison in the comparator circuit.

[0009] According to the present invention, a semiconductor device having improved surge current tolerance can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 This is a block diagram of the semiconductor device according to the first embodiment.

[0011] Figure 2 This is a schematic cross-sectional view of the transistor according to the first embodiment.

[0012] Figure 3 This is a diagram showing a specific example of the semiconductor device according to the first embodiment.

[0013] Figure 4 It is an explanatory diagram of the control method of the semiconductor device according to the first embodiment.

[0014] Figure 5A 、 Figure 5B 、 Figure 5C 、 Figure 5D 、 Figure 5E 、 Figure 5F It is an explanatory diagram of the control method of the semiconductor device according to the first embodiment.

[0015] Figure 6 is a block diagram of a semiconductor device according to a comparative example.

[0016] Figure 7 It is an explanatory diagram of a control method of a semiconductor device according to a comparative example.

[0017] Figure 8A 、 Figure 8B 、 Figure 8C 、 Figure 8DIt is an explanatory diagram of a control method of a semiconductor device according to a comparative example.

[0018] Figure 9 It is an explanatory diagram of the operation and effect of the semiconductor device according to the first embodiment.

[0019] Figure 10 These are diagrams for explaining the operation and effects of the semiconductor device according to the first embodiment.

[0020] Figure 11 It is an explanatory diagram of the operation and effect of the semiconductor device according to the first embodiment.

[0021] Figure 12A 、 Figure 12B These are diagrams for explaining the operation and effects of the semiconductor device according to the first embodiment.

[0022] Figure 13 It is an explanatory diagram of the operation and effect of the semiconductor device according to the first embodiment.

[0023] Figure 14 This is a block diagram of a semiconductor device according to a modified example of the first embodiment.

[0024] Figure 15 It is an explanatory diagram of a control method of a semiconductor device according to a modification of the first embodiment.

[0025] Figure 16 This is a block diagram of a semiconductor device according to a second embodiment.

[0026] Figure 17 It is a schematic cross-sectional view of a transistor according to a second embodiment.

[0027] Figure 18 This is a block diagram of a semiconductor device according to a modified example of the second embodiment.

[0028] (Explanation of Symbols)

[0029] 12: Source electrode (first electrode); 14: Drain electrode (second electrode); 18: Gate electrode; 28: Drift region (first semiconductor region); 30: Main region (second semiconductor region); 34: Source region (third semiconductor region); 100: Semiconductor module (semiconductor device); 100a: Transistor; 100b: Ammeter (detector); 100c: Comparator circuit; 100d: Gate driver circuit; 100f: Voltmeter (detector); 101: Semiconductor module (semiconductor device); 200: Semiconductor module (semiconductor device); 200a: Transistor; 201: Semiconductor module (semiconductor device). DETAILED DESCRIPTION

[0030] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following description, the same or similar components may be denoted by the same reference numerals, and description of components that have been described once may be omitted as appropriate.

[0031] In addition, in the following description, n + 、n、n - and p + ,p,p - The mark indicates the relative high and low of the impurity concentration in each conductivity type. + Indicates that the n-type impurity concentration is relatively high compared to n. - Indicates that the n-type impurity concentration is relatively low compared to n. + Indicates that the p-type impurity concentration is relatively high compared to p-type. - Indicates that the p-type impurity concentration is relatively low compared to p-type. In addition, n + Type, n - Type is abbreviated as n type, and p + Type, p - The type is abbreviated as p-type.

[0032] The impurity concentration can be measured, for example, by SIMS (Secondary Ion Mass Spectrometry). Furthermore, the relative level of the impurity concentration can be determined based on the carrier concentration determined by SCM (Scanning Capacitance Microscopy). Furthermore, for example, SIMS can be used to determine the depth, thickness, and other distances of the impurity region. Furthermore, for example, the depth, thickness, width, and spacing of the impurity region can be determined based on a composite image of an SCM image and an AFM (Atomic Force Microscope) image.

[0033] In this specification, the impurity concentration of a semiconductor region means the maximum impurity concentration of the semiconductor region unless otherwise specified.

[0034] (First embodiment)

[0035] The semiconductor device of the first embodiment comprises: a first electrode; a second electrode; a transistor, including an n-type first semiconductor region arranged between the first electrode and the second electrode and electrically connected to the second electrode, a p-type second semiconductor region arranged between the first semiconductor region and the first electrode and electrically connected to the first electrode, an n-type third semiconductor region arranged between the second semiconductor region and the first electrode and electrically connected to the first electrode, and a gate electrode facing the second semiconductor region; a detector, which detects a current flowing from the first electrode to the second electrode when the voltage of the first electrode is a positive voltage higher than that of the second electrode; a comparison circuit, which compares a measurement value measured by the detector with a first threshold value in the above state; and a gate driver circuit, which applies a first positive voltage higher than the threshold voltage of the transistor to the gate electrode in the above state, and applies a first negative voltage to the gate electrode when the measurement value in the comparison circuit exceeds the first threshold value.

[0036] Figure 1 1 is a block diagram of a semiconductor device according to Embodiment 1. The semiconductor device according to Embodiment 1 is a semiconductor module 100 including a transistor 100 a using silicon carbide.

[0037] The semiconductor module 100 includes a transistor 100 a , an ammeter 100 b , a comparison circuit 100 c , and a gate driver circuit 100 d .

[0038] Figure 2 This is a schematic cross-sectional view of the transistor according to the first embodiment. Figure 2 is a cross-sectional view of the transistor 100a.

[0039] Transistor 100a is a planar-gate vertical MOSFET using silicon carbide. Transistor 100a is a double-implantation MOSFET (DIMOSFET) in which the body and source regions are formed by ion implantation, for example. Transistor 100a is a vertical n-channel MOSFET using electrons as carriers.

[0040] The transistor 100 a includes a silicon carbide layer 10 , a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate insulating layer 16 , a gate electrode 18 , and an interlayer insulating layer 20 .

[0041] In the silicon carbide layer 10, n + Type drain region 26, n - The p-type drift region 28 (first semiconductor region), the p-type body region 30 (second semiconductor region), and the n-type + Type source region 34 (third semiconductor region).

[0042] The silicon carbide layer 10 is provided between the source electrode 12 and the drain electrode 14. The silicon carbide layer 10 is provided between the gate electrode 18 and the drain electrode 14. The silicon carbide layer 10 is single-crystal SiC. The silicon carbide layer 10 is, for example, 4H-SiC.

[0043] The silicon carbide layer 10 has a first surface ( Figure 2 "P1") and Side 2 ( Figure 2 ("P2" in the figure). The first surface P1 and the second surface P2 face each other. Hereinafter, the first surface may be referred to as the front surface, and the second surface may be referred to as the back surface. In addition, the "depth" hereafter means the depth relative to the first surface.

[0044] The first plane P1 is, for example, a plane inclined at an angle of 0 to 8 degrees relative to the (0001) plane. Furthermore, the second plane P2 is, for example, a plane inclined at an angle of 0 to 8 degrees relative to the (000-1) plane. The (0001) plane is referred to as a silicon plane. The (000-1) plane is referred to as a carbon plane.

[0045] n + The type drain region 26 is provided between the source electrode 12 and the drain electrode 14. + The n-type drain region 26 is provided on the back side of the silicon carbide layer 10. The drain region 26 contains nitrogen (N) as an n-type impurity, for example. The n-type impurity concentration of the drain region 26 is, for example, 1×10 18 cm -3 Above and 1×10 21 cm -3 the following.

[0046] The drain region 26 is electrically connected to the drain electrode 14 . The drain region 26 is in contact with the drain electrode 14 .

[0047] n - The drift region 28 of the MOSFET type is provided between the drain region 26 and the first plane P1. The drift region 28 is provided between the source electrode 12 and the drain electrode 14. The drift region 28 is provided between the gate electrode 18 and the drain electrode 14.

[0048] The drift region 28 functions as a current path when the transistor 100a is in the on state. Furthermore, when the transistor 100a is in the off state, a thick depletion layer is formed in the drift region 28, thereby increasing the breakdown voltage of the transistor 100a. Furthermore, the drift region 28 functions as an n-type semiconductor region of a pn junction diode.

[0049] The drift region 28 is provided on the drain region 26. The drift region 28 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drift region 28 is lower than the n-type impurity concentration of the drain region 26. The n-type impurity concentration of the drift region 28 is, for example, 4×10 14 cm -3Above and 1×10 17 cm -3 the following.

[0050] The thickness of the drift region 28 in the direction from the source electrode 12 toward the drain electrode 14 is, for example, not less than 5 μm and not more than 150 μm. The thickness of the drift region 28 in the direction from the source electrode 12 toward the drain electrode 14 is, for example, thicker than the thickness of the drift region 28 in the direction from the source electrode 12 toward the drain electrode 14 of the body region 30. The thickness of the drift region 28 in the direction from the source electrode 12 toward the drain electrode 14 is, for example, not less than 10 times the thickness of the drift region 28 in the direction from the source electrode 12 toward the drain electrode 14 of the body region 30.

[0051] The drift region 28 is electrically connected to the drain electrode 14 .

[0052] A p-type body region 30 is provided between the drift region 28 and the first plane P1. The body region 30 is provided between the drift region 28 and the source electrode 12. A portion of the body region 30 functions as the channel region of the transistor 100a. The body region 30 functions as a p-type semiconductor region of a pn junction diode.

[0053] The body region 30 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the body region 30 is, for example, 1×10 16 cm -3 Above and 1×10 21 cm -3 the following.

[0054] The depth of the body region 30 is, for example, not less than 0.3 μm and not more than 1.0 μm.

[0055] The body region 30 is electrically connected to the source electrode 12 . The body region 30 is in contact with the source electrode 12 .

[0056] n + The source region 34 of the type is provided between the body region 30 and the first plane P1 . The source region 34 is provided between the body region 30 and the source electrode 12 .

[0057] The source region 34 contains, for example, phosphorus (P) as an n-type impurity. The n-type impurity concentration of the source region 34 is higher than the n-type impurity concentration of the drift region 28. The n-type impurity concentration of the source region 34 is, for example, 10 times or more higher than the n-type impurity concentration of the drift region 28.

[0058] The n-type impurity concentration of the source region 34 is, for example, 1×10 18 cm -3 Above and 1×10 21 cm -3The depth of the source region 34 is shallower than that of the body region 30. The depth of the source region 34 is, for example, not less than 0.1 μm and not more than 0.3 μm.

[0059] The source region 34 is electrically connected to the source electrode 12 . The source region 34 is in contact with the source electrode 12 .

[0060] The gate electrode 18 is provided on the first surface P1 side of the silicon carbide layer 10. The gate electrode 18 is provided on the silicon carbide layer 10. The gate electrode 18 has a stripe shape, for example.

[0061] The gate electrode 18 is a conductive layer and is made of, for example, polysilicon containing p-type impurities or n-type impurities.

[0062] For example, the gate electrode 18 faces a portion of the body region 30 that is in contact with the first plane P1. For example, the gate electrode 18 faces a portion of the drift region 28 that is in contact with the first plane P1.

[0063] The gate insulating layer 16 is disposed between the gate electrode 18 and the body region 30 . The gate insulating layer 16 is disposed between the gate electrode 18 and the drift region 28 .

[0064] The gate insulating layer 16 is made of, for example, silicon oxide. For example, a High-k insulating material (high dielectric constant insulating material) can be applied to the gate insulating layer 16 .

[0065] The interlayer insulating layer 20 is provided on the gate electrode 18 and the silicon carbide layer 10. The interlayer insulating layer 20 is provided between the gate electrode 18 and the source electrode 12. The interlayer insulating layer 20 is, for example, silicon oxide.

[0066] Source electrode 12 is provided on the first surface P1 side of silicon carbide layer 10. Source electrode 12 is in contact with first surface P1.

[0067] The source electrode 12 is in contact with the body region 30 and the source region 34 .

[0068] The source electrode 12 is made of metal. The metal forming the source electrode 12 is, for example, a stacked structure of titanium (Ti) and aluminum (Al).

[0069] The portion of the source electrode 12 that is in contact with the body region 30 and the source region 34 is, for example, a metal silicide, such as titanium silicide or nickel silicide.

[0070] The contact between the body region 30 and the source electrode 12 and the contact between the source region 34 and the source electrode 12 are, for example, ohmic contacts.

[0071] The drain electrode 14 is provided on the second surface P2 side of the silicon carbide layer 10 . The drain electrode 14 is in contact with the second surface P2 . The drain electrode 14 is in contact with the drain region 26 .

[0072] The drain electrode 14 is, for example, a metal or a metal semiconductor compound and includes at least one material selected from the group consisting of nickel silicide, titanium (Ti), nickel (Ni), silver (Ag), and gold (Au).

[0073] The contact between the drain region 26 and the drain electrode 14 is, for example, an ohmic contact.

[0074] like Figure 1 As shown, a pn junction diode is connected between the source electrode 12 and the drain electrode 14 of the transistor 100 a as a built-in diode.

[0075] For example, consider the case where transistor 100a is used as a switching element connected to an inductive load. When transistor 100a is in the off state, the load current generated by the inductive load may cause a positive voltage higher than the voltage at drain electrode 14 to be applied to source electrode 12. In this case, a forward current flows through the internal diode of transistor 100a. This state is also called a reverse conduction state.

[0076] When the voltage between the source electrode 12 and the drain electrode 14 exceeds the forward voltage (Vf) of the pn junction diode, a forward current flows through the pn junction diode.

[0077] The ammeter 100b is provided, for example, between the source electrode 12 and the channel region of the transistor 100a. The ammeter 100b is an example of a detector. The ammeter 100b detects the current flowing from the source electrode 12 to the drain electrode 14 when the voltage of the source electrode 12 is a positive voltage higher than the voltage of the drain electrode 14.

[0078] The comparator circuit 100c is electrically connected to the ammeter 100b and compares a value measured by the ammeter 100b with a first threshold value when the voltage of the source electrode 12 is a positive voltage higher than the voltage of the drain electrode 14 .

[0079] The value measured by the ammeter 100b is a current value. The first threshold value is a preset threshold current.

[0080] The first threshold is, for example, the maximum allowable peak current value (I FSM ) is greater than or equal to 0.6 times and less than or equal to 1.0 times. In this case, the maximum allowable peak current value (I FSM ) is the maximum allowable peak current value (I FSM ).

[0081] The comparison circuit 100c is, for example, an electronic circuit and includes, for example, hardware and software.

[0082] The comparison circuit 100c includes, for example, a central processing unit (CPU). The comparison circuit 100c includes, for example, a storage device. The storage device included in the comparison circuit 100c is, for example, a semiconductor memory. The storage device stores, for example, a first threshold value.

[0083] The gate driver circuit 100 d is electrically connected to the comparison circuit 100 c and the gate electrode 18 .

[0084] The gate driver circuit 100d applies a first positive voltage, which is higher than the threshold voltage of the transistor 100a, to the gate electrode 18 when the voltage of the source electrode 12 is a positive voltage higher than the voltage of the drain electrode 14. Furthermore, the gate driver circuit 100d applies a first negative voltage to the gate electrode 18 when the value measured by the comparison circuit 100c exceeds the first threshold.

[0085] The gate driver circuit 100d is, for example, an electronic circuit, and the comparison circuit 100c includes, for example, hardware and software.

[0086] When the comparator circuit 100c detects the current flowing from the source electrode 12 to the drain electrode 14, the delay time from when the value measured by the comparator circuit 100c exceeds the first threshold value to when the first negative voltage is applied to the gate electrode 18 is, for example, less than 2 ms (2000 μs). For example, the delay time from when the value measured by the comparator circuit 100c exceeds the first threshold value to when the gate driver circuit 100d outputs the first negative voltage to the gate electrode 18 is, for example, less than 2 ms.

[0087] Figure 3 This is a diagram showing a specific example of the semiconductor device according to the first embodiment.

[0088] The semiconductor module 100 includes a transistor 100 a , a Rogowski coil ammeter 100 ax , a comparator 100 cx , a pulse generator 100 e , and a gate driver circuit 100 d .

[0089] The Rogowski coil ammeter 100ax is an example of a detector, and the comparator 100cx is an example of a comparison circuit.

[0090] The comparator 100cx compares the value measured by the Rogowski coil ammeter 100ax with the first threshold value. The pulse generator 100e generates a pulse based on the comparison result obtained by the comparator 100cx and transmits it to the gate driver circuit 100d.

[0091] Next, a control method of the semiconductor device according to the first embodiment will be described.

[0092] A control method for a semiconductor device in a first embodiment includes a first electrode; a second electrode; and a transistor including an n-type first semiconductor region disposed between the first electrode and the second electrode and electrically connected to the second electrode, a p-type second semiconductor region disposed between the first semiconductor region and the first electrode and electrically connected to the first electrode, an n-type third semiconductor region disposed between the second semiconductor region and the first electrode and electrically connected to the first electrode, and a gate electrode facing the second semiconductor region. The method includes applying a positive voltage higher than that of the second electrode to the first electrode, applying a first positive voltage higher than a threshold voltage of the transistor to the gate electrode, detecting a current flowing from the first electrode to the second electrode, comparing the detected measured value with a first threshold value, and applying a first negative voltage to the gate electrode when the measured value exceeds the first threshold value.

[0093] Figure 4 、 Figure 5A 、 Figure 5B 、 Figure 5C 、 Figure 5D 、 Figure 5E as well as Figure 5F It is an explanatory diagram of the control method of the semiconductor device according to the first embodiment.

[0094] Figure 4 Graphs showing temporal changes in current and gate voltage of the transistor 100 a according to the first embodiment. Figure 4 FIG. 1 shows the temporal changes in current and gate voltage when the voltage of the source electrode 12 is a positive voltage higher than that of the drain electrode 14. Figure 4 , the voltage of the source electrode 12 is also shown.

[0095] exist Figure 4 In the above figure, the horizontal axis is time, and the vertical axis is current and voltage. The current is the current flowing from the source electrode 12 to the drain electrode 14. The voltage is the voltage of the source electrode 12. In addition, the voltage of the source electrode 12 is, for example, the potential difference between the potential of the source electrode 12 and the reference potential. The reference potential is, for example, 0V. Figure 4 In the figure above, the solid line represents the current and the dotted line represents the voltage.

[0096] exist Figure 4 In the figure below, the horizontal axis represents time and the vertical axis represents gate voltage. The gate voltage is the voltage applied to the gate electrode 18. The gate voltage is, for example, the potential difference between the potential of the gate electrode 18 and a reference potential. The reference potential is, for example, 0V.

[0097] Figure 5A 、 Figure 5B 、 Figure 5C 、 Figure 5D 、 Figure 5E as well as Figure 5F It is shown in Figure 4 Schematic diagram of current flowing in transistor 100a during each time period shown. In the figure, solid arrows represent unipolar currents, and dashed arrows represent bipolar currents.

[0098] In the following description, for example, transistor 100a is used as a high-side transistor in one arm of a three-phase inverter circuit performing synchronous rectification. Specifically, consider a case where, when transistor 100a is in the off state, a load current flowing from an inductive load causes a positive voltage to be applied to source electrode 12 relative to drain electrode 14. In other words, consider a case where the source voltage of source electrode 12 is a higher positive voltage than the drain voltage of drain electrode 14.

[0099] During the period from time t0 to time t1, a gate voltage Vg lower than the threshold voltage of transistor 100a is applied to gate electrode 18. During the period from time t0 to time t1, for example, a negative gate voltage Vg is applied to gate electrode 18. During the period from time t0 to time t1, a negative voltage is applied to gate electrode 18. Gate voltage Vg is, for example, -15V.

[0100] The gate driver circuit 100 d applies a gate voltage Vg to the gate electrode 18 .

[0101] During the period from time t0 to time t1, the gate voltage Vg is lower than the threshold voltage of the transistor 100a. Figure 5A As shown, no inversion layer is formed in the channel region of transistor 100a, and no current flows in the channel region. Furthermore, during the period from time t0 to time t1, for example, the voltage between source electrode 12 and drain electrode 14 is lower than the forward voltage (Vf) of the pn junction diode built into transistor 100a, and therefore no current flows in the pn junction diode.

[0102] In a three-phase inverter circuit performing synchronous rectification, it is necessary to prevent shoot-through current from flowing through a branch. For example, it is necessary to prevent both the low-side transistor and transistor 100a, located in the same branch as transistor 100a, from turning on, thereby preventing shoot-through current from flowing. Therefore, during synchronous rectification, a dead time is provided during which both transistor 100a (the low-side transistor and the high-side transistor) are turned off. The period from time t0 to time t1 constitutes part of this dead time.

[0103] During the period from time t1 to time t2, a positive gate voltage Vg is applied to the gate electrode 18. During the period from time t1 to time t2, a positive voltage is applied to the gate electrode 18. The gate voltage Vg is, for example, +15 V. The gate voltage Vg applied to the gate electrode 18 during the period from time t1 to time t2 is an example of a first positive voltage.

[0104] During the period from time t1 to time t2, if Figure 5B As shown, an inversion layer is formed in the channel region of transistor 100a, and a unipolar current flows in the channel region. Furthermore, during the period from time t1 to time t2, for example, the voltage between source electrode 12 and drain electrode 14 is lower than the forward voltage (Vf) of the pn junction diode built into transistor 100a, so no current flows through the pn junction diode.

[0105] For example, during the period from time t2 to time t6, a large surge current exceeding the steady state current flows through transistor 100a. For example, the surge current reaches its maximum at time t4. During the period from time t0 to time t2 and from time t6 to time t7, transistor 100a is in a steady state.

[0106] During the period from time t2 to time t3, a positive gate voltage Vg is applied to the gate electrode 18. During the period from time t2 to time t3, a positive voltage is applied to the gate electrode 18. The gate voltage Vg is, for example, +15 V. The gate voltage Vg applied to the gate electrode 18 during the period from time t2 to time t3 is an example of a first positive voltage.

[0107] During the period from time t2 to time t3, if Figure 5C As shown, an inversion layer is formed in the channel region of transistor 100a, causing a unipolar current to flow in the channel region. Furthermore, during the period from time t2 to time t3, for example, the voltage between source electrode 12 and drain electrode 14 exceeds the forward voltage (Vf) of the pn junction diode built into transistor 100a, causing a bipolar current to flow through the pn junction diode. During the period from time t2 to time t3, for example, both a unipolar current and a bipolar current flow through transistor 100a.

[0108] At time t3, the current flowing from the source electrode 12 to the drain electrode 14 of the transistor 100a exceeds the first threshold current. The first threshold current is a predetermined current value. The first threshold current is an example of a first threshold value. The current flowing from the source electrode 12 to the drain electrode 14 is measured using the ammeter 100b.

[0109] The first threshold current is, for example, the maximum allowable peak current value (I FSM ) is greater than or equal to 0.6 times and less than or equal to 1.0 times. In this case, the maximum allowable peak current value (IFSM ) is the maximum allowable peak current value (I FSM ).

[0110] At time t3, the comparison circuit 100c determines that the current flowing from the source electrode 12 to the drain electrode 14 of the transistor 100a exceeds the first threshold current. The comparison circuit 100c makes this determination by comparing the value measured by the ammeter 100b with the first threshold current.

[0111] At time t3, a negative gate voltage Vg lower than the threshold voltage of the transistor 100a is applied to the gate electrode 18. At time t3, a negative voltage is applied to the gate electrode 18. The gate voltage Vg is, for example, -15 V. The gate voltage Vg applied to the gate electrode 18 at time t3 is an example of a first negative voltage.

[0112] As a result of the comparison in the comparator circuit 100 c , when the measured current value exceeds the first threshold current, the gate driver circuit 100 d applies a first negative voltage to the gate electrode 18 .

[0113] The delay time from when the value measured by the comparator circuit 100c exceeds the first threshold current to when a negative voltage is applied to the gate electrode 18 is, for example, 2 ms or less. For example, the delay time from when the value measured by the comparator circuit 100c exceeds the first threshold current to when the gate driver circuit 100d outputs the first negative voltage to the gate electrode 18 is, for example, 2 ms or less.

[0114] During the period from time t3 to time t5, a negative gate voltage Vg is applied to the gate electrode 18. During the period from time t3 to time t5, a negative voltage is applied to the gate electrode 18. The gate voltage Vg is, for example, -15 V. The gate voltage Vg applied to the gate electrode 18 during the period from time t3 to time t5 is an example of a first negative voltage.

[0115] During the period from time t3 to time t5, the gate voltage Vg becomes the first negative voltage, and the body region 30 facing the gate electrode 18 enters the accumulation state. During the period from time t3 to time t5, an accumulation layer is formed in the channel region of the transistor 100a, and no channel is formed in the channel region. Figure 5D As shown, no current flows in the channel region.

[0116] Furthermore, during the period from time t3 to time t5, for example, the voltage between the source electrode 12 and the drain electrode 14 is higher than the forward voltage (Vf) of the pn junction diode built into the transistor 100a, causing a bipolar current to flow through the pn junction diode. During the period from time t3 to time t5, for example, only a bipolar current flows, not a unipolar current.

[0117] At time t5, the current flowing from the source electrode 12 to the drain electrode 14 of the transistor 100a falls below the second threshold current. The second threshold current is an example of a second threshold value. The second threshold current may be equal to the first threshold current. Alternatively, the second threshold current may be different from the first threshold current.

[0118] At time t5, the comparison circuit 100c determines that the current flowing from the source electrode 12 to the drain electrode 14 of the transistor 100a is lower than the second threshold current. The comparison circuit 100c makes this determination by comparing the value measured by the ammeter 100b with the second threshold current.

[0119] At time t5, a positive gate voltage Vg higher than the threshold voltage of transistor 100a is applied to gate electrode 18. At time t5, a positive voltage is applied to gate electrode 18. Gate voltage Vg is, for example, +15 V. At time t5, gate voltage Vg applied to gate electrode 18 is an example of a second positive voltage.

[0120] When the measured current value is lower than the second threshold current as a result of the comparison in the comparator circuit 100 c , the second positive voltage is applied to the gate electrode 18 by the gate driver circuit 100 d .

[0121] During the period from time t5 to time t6, a positive gate voltage Vg is applied to the gate electrode 18. During the period from time t5 to time t6, a positive voltage is applied to the gate electrode 18. The gate voltage Vg is, for example, +15 V. The gate voltage Vg applied to the gate electrode 18 during the period from time t5 to time t6 is an example of a second positive voltage.

[0122] During the period from time t5 to time t6, an inversion layer is formed in the channel region of the transistor 100a. Figure 5E As shown, a unipolar current flows in the channel region of transistor 100a. Furthermore, during the period from time t5 to time t6, for example, the voltage between source electrode 12 and drain electrode 14 is higher than the forward voltage (Vf) of the pn junction diode built into transistor 100a. Therefore, a bipolar current flows through the pn junction diode. During the period from time t5 to time t6, for example, both a unipolar current and a bipolar current flow through transistor 100a.

[0123] During the period from time t6 to time t7, a positive gate voltage Vg is applied to the gate electrode 18. During the period from time t6 to time t7, a positive voltage is applied to the gate electrode 18. The gate voltage Vg is, for example, +15 V. The gate voltage Vg applied to the gate electrode 18 during the period from time t6 to time t7 is an example of a second positive voltage.

[0124] During the period from time t6 to time t7, an inversion layer is formed in the channel region of the transistor 100a. Figure 5F As shown, a unipolar current flows in the channel region of the transistor 100a. In addition, during the period from time t6 to time t7, for example, the voltage between the source electrode 12 and the drain electrode 14 is lower than the forward voltage (Vf) of the pn junction diode built into the transistor 100a, so no current flows in the pn junction diode.

[0125] Next, the operation and effects of the semiconductor device according to the first embodiment will be described.

[0126] Vertical MOSFETs using silicon carbide have a pn junction diode as a built-in diode. For example, MOSFETs are used as switching elements connected to inductive loads. In this case, the built-in diode allows return current to flow even when the MOSFET is off.

[0127] Sometimes a surge current exceeding the steady state may flow through the MOSFET instantaneously. When a large surge current flows, the MOSFET heats up and breaks down. The maximum allowable peak current value (I FSM ) is called surge current capability. In MOSFETs, it is desirable to improve surge current capability.

[0128] The semiconductor module 100 according to the first embodiment can improve surge current tolerance by applying a negative voltage to the gate electrode 18 when a surge current flows through the transistor 100 a included in the semiconductor module 100 . This will be described in detail below.

[0129] Figure 6 1 is a block diagram of a semiconductor device according to a comparative example. The semiconductor device according to the comparative example is a semiconductor module 900 including a transistor 100 a using silicon carbide.

[0130] The semiconductor module 900 includes a transistor 100a and a gate driver circuit 100d. The semiconductor module 900 differs from the semiconductor module 100 of the first embodiment in that the ammeter 100b and the comparator circuit 100c are not included.

[0131] Figure 7 、 Figure 8A 、 Figure 8B 、 Figure 8C as well as Figure 8D It is an explanatory diagram of a control method of a semiconductor device according to a comparative example.

[0132] Figure 7 Graphs showing temporal changes in current and gate voltage of the transistor 100 a according to the comparative example. Figure 7 The first embodiment Figure 4 The corresponding figure.

[0133] Figure 8A 、 Figure 8B 、 Figure 8C as well as Figure 8D It is shown in Figure 7 Schematic diagram of current flowing in transistor 100a during each time period shown. In the figure, solid arrows represent unipolar currents, and dashed arrows represent bipolar currents.

[0134] During the period from time t0 to time t1, a gate voltage Vg lower than the threshold voltage of the transistor 100a is applied to the gate electrode 18. Figure 8A As shown, no current flows in the channel region. Also, during the period from time t0 to time t1, for example, no current flows in the pn junction diode.

[0135] During the period from time t1 to time t2, a positive gate voltage Vg higher than the threshold voltage of the transistor 100a is applied to the gate electrode 18. Figure 8B As shown, a unipolar current flows in the channel region. In addition, during the period from time t1 to time t2, no current flows in the pn junction diode.

[0136] For example, during the period from time t2 to time t6, if Figure 7 As shown in the upper figure, a surge current exceeding the steady state is applied to the transistor 100a. For example, the surge current reaches a maximum at time t4.

[0137] During the period from time t2 to time t6, if Figure 7 As shown in the lower figure, a positive gate voltage Vg higher than the threshold voltage of the transistor 100a is applied to the gate electrode 18. During the period from time t2 to time t6, the positive voltage is applied to the gate electrode 18. The gate voltage Vg is, for example, +15V.

[0138] During the period from time t2 to time t6, an inversion layer is formed in the channel region of the transistor 100a. Figure 8CAs shown, a unipolar current flows in the channel region of transistor 100a. Furthermore, during the period from time t2 to time t6, for example, the voltage between source electrode 12 and drain electrode 14 is higher than the forward voltage (Vf) of the pn junction diode built into transistor 100a. Therefore, a bipolar current flows through the pn junction diode. During the period from time t2 to time t6, for example, both a unipolar current and a bipolar current flow through transistor 100a.

[0139] During the period from time t6 to time t7, a positive gate voltage Vg is applied to the gate electrode 18. During the period from time t1 to time t2, an inversion layer is formed in the channel region of the transistor 100a. Figure 8D As shown, a unipolar current flows in the channel region. In addition, during the period from time t6 to time t7, for example, the voltage between the source electrode 12 and the drain electrode 14 is lower than the forward voltage (Vf) of the pn junction diode built into the transistor 100a, so no current flows in the pn junction diode.

[0140] The control method of the semiconductor module 900 of the comparative example differs from the control method of the semiconductor module 100 of the first embodiment in that a negative voltage is not applied to the gate electrode 18, particularly when a large surge current flows through the transistor 100a. In other words, the control method of the semiconductor module 900 of the comparative example differs from the control method of the semiconductor module 100 of the first embodiment in that a positive voltage is continuously applied to the gate electrode 18, particularly when a large surge current flows through the transistor 100a.

[0141] Figure 9 It is an explanatory diagram of the operation and effect of the semiconductor device according to the first embodiment. Figure 9 FIG. 2 shows the relationship between the source voltage of the transistor 100 a and the current flowing through the transistor 100 a . The current flows when the source voltage of the source electrode 12 is a positive voltage higher than the drain voltage of the drain electrode 14 . Figure 9 The solid line in FIG. 5 represents the case where the gate voltage Vg is +15V, and the dotted line represents the case where the gate voltage Vg is −15V.

[0142] like Figure 9 As shown in FIG. 1 , when the gate voltage Vg is +15 V, a unipolar current flows in the channel region of the transistor 100 a, so the current rises from the source voltage 0 V. On the other hand, Figure 9 As shown, when the gate voltage Vg is -15 V, no current flows in the channel region of the transistor 100 a , but the current increases when the source voltage exceeds the forward voltage (Vf) of the pn junction diode.

[0143] When using transistor 100a to allow a backflow current to flow, for example, by setting the gate voltage Vg to +15 V, a unipolar current can flow in the channel region, thereby reducing power loss in the semiconductor module. Therefore, when allowing a backflow current to flow, it is preferable to apply a positive voltage exceeding the threshold voltage of transistor 100a as gate voltage Vg.

[0144] In the semiconductor module 900 of the comparative example, a positive voltage exceeding the threshold voltage of the transistor 100a is applied as the gate voltage Vg during a stable period in which no surge current flows, for example, between time t1 and time t2 and between time t6 and time t7. This reduces power loss in the semiconductor module 900.

[0145] Similarly, in the semiconductor module 100 of the first embodiment, a positive voltage exceeding the threshold voltage of the transistor 100a is applied as the gate voltage Vg during a stable period in which no surge current flows, for example, between time t1 and time t2 and between time t6 and time t7. This reduces power loss in the semiconductor module 100.

[0146] Figure 10 It is an explanatory diagram of the operation and effect of the semiconductor device according to the first embodiment. Figure 10 The maximum allowable peak current value (I FSM ) ratio. Figure 10 The maximum allowable peak current value (I FSM ) is 100%, the maximum allowable peak current value (I FSM ) ratio.

[0147] like Figure 10 As shown in FIG. 1 , the maximum allowable peak current value (I FSM ) is 29%, which is lower than the maximum allowable peak current value (I FSM ) In other words, the semiconductor module of the first embodiment has improved surge current tolerance compared to the semiconductor module of the comparative example.

[0148] Figure 11 It is an explanatory diagram of the operation and effect of the semiconductor device according to the first embodiment. Figure 11 FIG. 2 shows the relationship between the source voltage of the transistor 100 a and the current flowing through the transistor 100 a . The current flows when the source voltage of the source electrode 12 is a positive voltage higher than the drain voltage of the drain electrode 14 . Figure 11 The solid line in the figure is when the gate voltage Vg is +15V, and the dotted line is when the gate voltage Vg is -15V. Figure 11 In, become included with Figure 9 Graph of the region with higher voltage compared to the source.

[0149] like Figure 11 As shown, in the region where the current flowing through the transistor 100a is low, when the gate voltage Vg is +15 V, the source voltage is lower than when the gate voltage Vg is -15 V. Therefore, when the gate voltage Vg is +15 V, the amount of heat generated, which is proportional to the product of current and voltage, is suppressed to a lower level.

[0150] On the other hand, Figure 11 As shown, in the region where the current flowing through the transistor 100a is high, specifically, in Figure 11 In the region where the current is higher than the current reversal point, when the gate voltage Vg is +15V, the source voltage is higher than when the gate voltage Vg is -15V. Figure 11 In the region where the current is higher than the current reversal point, when the gate voltage Vg is +15 V, the amount of heat generated, which is proportional to the product of the current and the voltage, is higher than when the gate voltage Vg is -15 V.

[0151] In the semiconductor module 900 of the comparative example, Figure 7 As shown, during the period from time t2 to time t6 when the surge current flows, the gate voltage Vg is maintained at +15 V. Therefore, for example, the heat generated when the surge current flows is higher than when the gate voltage Vg is maintained at -15 V. Therefore, it is believed that the surge current tolerance is reduced.

[0152] On the other hand, in the semiconductor module 100 of the first embodiment, as Figure 4 As shown, during the period from time t3 to time t5 when a high surge current flows, the gate voltage Vg is maintained at -15 V. Therefore, compared to the case where the gate voltage Vg is maintained at +15 V, for example, the heat generated when the surge current flows is lower. Therefore, it is believed that the surge current tolerance is improved.

[0153] In the semiconductor module 100 of the first embodiment, from the viewpoint of preventing current from flowing in the channel region of the transistor 100 a , the first negative voltage applied to the gate electrode 18 during the period from time t3 to time t5 is preferably −5 V or less, more preferably −10 V or less, and even more preferably −15 V or less.

[0154] In the semiconductor module 100 of the first embodiment, from the perspective of current flowing in the channel region of the transistor 100a, the first negative voltage applied to the gate electrode 18 during the period between time t1 and time t2 and between time t6 and time t7 is preferably greater than +5V, more preferably greater than +10V, and even more preferably greater than +15V.

[0155] Figure 12A 、 Figure 12B It is an explanatory diagram of the operation and effect of the semiconductor device according to the first embodiment. Figure 12A 、 Figure 12B It is a figure which shows the simulation result.

[0156] Figure 12A It is shown in Figure 2 FIG. 1 is a graph showing a time change of a surge current when a positive gate voltage Vg of +15 V higher than the threshold voltage of the transistor 100 a is applied to the gate electrode 18 in the structure of the transistor 100 a shown in FIG. Figure 12A As shown, a current peak of 34 A was observed during a time period of 4.0 ms (milliseconds).

[0157] Figure 12B It is shown in Figure 2 This graph shows the maximum temperature of transistor 100a when a surge current flows through the structure of transistor 100a. As in the comparative example, the solid line shows the case where +15V is continuously applied as gate voltage Vg. The dashed line shows the case where the positive gate voltage Vg of +15V is switched to the negative gate voltage Vg of -15V at the time (4.0ms) when the current peak is observed. The dashed line corresponds to the first embodiment.

[0158] like Figure 12B As shown, there is a delay of 2 ms (milliseconds) from the time when the current peak is observed to the time when the maximum temperature appears. It is believed that the delay in heat propagation inside the transistor 100a is one of the causes of this delay.

[0159] Due to the above-mentioned delay time, even if the gate voltage Vg is switched from a positive voltage to a negative voltage simultaneously with the time when the current peak is observed, as in Figure 12B As shown by the middle dashed line, the internal temperature of transistor 100a is also kept sufficiently low. Due to the aforementioned delay time, the gate voltage Vg is switched from a positive voltage to a negative voltage within a period of less than 2 ms from the time the current peak is observed, thereby suppressing the internal temperature of transistor 100a from reaching the maximum temperature.

[0160] Figure 13 It is an explanatory diagram of the operation and effect of the semiconductor device according to the first embodiment. Figure 13 Is shown using Figure 2 Graph showing experimental results of transistor 100a.

[0161] The maximum allowable peak current value (I FSM ) results of the evaluation.

[0162] When the first threshold current (Isw) is set to the maximum allowable peak current value (I FSM ) of 34A, under the operating conditions of the first embodiment, the maximum allowable peak current value (I FSM ) from the maximum allowable peak current value (I FSM ) decreases. In addition, the maximum allowable peak current value (I FSM ) the same or higher maximum allowable peak current value (I FSM ).

[0163] When the comparison circuit 100c detects the current flowing from the source electrode 12 to the drain electrode 14, the delay time from when the value measured in the comparison circuit 100c exceeds the first threshold current to when the first negative voltage is applied to the gate electrode 18 is preferably less than 2 ms, more preferably less than 500 μs, and more preferably less than 200 μs. For example, the time from when the value measured in the comparison circuit 100c exceeds the first threshold current to when the gate driver circuit 100d outputs the first negative voltage to the gate electrode 18 is preferably less than 2 ms, more preferably less than 500 μs, and more preferably less than 200 μs. By satisfying the above-mentioned upper limit, the maximum allowable peak current value (I FSM ) is suppressed, and the surge current tolerance is improved.

[0164] The first threshold current is preferably the maximum allowable peak current value (I FSM ) is not less than 0.6 times and not more than 1.0 times, more preferably not less than 0.8 times and not more than 1.0 times. In this case, the maximum allowable peak current value (I FSM) is the maximum allowable peak current value (I ) of the transistor 100a under the operating condition (operating condition of the comparative example) in which the gate voltage Vg of +15V is continuously applied to the gate electrode 18 while the voltage of the source electrode 12 is a positive voltage higher than that of the drain electrode 14. FSM ).

[0165] Since the first threshold current satisfies the upper limit, the maximum allowable peak current value (I FSM ) is suppressed. In addition, since the first threshold current satisfies the above-mentioned lower limit value, the reduction of power loss of the semiconductor module 100 is promoted.

[0166] (Variation)

[0167] The semiconductor device according to the modification of the first embodiment differs from the first embodiment in that it includes a detector that detects the voltage of the first electrode when the voltage of the first electrode is a positive voltage higher than the voltage of the second electrode.

[0168] Figure 14 1 is a block diagram of a semiconductor device according to a modification of the first embodiment. The semiconductor device according to the modification of the first embodiment is a semiconductor module 101 including a transistor 100 a using silicon carbide.

[0169] The semiconductor module 101 includes a transistor 100 a , a voltmeter 100 f , a comparison circuit 100 c , and a gate driver circuit 100 d .

[0170] The voltmeter 100f is provided, for example, between the source electrode 12 and the drain electrode 14 of the transistor 100a. The voltmeter 100f can detect the voltage of the source electrode 12, that is, the source voltage.

[0171] The voltmeter 100 f is an example of a detector, and the voltmeter 100 f detects the voltage of the source electrode 12 when the voltage of the source electrode 12 is a higher positive voltage than that of the drain electrode 14 .

[0172] The comparison circuit 100 c is electrically connected to the voltmeter 100 f , and compares a value measured by the voltmeter 100 f with a first threshold value when the voltage of the source electrode 12 is a positive voltage higher than that of the drain electrode 14 .

[0173] The value measured by the voltmeter 100f is a voltage value. The first threshold value is a preset threshold voltage. The first threshold value is, for example, 5V or more and 15V or less.

[0174] The gate driver circuit 100 d is electrically connected to the comparison circuit 100 c and the gate electrode 18 .

[0175] The gate driver circuit 100d applies a first positive voltage, which is higher than the threshold voltage of the transistor 100a, to the gate electrode 18 when the voltage of the source electrode 12 is a positive voltage higher than that of the drain electrode 14. Furthermore, the gate driver circuit 100d applies a first negative voltage to the gate electrode 18 when the value measured by the comparison circuit 100c exceeds the first threshold.

[0176] Next, a method for controlling a semiconductor device according to a modified example of the first embodiment will be described.

[0177] The control method of the semiconductor device according to the first embodiment is different from the control method of the semiconductor device according to the first embodiment in that the voltage of the first electrode is detected.

[0178] Figure 15 It is an explanatory diagram of a control method of a semiconductor device according to a modification of the first embodiment. Figure 15 The first embodiment Figure 4 The corresponding figure.

[0179] Figure 15 Graphs showing temporal changes in the voltage and gate voltage of the transistor 100 a according to a modification of the first embodiment. Figure 15 FIG. 1 shows the temporal changes in the voltage and gate voltage when the voltage of the source electrode 12 is a positive voltage higher than that of the drain electrode 14. Figure 15 , the current of the source electrode 12 is also shown.

[0180] exist Figure 15 In the figure above, the horizontal axis is time, and the vertical axis is current and voltage. Current is the current flowing from the source electrode 12 to the drain electrode 14. Voltage is the voltage of the source electrode 12. The reference potential is, for example, 0V. Figure 15 In the figure above, the dotted line represents the current and the solid line represents the voltage.

[0181] exist Figure 15 In the figure below, the horizontal axis represents time and the vertical axis represents gate voltage. The gate voltage is the voltage applied to the gate electrode 18.

[0182] During the period from time t0 to time t1, similarly to the first embodiment, a gate voltage Vg lower than the threshold voltage of the transistor 100a is applied to the gate electrode 18. During the period from time t0 to time t1, for example, a negative gate voltage Vg is applied to the gate electrode 18.

[0183] During the period from time t1 to time t2, as in the first embodiment, a positive gate voltage Vg is applied to the gate electrode 18. During the period from time t1 to time t2, a positive voltage is applied to the gate electrode 18. The gate voltage Vg is, for example, +15 V. The gate voltage Vg applied to the gate electrode 18 during the period from time t1 to time t2 is an example of a first positive voltage.

[0184] For example, during the period from time t2 to time t6, a surge current exceeding the steady state flows through the transistor 100a. For example, the surge current reaches its maximum at time t4.

[0185] During the period from time t2 to time t3, as in the first embodiment, a positive gate voltage Vg is applied to the gate electrode 18. During the period from time t2 to time t3, a positive voltage is applied to the gate electrode 18. The gate voltage Vg is, for example, +15 V. During the period from time t2 to time t3, the gate voltage Vg applied to the gate electrode 18 is an example of a first positive voltage.

[0186] At time t3, the voltage of the source electrode 12 of the transistor 100a exceeds the first threshold voltage. The first threshold voltage is a predetermined voltage value. The first threshold voltage is an example of a first threshold value. The voltage of the source electrode 12 is measured using a voltmeter 100f.

[0187] At time t3, the comparison circuit 100c determines that the current flowing from the source electrode 12 to the drain electrode 14 of the transistor 100a exceeds the first threshold voltage. The comparison circuit 100c makes the determination by comparing the value measured by the voltmeter 100f with the first threshold voltage.

[0188] At time t3, a negative gate voltage Vg lower than the threshold voltage of the transistor 100a is applied to the gate electrode 18. At time t3, a negative voltage is applied to the gate electrode 18. The gate voltage Vg is, for example, -15 V. The gate voltage Vg applied to the gate electrode 18 at time t3 is an example of a first negative voltage.

[0189] When the result of the comparison in the comparator circuit 100 c indicates that the measured value of the voltage of the source electrode 12 exceeds the first threshold voltage, the gate driver circuit 100 d applies a first negative voltage to the gate electrode 18 .

[0190] During the period from time t3 to time t5, similar to the first embodiment, a negative gate voltage Vg is applied to the gate electrode 18. During the period from time t3 to time t5, a negative voltage is applied to the gate electrode 18. The gate voltage Vg is, for example, -15 V. The gate voltage Vg applied to the gate electrode 18 during the period from time t3 to time t5 is an example of a first negative voltage.

[0191] At time t5, the voltage of the source electrode 12 of the transistor 100a is lower than the second threshold voltage. The second threshold voltage is an example of a second threshold. The second threshold voltage may be equal to the first threshold voltage, for example. Alternatively, the second threshold voltage may be lower than the first threshold voltage, for example.

[0192] At time t5, the comparison circuit 100c determines that the voltage of the source electrode 12 of the transistor 100a is lower than the second threshold voltage. The comparison circuit 100c makes this determination by comparing the value measured by the voltmeter 100f with the second threshold voltage.

[0193] At time t5, a positive gate voltage Vg higher than the threshold voltage of transistor 100a is applied to gate electrode 18. At time t5, a positive voltage is applied to gate electrode 18. Gate voltage Vg is, for example, +15 V. At time t5, gate voltage Vg applied to gate electrode 18 is an example of a second positive voltage.

[0194] When the result of the comparison in the comparator circuit 100 c shows that the measured value of the voltage of the source electrode 12 is lower than the second threshold voltage, the gate driver circuit 100 d applies the second positive voltage to the gate electrode 18 .

[0195] During the period from time t5 to time t6, as in the first embodiment, a positive gate voltage Vg is applied to the gate electrode 18. During the period from time t5 to time t6, a positive voltage is applied to the gate electrode 18. The gate voltage Vg is, for example, +15 V. The gate voltage Vg applied to the gate electrode 18 during the period from time t5 to time t6 is an example of a second positive voltage.

[0196] During the period from time t6 to time t7, as in the first embodiment, a positive gate voltage Vg is applied to the gate electrode 18. During the period from time t6 to time t7, a positive voltage is applied to the gate electrode 18. The gate voltage Vg is, for example, +15 V. During the period from time t6 to time t7, the gate voltage Vg applied to the gate electrode 18 is an example of a second positive voltage.

[0197] According to the semiconductor module 101 of the modification of the first embodiment, similarly to the semiconductor module 100 of the first embodiment, when a surge current flows through the transistor 100a included in the semiconductor module 101, a negative voltage is applied to the gate electrode 18. Therefore, surge current tolerance can be improved.

[0198] Furthermore, in the semiconductor module 101 of the modified example of the first embodiment, the surge current tolerance is improved, so as to Figure 15 As shown, the second threshold voltage is preferably lower than the first threshold voltage.

[0199] like Figure 15As shown, for example, the voltage at the source electrode 12 of transistor 100a exhibits a behavior that peaks at the start of the surge current flow and then decreases. Therefore, if the second threshold voltage and the first threshold voltage are equal, the current flowing through transistor 100a at time t5 may be greater than the current flowing through transistor 100a at time t3. In this case, if a positive voltage is applied to the gate electrode 18 at time t5, the current flowing through transistor 100a may exceed the maximum allowable peak current value.

[0200] By setting the second threshold voltage lower than the first threshold voltage, the current flowing through transistor 100a at time t5 can be made less than the current flowing through transistor 100a at time t3. Therefore, by applying a positive voltage to gate electrode 18 at time t5, the possibility of exceeding the maximum allowable peak current value is eliminated, thereby improving the surge current tolerance of semiconductor module 101.

[0201] As described above, according to the first embodiment and its modified examples, a semiconductor device with improved surge current tolerance is realized. In addition, according to the first embodiment and its modified examples, a semiconductor device with reduced power loss is realized.

[0202] (Second embodiment)

[0203] The semiconductor device and semiconductor device control method of the second embodiment differ from the semiconductor device of the first embodiment in that the first electrode is in contact with the first semiconductor region. Specifically, the semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that the transistor includes a Schottky diode as a built-in diode. Below, some of the details overlapping with the first embodiment may be omitted.

[0204] Figure 16 2 is a block diagram of a semiconductor device according to Embodiment 2. The semiconductor device according to Embodiment 2 is a semiconductor module 200 including a transistor 200 a using silicon carbide.

[0205] The semiconductor module 200 includes a transistor 200 a , an ammeter 100 b , a comparison circuit 100 c , and a gate driver circuit 100 d .

[0206] Figure 17 It is a schematic cross-sectional view of a transistor according to a second embodiment. Figure 17 is a cross-sectional view of the transistor 200a.

[0207] Transistor 200a is a vertical MOSFET with a planar gate using silicon carbide. Transistor 200a is, for example, a double-implantation MOSFET (DIMOSFET) in which the body and source regions are formed by ion implantation. Transistor 200a is a vertical n-channel MOSFET using electrons as carriers.

[0208] The transistor 200 a includes a silicon carbide layer 10 , a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate insulating layer 16 , a gate electrode 18 , and an interlayer insulating layer 20 .

[0209] In the silicon carbide layer 10, n + Type drain region 26, n - The p-type drift region 28 (first semiconductor region), the p-type body region 30 (second semiconductor region), and the n-type + Type source region 34 (third semiconductor region).

[0210] Source electrode 12 is provided on the first surface P1 side of silicon carbide layer 10. Source electrode 12 is in contact with first surface P1.

[0211] The source electrode 12 is in contact with the drift region 28, the body region 30, and the source region 34. The source electrode 12 is in contact with the drift region 28 on the first plane P1.

[0212] The source electrode 12 is made of metal. The metal forming the source electrode 12 is, for example, a stacked structure of titanium (Ti) and aluminum (Al).

[0213] The portion of the source electrode 12 that is in contact with the body region 30 and the source region 34 is, for example, a metal silicide, such as titanium silicide or nickel silicide.

[0214] The contact between the body region 30 and the source electrode 12 and the contact between the source region 34 and the source electrode 12 are, for example, ohmic contacts.

[0215] The contact between the drift region 28 and the source electrode 12 is, for example, a Schottky contact.

[0216] like Figure 16 As shown, in the transistor 200 a , a pn junction diode and a Schottky junction diode are connected between the source electrode 12 and the drain electrode 14 as built-in diodes.

[0217] For example, consider the case where transistor 200a is used as a switching element connected to an inductive load. When transistor 200a is off, the load current from the inductive load may cause a positive voltage to be applied to source electrode 12 relative to drain electrode 14. In this case, a forward current flows through the internal diode. This state is also called a reverse conduction state.

[0218] When the voltage between the source electrode 12 and the drain electrode 14 exceeds the forward voltage (Vf) of the Schottky junction diode, a forward current flows through the Schottky junction diode. Furthermore, when the voltage between the source electrode 12 and the drain electrode 14 exceeds the forward voltage (Vf) of the pn junction diode, a forward current flows through the pn junction diode. The forward voltage (Vf) of the Schottky junction diode is lower than the forward voltage (Vf) of the pn junction diode.

[0219] According to the semiconductor module 200 of the second embodiment, similarly to the semiconductor module 100 of the first embodiment, when a surge current flows through the transistor 200 a included in the semiconductor module 200 , a negative voltage is applied to the gate electrode 18 , thereby improving surge current tolerance.

[0220] In addition, in the transistor 200a, a Schottky junction diode having a forward voltage (Vf) lower than the forward voltage (Vf) of the pn junction diode is included as a built-in diode. Therefore, for example, if Figure 4 During the period from time t0 to time t1, the voltage between the source electrode 12 and the drain electrode 14 is higher than the forward voltage (Vf) of the Schottky junction diode built into the transistor 200a, allowing current to flow through the Schottky junction diode. Therefore, the semiconductor module 200 of the second embodiment can start flowing the return current earlier than the semiconductor module 100 of the first embodiment, further reducing power loss.

[0221] (Variation)

[0222] The semiconductor device of the variation of the second embodiment differs from the second embodiment in that the semiconductor device includes a detector for detecting the voltage of the first electrode when the voltage of the first electrode is a positive voltage higher than the voltage of the second electrode. Furthermore, the semiconductor device of the variation of the second embodiment differs from the semiconductor device of the variation of the first embodiment in that the transistor includes a Schottky junction diode as a built-in diode.

[0223] Figure 18 2 is a block diagram of a semiconductor device according to a modification of Embodiment 2. The semiconductor device according to the modification of Embodiment 2 is a semiconductor module 201 including a transistor 200 a using silicon carbide.

[0224] The semiconductor module 201 includes a transistor 200 a , a voltmeter 100 f , a comparison circuit 100 c , and a gate driver circuit 100 d .

[0225] According to the semiconductor module 201 of the modification of the second embodiment, similarly to the semiconductor module 200 of the second embodiment, when a surge current flows through the transistor 200 a included in the semiconductor module 201 , a negative voltage is applied to the gate electrode 18 , thereby improving surge current tolerance.

[0226] As described above, according to the second embodiment and its modified example, a semiconductor device with improved surge current tolerance is realized. In addition, according to the second embodiment and its modified example, a semiconductor device with further reduced power loss is realized.

[0227] In the first and second embodiments, the case where the semiconductor region is made of silicon carbide (SiC) has been described as an example, but the semiconductor region may be made of silicon (Si) or a nitride semiconductor, for example.

[0228] In the first and second embodiments, the case where 4H-SiC is used as the crystal structure of SiC is described as an example, but the present invention is also applicable to devices using SiC with other crystal structures such as 6H-SiC and 3C-SiC. In addition, the surface of the silicon carbide layer 10 can also be applied to planes other than the (0001) plane.

[0229] In the first and second embodiments, aluminum (Al) is exemplified as the p-type impurity, but boron (B) can also be used. Furthermore, nitrogen (N) and phosphorus (P) are exemplified as the n-type impurity, but arsenic (As), antimony (Sb), etc. can also be applied.

[0230] Although several embodiments of the present invention have been described, these embodiments are merely illustrative and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways and can be omitted, replaced, or modified in various ways without departing from the gist of the invention. For example, the constituent elements of one embodiment can be replaced or modified with constituent elements of other embodiments. These embodiments and their variations are included in the scope and gist of the invention and are included in the invention described in the claims and their equivalents.

Claims

1. A semiconductor device comprising: 1st electrode; 2nd electrode; a transistor comprising an n-type first semiconductor region disposed between the first electrode and the second electrode and electrically connected to the second electrode, a p-type second semiconductor region disposed between the first semiconductor region and the first electrode and electrically connected to the first electrode, an n-type third semiconductor region disposed between the second semiconductor region and the first electrode and electrically connected to the first electrode, and a gate electrode facing the second semiconductor region; a detector configured to detect the voltage of the first electrode or the current flowing from the first electrode to the second electrode when the voltage of the first electrode is a positive voltage higher than the voltage of the second electrode; a comparison circuit that compares a measurement value measured by the detector with a first threshold value in the state; as well as The gate driver circuit applies a first positive voltage higher than the threshold voltage of the transistor to the gate electrode in the state, and applies a first negative voltage to the gate electrode when the measured value exceeds the first threshold value as a result of comparison in the comparison circuit.

2. The semiconductor device according to claim 1, wherein The first electrode is in contact with the first semiconductor region.

3. The semiconductor device according to claim 2, wherein The contact between the first electrode and the first semiconductor region is a Schottky contact.

4. The semiconductor device according to claim 1, wherein When the first negative voltage is applied to the gate electrode, the second semiconductor region facing the gate electrode enters an accumulation state.

5. The semiconductor device according to claim 1, wherein After the first negative voltage is applied to the gate electrode, the comparator circuit compares the value measured by the detector with the second threshold value in the above state. In the above state, when the measured value in the comparison circuit is lower than the second threshold value, the gate driver circuit applies a second positive voltage higher than the threshold voltage to the gate electrode. The semiconductor device according to claim 5 , wherein: When the detector detects the voltage of the first electrode, the second threshold value is a voltage lower than the first threshold value.

7. The semiconductor device according to claim 1, wherein The first semiconductor region, the second semiconductor region, and the third semiconductor region are made of silicon carbide.

8. The semiconductor device according to claim 1, wherein When the detector detects the current flowing from the first electrode to the second electrode, the first threshold value is a current value, and the first threshold value is a maximum allowable peak current value (I FSM ) is greater than or equal to 0.6 times and less than or equal to 1.0 times.

9. The semiconductor device according to claim 1, wherein When the detector detects the current flowing from the first electrode to the second electrode, the first threshold value is a current value, and the first threshold value is a maximum allowable peak current value (I FSM ) is greater than or equal to 0.8 times and less than or equal to 1.0 times.

10. The semiconductor device according to claim 1, wherein When the detector detects the current flowing from the first electrode to the second electrode, a delay time from when the measured value exceeds the first threshold value to when the first negative voltage is applied to the gate electrode is less than 2 ms.

11. The semiconductor device according to claim 1, wherein When the detector detects the current flowing from the first electrode to the second electrode, a delay time from when the measured value exceeds the first threshold value to when the first negative voltage is applied to the gate electrode is less than 200 μs.

12. A method for controlling a semiconductor device, the semiconductor device comprising: 1st electrode; a second electrode; and A transistor comprising an n-type first semiconductor region disposed between the first electrode and the second electrode and electrically connected to the second electrode, a p-type second semiconductor region disposed between the first semiconductor region and the first electrode and electrically connected to the first electrode, an n-type third semiconductor region disposed between the second semiconductor region and the first electrode and electrically connected to the first electrode, and a gate electrode facing the second semiconductor region, wherein: applying a positive voltage higher than that of the second electrode to the first electrode, applying a first positive voltage higher than a threshold voltage of the transistor to the gate electrode, detecting a voltage of the first electrode or a current flowing from the first electrode to the second electrode, The detected measurement value is compared with a first threshold value, and when the measurement value exceeds the first threshold value, a first negative voltage is applied to the gate electrode.

13. The method for controlling a semiconductor device according to claim 12, wherein: The first electrode is in contact with the first semiconductor region.

14. The method for controlling a semiconductor device according to claim 13, wherein: The contact between the first electrode and the first semiconductor region is a Schottky contact.

15. The method for controlling a semiconductor device according to claim 12, wherein: When the first negative voltage is applied to the gate electrode, the second semiconductor region facing the gate electrode enters an accumulation state.

16. The method for controlling a semiconductor device according to claim 12, wherein: After applying the first negative voltage to the gate electrode, the measured value is compared with a second threshold value, When the measured value exceeds the second threshold value, a second positive voltage higher than the threshold voltage is applied to the gate electrode.

17. The method for controlling a semiconductor device according to claim 16, wherein: When the voltage of the first electrode is detected, the second threshold value is a voltage lower than the first threshold value.

18. The method for controlling a semiconductor device according to claim 12, wherein: The first semiconductor region, the second semiconductor region, and the third semiconductor region are made of silicon carbide.

19. The method for controlling a semiconductor device according to claim 12, wherein: When detecting the current flowing from the first electrode to the second electrode, the first threshold value is a current value, which is the maximum allowable peak current value (I FSM ) is greater than or equal to 0.6 times and less than or equal to 1.0 times.

20. The method for controlling a semiconductor device according to claim 12, wherein: When detecting the current flowing from the first electrode to the second electrode, the first threshold value is a current value, which is the maximum allowable peak current value (I FSM ) is greater than or equal to 0.8 times and less than or equal to 1.0 times.

21. The method for controlling a semiconductor device according to claim 12, wherein: When detecting the current flowing from the first electrode to the second electrode, a delay time from when the measured value exceeds the first threshold value to when the first negative voltage is applied to the gate electrode is less than 2 ms.

22. The method for controlling a semiconductor device according to claim 12, wherein: When detecting the current flowing from the first electrode to the second electrode, a delay time from when the measured value exceeds the first threshold value to when the first negative voltage is applied to the gate electrode is less than 200 μs.

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