An integrated layout structure capable of quickly selecting power MOS substrate potential

Abstract

The present invention discloses an integrated layout structure capable of quickly selecting the substrate potential of a power MOS transistor (MOSFET). The structure comprises a power MOS transistor (PMO), a substrate potential selection MOS transistor (PM1), and a substrate potential selection MOS transistor (PM2). The power MOS transistor (PMO), the substrate potential selection MOS transistor (PM1), and the substrate potential selection MOS transistor (PM2) are divided into multiple subunits. A power MOS transistor (PM0), a substrate potential selection MOS transistor (PM1), and a substrate potential selection MOS transistor (PM2) subunit constitute a basic functional unit. Within a basic functional unit, the substrate potential selection MOS transistor (PM1) and the substrate potential selection MOS transistor (PM2) subunits are symmetrically arranged on either side of the power MOS transistor (PM0). The present invention saves chip area, simplifies metal wiring for high-current paths, improves potential switching speed, and achieves uniform potential distribution.

Description

Technical Field

[0001] The present invention relates to an integrated layout structure, in particular to an integrated layout structure capable of quickly selecting a power MOS substrate potential, and belongs to the technical field of semiconductor integrated circuits. Background Art

[0002] In traditional analog integrated circuit design, to achieve substrate potential selection, two MOS devices are typically connected directly to the substrate of the power transistor. While this approach is simple and straightforward, in practice it often results in a large chip footprint and complex high-current metal wiring. This can also limit the speed of potential switching and pose the risk of uneven substrate potential switching, impacting reliability. Therefore, a new layout structure is urgently needed to overcome these issues.

[0003] In traditional analog integrated circuits, especially in high-voltage or high-side power switch designs, it's often necessary to control the substrate potential of the power MOS transistor to prevent parasitic bipolar effects. This control is often achieved using two anti-phase-controlled MOS switches: one connected to the power transistor's source voltage and the other to its drain voltage, forming a "bulk switching" structure.

[0004] The existing analog integrated circuits mainly have the following problems:

[0005] 1. Area waste: such as Figure 9 As shown, two MOS devices for substrate potential switching are usually placed in an independent form, which not only occupies additional chip area but also makes the metal wiring of the large current path relatively complicated.

[0006] 2. Switching speed is limited: Since the MOS device is far away from the power tube itself, its connection path is long, which leads to increased parasitic resistance and capacitance, affecting the potential switching speed.

[0007] 3. Reliability risk: Single-point driving of the substrate may lead to uneven potential distribution across the entire substrate, bringing potential reliability risks such as local latch-up or unstable performance, and excessive local current causing chip burn-in.

[0008] Therefore, a new layout structure is urgently needed to solve the above problems without affecting the functions. Summary of the Invention

[0009] The technical problem to be solved by the present invention is to provide an integrated layout structure capable of quickly selecting the potential of a power MOS substrate, thereby solving at least one technical problem of the prior art.

[0010] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0011] An integrated layout structure capable of quickly selecting a power MOS substrate potential includes a power MOS transistor PMO, a substrate potential selection MOS transistor PM1, and a substrate potential selection MOS transistor PM2. The power MOS transistor PMO is split into A power MOS transistor PM0 subunits, and the substrate potential selection MOS transistor PM1 and the substrate potential selection MOS transistor PM2 are respectively split into B substrate potential selection MOS transistor PM1 subunits and substrate potential selection MOS transistor PM2 subunits, where A≥B. One power MOS transistor PM0 subunit, one substrate potential selection MOS transistor PM1 subunit, and one substrate potential selection MOS transistor PM2 subunit constitute a basic functional unit. In a basic functional unit, the substrate potential selection MOS transistor PM1 subunit and the substrate potential selection MOS transistor PM2 subunit are symmetrically arranged on both sides of the power MOS transistor PM0 subunit.

[0012] Furthermore, the number of the power MOS transistor PM0 sub-unit, the substrate potential selection MOS transistor PM1 sub-unit, and the substrate potential selection MOS transistor PM2 sub-unit is an odd number.

[0013] Furthermore, the B power MOS transistor PM0 subunits, substrate potential selection MOS transistor PM1 subunit and substrate potential selection MOS transistor PM2 subunit constitute B basic functional units, and then the remaining AB power MOS transistor PM0 subunits are evenly distributed with the B basic functional units.

[0014] Furthermore, the substrate potential selection MOS transistor PM1 subunit and the substrate potential selection MOS transistor PM2 subunit are symmetrically arranged on both sides of the power MOS transistor PM0 subunit in an axial symmetry or a point symmetry.

[0015] Furthermore, in the basic functional unit, the source and drain ends of the power MOS transistor PM0 sub-unit, the substrate potential selection MOS transistor PM1 sub-unit, and the substrate potential selection MOS transistor PM2 sub-unit are merged into a whole through a shared P-type implantation active region and a CONT contact hole. At the same time, the input ends of the substrate potential selection MOS transistor PM1 sub-unit and the substrate potential selection MOS transistor PM2 sub-unit on both sides are also connected to the source and drain ends of the power MOS transistor PM0 sub-unit.

[0016] Furthermore, in the basic functional unit, the output ends of the substrate potential selection MOS transistor PM1 subunit and the substrate potential selection MOS transistor PM2 subunit are respectively located at the outermost sides of the basic functional unit. The output ends of the substrate potential selection MOS transistor PM1 subunit and the substrate potential selection MOS transistor PM2 subunit are divided by the center line of the CONT contact hole. The output end located on the inner side maintains P-type doping and serves as the source end of the substrate potential selection MOS transistor PM1 subunit or the substrate potential selection MOS transistor PM2 subunit, and the output end located on the outer side is N-doped to become the substrate contact structure of the substrate potential selection MOS transistor PM1 subunit or the substrate potential selection MOS transistor PM2 subunit.

[0017] Furthermore, a second layer of metal is disposed laterally on the upper and lower sides of the basic functional unit, respectively. The second layer of metal is provided with a gate control signal of the power MOS transistor PM0, a gate control signal of the substrate potential selection MOS transistor PM1, and a gate control signal of the substrate potential selection MOS transistor PM2 that are laterally passed through. The gate control signal of the substrate potential selection MOS transistor PM1 and the gate control signal of the substrate potential selection MOS transistor PM2 that are laterally passed through control the substrate potential selection MOS transistor PM1 and the substrate potential selection MOS transistor PM2, respectively, to select and output the source end or the drain end of the power MOS transistor PM0 as the substrate potential of the power MOS transistor PM0.

[0018] Furthermore, in the basic functional unit, an N-type doped active area is used as a substrate contact and is arranged on the upper and lower sides of the basic functional unit, and the output end of the MOS for substrate potential selection on both sides is fully connected to the substrate contact integrated structure using a first layer of metal.

[0019] Compared with the prior art, the present invention has the following advantages and effects:

[0020] 1. The present invention saves chip area and simplifies the complexity of metal wiring of high current paths through integrated design;

[0021] 2. The present invention significantly improves the substrate potential switching speed, meeting the requirements of high-performance power management chips;

[0022] 3. The present invention achieves uniform distribution of substrate potential, reduces latch-up risk, and enhances system reliability;

[0023] 4. The present invention reduces the influence of parasitic parameters and improves response speed and signal integrity;

[0024] 5. The layout of the present invention is compact and highly symmetrical, which is beneficial for thermal management and electrical consistency;

[0025] 6. The present invention is compatible with standard CMOS / BCD process flow and does not require additional special process support. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 This is a schematic diagram of an integrated layout structure capable of quickly selecting the potential of a power MOS substrate of the present invention.

[0027] Figure 2 This is a circuit schematic diagram of an integrated layout structure capable of quickly selecting the potential of a power MOS substrate according to the present invention.

[0028] Figure 3 It is a schematic diagram of a basic functional unit of an integrated layout structure capable of quickly selecting the potential of a power MOS substrate of the present invention.

[0029] Figure 4 It is a structural schematic diagram of a basic functional unit of an integrated layout structure capable of quickly selecting the potential of a power MOS substrate of the present invention.

[0030] Figure 5 It is a partially enlarged view of a basic functional unit of an integrated layout structure capable of quickly selecting the potential of a power MOS substrate according to the present invention.

[0031] Figure 6 It is a cross-sectional view of a basic functional unit of an integrated layout structure capable of quickly selecting the potential of a power MOS substrate according to the present invention.

[0032] Figure 7 It is a cross-sectional view of the splicing structure of basic functional units of an integrated layout structure capable of quickly selecting the potential of a power MOS substrate of the present invention.

[0033] Figure 8 This is a diagram of the connection structure of each subunit of a basic functional unit of an integrated layout structure capable of quickly selecting the power MOS substrate potential of the present invention.

[0034] Figure 9 It is a schematic diagram of the layout structure of the power tube and substrate potential switching circuit in the prior art. DETAILED DESCRIPTION

[0035] In order to elaborate on the technical solutions adopted by the present invention to achieve the predetermined technical purpose, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0036] like Figure 1 As shown, an integrated layout structure capable of quickly selecting a power MOS substrate potential of the present invention includes a power MOS transistor PMO, a substrate potential selection MOS transistor PM1, and a substrate potential selection MOS transistor PM2. The substrate potential selection MOS transistor PM1 and the substrate potential selection MOS transistor PM2 are respectively used to be connected to the source terminal A and the drain terminal B of the power MOS transistor PM0. The gate of the substrate potential selection MOS transistor PM1 is connected to a control signal SLEA to control the selection of the substrate potential. The gate of the substrate potential selection MOS transistor PM2 is connected to a control signal SLEB to control the selection of the substrate potential.

[0037] The power MOS transistor PMO is split into A power MOS transistor PM0 subunits, and the substrate potential selection MOS transistor PM1 and the substrate potential selection MOS transistor PM2 are split into B substrate potential selection MOS transistor PM1 subunits and substrate potential selection MOS transistor PM2 subunits, respectively. A ≥ B. One power MOS transistor PM0 subunit, one substrate potential selection MOS transistor PM1 subunit, and one substrate potential selection MOS transistor PM2 subunit constitute a basic functional unit 100. In one basic functional unit 100, the substrate potential selection MOS transistor PM1 subunit and the substrate potential selection MOS transistor PM2 subunit are symmetrically arranged on both sides of the power MOS transistor PM0 subunit.

[0038] The number of power MOS transistor PM0 subunits, substrate potential selection MOS transistor PM1 subunits, and substrate potential selection MOS transistor PM2 subunits is an odd number. For example, the number of power MOS transistor PM0 subunits is 2n+1, the number of substrate potential selection MOS transistor PM1 subunits, and substrate potential selection MOS transistor PM2 subunits is 2m+1, and n and m are 0 or natural numbers. In this embodiment, Figure 5 As shown, the number of power MOS transistor PM0 subunits is 29, and the number of substrate potential selection MOS transistor PM1 subunit and substrate potential selection MOS transistor PM2 subunit is 1, forming a basic functional unit 100. In each basic functional unit, the number of power MOS transistor PM0 and substrate potential selection MOS transistors PM1 and PM2 must be an odd number so that the source and drain ports of the three MOS transistors can be cleverly merged later, sharing the P-type doped active region and CONT contact hole, and thus forming a complete structure of the integrated layout.

[0039] B power MOS transistor PM0 subunits, substrate potential selection MOS transistor PM1 subunit and substrate potential selection MOS transistor PM2 subunit constitute B basic functional units, and then the remaining AB power MOS transistor PM0 subunits and B basic functional units are evenly distributed according to the layout requirements of the power MOS.

[0040] The substrate potential selection MOS transistor PM1 and PM2 subunits are symmetrically arranged on either side of the power MOS transistor PM0 subunit, using either axisymmetry or point symmetry. Specifically, the PM1 and PM2 subunits are axisymmetric (mirror-symmetric) about the vertical centerline of the power MOS transistor PM0 subunit, or point-symmetric about the center of the power MOS transistor PM0 subunit (the PM1 subunit overlaps with the PM2 subunit after rotating 180° around the center of the power MOS transistor PM0 subunit). This ensures consistent electrical characteristics and thermal distribution across the entire integrated substrate potential selection structure. Prioritizing the symmetry of the power MOS transistor current paths during layout prevents performance deviations caused by uneven current flow.

[0041] Figure 5 In the figure, component 1 is the N-type doping in the integrated structure for substrate selection and substrate contact; component 2 is the P-type doping for the source and drain of the three MOS transistors in the integrated basic functional unit, and is also the output terminal of the substrate selection MOS transistor PM1, integrated into the same active area; component 3 is the CONT contact hole, a connection hole between the active area and the first layer of metal; component 4 is the gate polysilicon of the substrate selection MOS transistor PM1; component 5 is the N-type doped active area, serving as the upper and lower substrate contact structure of the basic functional unit; component 6 is the gate polysilicon of the power MOS transistor PM0; component 7 is the gate polysilicon of the substrate selection MOS transistor PM2; component 8 is the N-type doping for the substrate contact potential of the three MOS transistors in the integrated basic functional unit, and is also the P-type doping for the output terminal of the substrate selection MOS transistor PM1, integrated into the same active area and CONT contact hole, with the two doping types being separated by the centerline of the CONT contact hole.

[0042] Figure 6In the figure, component 1 is the N-type doping in the integrated structure for substrate selection and substrate contact; component 2 is the P-type doping for the source and drain of the three MOS transistors in the integrated basic functional unit; component 3 is the CONT contact hole, a connection hole between the active area and the first metal layer; component 4 is the gate polysilicon of the substrate selection MOS transistor PM1; component 5 is the N-type doped active area, serving as the upper and lower substrate contact structure of the basic functional unit; component 6 is the gate polysilicon of the power MOS transistor PM0; component 8 is the N-type doping for the substrate contact potential of the three MOS transistors in the integrated basic functional unit, and is also the P-type doping for the output end of the substrate selection MOS transistor PM1, integrated into the same active area and CONT contact hole, with the two doping types being separated by the centerline of the CONT contact hole; component 9 is the integration of the source end of the power MOS transistor PM0 and the input drain end of the substrate selection MOS transistor PM1 through a shared P-type active area and CONT contact hole; component 10 is the drain end B of the power MOS transistor PM0.

[0043] like Figure 5 and Figure 6 As shown, in the basic functional unit 100, the source and drain terminals of the power MOS transistor PM0 sub-unit, the substrate potential selection MOS transistor PM1 sub-unit, and the substrate potential selection MOS transistor PM2 sub-unit are merged into a whole through a shared P-type implanted active region and a CONT contact hole. At the same time, the input terminals of the substrate potential selection MOS transistor PM1 sub-unit and the substrate potential selection MOS transistor PM2 sub-unit on both sides are also connected to the source and drain terminals of the power MOS transistor PM0 sub-unit, eliminating the need for two wiring connections between the substrate selection MOS and the source and drain of the power MOS transistor.

[0044] In the basic functional unit, the output ends of the substrate potential selection MOS transistor PM1 subunit and the substrate potential selection MOS transistor PM2 subunit are respectively located at the outermost sides of the basic functional unit. The output ends of the substrate potential selection MOS transistor PM1 subunit and the substrate potential selection MOS transistor PM2 subunit are divided by the center line of the CONT contact hole. The output end located on the inner side maintains P-type doping to serve as the source end of the substrate potential selection MOS transistor PM1 subunit or the substrate potential selection MOS transistor PM2 subunit, and the output end located on the outer side is N-doped to serve as the substrate contact structure of the substrate potential selection MOS transistor PM1 subunit or the substrate potential selection MOS transistor PM2 subunit. This realizes the integration of the output ends of the two MOS substrate potential switching MOS transistors and the substrate contact structure, making the substrate potential connection more secure and saving area.

[0045] Figure 7In the embodiment, component 1a is the N-type doping in the integrated structure where the integrated substrate potential selection MOS transistor PM1 contacts the substrate; component 1b is the N-type doping in the integrated structure where the integrated substrate potential selection MOS transistor PM2 contacts the substrate; component 2a is the P-type doping at the output drain of the integrated substrate potential selection MOS transistor PM1; component 2b is the P-type doping at the output drain of the integrated substrate potential selection MOS transistor PM2; component 4 is the gate polysilicon of the substrate selection MOS transistor PM1; component 6 is the gate polysilicon of the power MOS transistor PM0; component 7 is the gate polysilicon of the substrate potential selection MOS transistor PM2; component 8a is the integrated base The N-type doping of the substrate contact potential of the three MOS transistors in the functional unit, which is also the P-type doping of the output end of the substrate potential selection MOS transistor PM1, is integrated into the same active area and CONT contact hole, with the center line of the CONT contact hole as the boundary between the two dopings; component 8b is the N-type doping of the substrate contact potential of the three MOS transistors in the integrated basic functional unit, which is also the P-type doping of the output end of the substrate potential selection MOS transistor PM2, which is integrated into the same active area and CONT contact hole, with the center line of the CONT contact hole as the boundary between the two dopings; component 9 is the source end of the power MOS transistor PM0 and the input drain end of the substrate potential selection MOS transistor PM1, which are connected to the C through a shared P-type active area. ONT contact holes are used for integration; component 10 is the drain terminal of the power MOS transistor PM0; component 11 is the first layer of metal, the substrate potential selection MOS transistor PM1 selected substrate potential output; component 12 is the first layer of metal, the substrate potential selection MOS transistor PM1 gate control signal; component 13 is the first layer of metal, the drain terminal B of the power MOS transistor PM0 and the input drain terminal of the substrate potential selection MOS transistor PM1; component 14 is VIA1, the connecting hole between the first layer of metal and the second layer of metal; component 15 is the second layer of metal, the drain terminal B of the power MOS transistor PM0; component 16 is the first layer of metal, the gate control signal of the power MOS transistor PM0; component 17 is V IA2 is a connecting via connecting the first metal layer and the second metal layer. Component 18 is the second metal layer, serving as the source terminal A of the power MOS transistor PM0. Component 19 is the first metal layer, serving as the gate control signal for the substrate potential selection MOS transistor PM2. Component 20 is the first metal layer, serving as the substrate potential output selected by the substrate potential selection MOS transistor PM2. Component 21 is a silicon dioxide-filled insulating dielectric. Component 22 represents the power MOS transistors omitted in the screenshot. The number of power MOS transistors PM0 is 2n+1. Component 23 is the integration of the source terminal of the power MOS transistor PM0 and the input drain terminal of the substrate potential selection MOS transistor PM2 through a shared P-type active region and a CONT contact hole.

[0046] Figure 8In the embodiment, component 1a is the N-type doping in the integrated structure where the integrated substrate potential selection MOS transistor PM1 contacts the substrate; component 1b is the N-type doping in the integrated structure where the integrated substrate potential selection MOS transistor PM2 contacts the substrate; component 2a is the P-type doping of the output drain end of the integrated substrate potential selection MOS transistor PM1; component 2b is the P-type doping of the output drain end of the integrated substrate potential selection MOS transistor PM2; component 4 is the polysilicon gate of the substrate potential selection MOS transistor PM1; component 7 is the polysilicon gate of the substrate potential selection MOS transistor PM2; component 9 is the source end of the power MOS transistor PM0 and the input drain end of the substrate potential selection MOS transistor PM1, which are integrated through a shared P-type active region and a CONT contact hole; component 11 is the first layer of metal, the substrate potential selection MOS transistor PM1 is the P-type doping of the output drain end of the substrate potential selection MOS transistor PM2; component 12 is the P-type doping of the output drain end of the substrate potential selection MOS transistor PM1; component 13 is the P-type doping of the output drain end of the substrate potential selection MOS transistor PM2; component 14 is the P-type doping of the output drain end of the substrate potential selection MOS transistor PM1; component 15 is the P-type doping of the output drain end of the substrate potential selection MOS transistor PM2; component 16 is the P-type doping of the output drain end of the substrate potential selection MOS transistor PM1; component 17 is the P-type doping of the output drain end of the substrate potential selection MOS transistor PM2; component 18 is the P-type doping of the output drain end of the substrate potential selection MOS transistor PM1; component 19 is the P-type doping of the output drain end of the substrate potential selection MOS transistor PM1; component 20 is the P-type doping of the output drain end of the substrate potential selection MOS transistor PM2; component 21 is the P-type doping of the output drain end Component 12 is the first layer of metal, and the substrate potential selects the gate control signal of the MOS transistor PM1. Component 14 is VIA1, a connecting through hole between the first and second layers of metal. Component 15 is the second layer of metal, and the drain terminal B of the power MOS transistor PM0. Component 17 is VIA2, a connecting through hole between the first and second layers of metal. Component 18 is the second layer of metal, and the source terminal A of the power MOS transistor PM0. Component 19 is the first layer of metal, and the substrate potential selects the gate control signal of the MOS transistor PM2. Component 20 is the first layer of metal, and the substrate potential selects the substrate potential output of the MOS transistor PM2. Component 23 is the source terminal of the power MOS transistor PM0 and the input drain terminal of the substrate potential select MOS transistor PM2, which are integrated through a shared P-type active region and a CONT contact hole.

[0047] Figure 9 In the figure, component 4 is the gate polysilicon of the substrate potential selection MOS transistor PM1; component 6 is the gate polysilicon of the power MOS transistor PM0; component 7 is the gate polysilicon of the substrate potential selection MOS transistor PM2; component 14 is VIA1, a connecting via between the first layer metal and the second layer metal; component 15 is the second layer metal, the drain terminal B of the power MOS transistor PM0; component 17 is VIA2, a connecting via between the first layer metal and the second layer metal; component 18 is the second layer metal, the source terminal A of the power MOS transistor PM0; component 25 is the second layer metal, a gate control signal of the power MOS transistor PM0 that passes horizontally through the gate; component 26 is the second layer metal, a gate control signal of the substrate potential selection MOS transistor PM1 that passes horizontally through the gate; component 27 is the second layer metal, a gate control signal of the substrate potential selection MOS transistor PM2 that passes horizontally through the gate; component 28 is the second layer metal, a gate control signal of the power MOS transistor PM0 that passes horizontally through the lower portion.

[0048] like Figure 7 、 8As shown in , 9 , a second metal layer is provided laterally on the upper and lower sides of the basic functional unit 100, respectively. The second metal layer is provided with a gate control signal of the power MOS transistor PM0, a gate control signal of the substrate potential selection MOS transistor PM1, and a gate control signal of the substrate potential selection MOS transistor PM2 that pass through the second metal layer. The gate control signal of the substrate potential selection MOS transistor PM1 and the gate control signal of the substrate potential selection MOS transistor PM2 that pass through the second metal layer respectively control the substrate potential selection MOS transistor PM1 and the substrate potential selection MOS transistor PM2 to select and output the source end or the drain end of the power MOS transistor PM0 as the substrate potential of the power MOS transistor PM0.

[0049] In the basic functional unit, an N-type doped active region serves as the substrate contact and is arranged on the upper and lower sides of the basic functional unit. A first layer of metal fully connects the output terminals of the substrate potential selection MOS on both sides to the substrate contact integrated structure, ensuring that the output substrate potential is uniformly and stably applied to the power MOS through the substrate contact integrated structure. The substrate contact integrated structure comprises components 1, 2, and 8, which are integrated onto the same active region. The contact hole CONT of component 8 is bisected along the centerline, with one half connected to the substrate contact of component 1 and the other half connected to the output terminal of the substrate potential selection MOS of component 2, forming the substrate contact integrated structure.

[0050] Based on the power transistor geometry and current distribution, these basic functional units are appropriately deployed to form a complete integrated layout structure for rapid selection of the power MOS substrate potential. The spacing and arrangement of each basic functional unit are ensured to maximize chip area utilization and ensure uniform current distribution to avoid local hotspots. Finally, the electrical connections are verified for correctness and compatibility using layout verification tools such as Calibre.

[0051] In the present invention, each substrate potential selection MOS transistor subunit can be driven by an independent control signal, thereby realizing a multi-point drive mechanism for the substrate region of the power MOS transistor PM0. The control signal can come from different channels output by the same controller, or be distributed through a buffer / driver and applied to each subunit separately.

[0052] This invention uses a multi-point drive mechanism, where multiple basic functional units act simultaneously on the substrate area of ​​the power MOS, resulting in a more uniform substrate potential distribution. Compared to traditional single-point drive methods, this invention significantly reduces the risk of local potential fluctuations and improves the stability and reliability of circuit operation.

[0053] Since multiple basic functional units work in parallel in the present invention, the time to establish the substrate potential is greatly shortened, thereby improving the overall potential switching speed, meeting application scenarios with high requirements for fast response, such as high-frequency switching power supplies.

[0054] The potential uniformity optimization brought about by the multi-point driving of the present invention helps to suppress the parasitic transistor turn-on caused by local potential differences, thereby reducing the potential latch-up risk and improving the safety and long-term stability of the chip.

[0055] Through a symmetrical layout, the present invention not only ensures consistency in current-carrying capacity and temperature distribution across each subunit, but also effectively prevents the formation of local hotspots, thereby improving the device's overall thermal stability and long-term reliability. The metal wiring between the power MOS transistor and its corresponding substrate potential selection subunit is minimized to reduce the effects of parasitic resistance and inductance. Connections preferably utilize a first or second metal layer made of a low-resistance material (such as copper or aluminum). Wide metal wires or multi-layer metal stacks can be used on critical paths to further reduce parasitic impedance. Sufficient contact holes (vias) are provided at connection nodes to ensure good conduction performance.

[0056] During the layout and routing process, a matching routing strategy is adopted for the substrate drive signal line to try to maintain the consistency of its routing length, width and adjacent ground line configuration to reduce mismatch and noise interference during signal transmission.

[0057] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment as above, it is not intended to limit the present invention. Any technician familiar with the present profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical content disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement of the above embodiments made according to the technical essence of the present invention, within the spirit and principles of the present invention, without departing from the content of the technical solution of the present invention, shall still fall within the scope of protection of the technical solution of the present invention.

Claims

1. An integrated layout structure capable of rapidly selecting a power MOS substrate potential, characterized by: The device comprises a power MOS transistor PMO, a substrate potential selection MOS transistor PM1, and a substrate potential selection MOS transistor PM2. The power MOS transistor PMO is split into A power MOS transistor PM0 subunits, and the substrate potential selection MOS transistor PM1 and the substrate potential selection MOS transistor PM2 are split into B substrate potential selection MOS transistor PM1 subunits and substrate potential selection MOS transistor PM2 subunits, respectively. A ≥ B. One power MOS transistor PM0 subunit, one substrate potential selection MOS transistor PM1 subunit, and one substrate potential selection MOS transistor PM2 subunit constitute a basic functional unit. In one basic functional unit, the substrate potential selection MOS transistor PM1 subunit and the substrate potential selection MOS transistor PM2 subunit are symmetrically arranged on both sides of the power MOS transistor PM0 subunit. In the basic functional unit, the output ends of the substrate potential selection MOS transistor PM1 subunit and the substrate potential selection MOS transistor PM2 subunit are respectively located at the outermost sides of the basic functional unit. The output ends of the substrate potential selection MOS transistor PM1 subunit and the substrate potential selection MOS transistor PM2 subunit are divided by the center line of the CONT contact hole. The output end located on the inner side maintains P-type doping and serves as the source end of the substrate potential selection MOS transistor PM1 subunit or the substrate potential selection MOS transistor PM2 subunit, and the output end located on the outer side is N-doped to become the substrate contact structure of the substrate potential selection MOS transistor PM1 subunit or the substrate potential selection MOS transistor PM2 subunit.

2. The integrated layout structure capable of quickly selecting the power MOS substrate potential according to claim 1, characterized in that: The number of the power MOS transistor PM0 subunit, the substrate potential selection MOS transistor PM1 subunit and the substrate potential selection MOS transistor PM2 subunit is an odd number.

3. The integrated layout structure capable of quickly selecting the power MOS substrate potential according to claim 2, characterized in that: The B power MOS transistor PM0 subunits, substrate potential selection MOS transistor PM1 subunit and substrate potential selection MOS transistor PM2 subunit constitute B basic functional units, and then the remaining AB power MOS transistor PM0 subunits are evenly distributed with the B basic functional units.

4. The integrated layout structure capable of quickly selecting the power MOS substrate potential according to claim 1, characterized in that: The substrate potential selection MOS transistor PM1 subunit and the substrate potential selection MOS transistor PM2 subunit are symmetrically arranged on both sides of the power MOS transistor PM0 subunit in an axial symmetry or a point symmetry.

5. The integrated layout structure capable of quickly selecting the power MOS substrate potential according to claim 1, characterized in that: In the basic functional unit, the source and drain terminals of the power MOS transistor PM0 sub-unit, the substrate potential selection MOS transistor PM1 sub-unit, and the substrate potential selection MOS transistor PM2 sub-unit are merged into a whole through a shared P-type implanted active region and a CONT contact hole. At the same time, the input terminals of the substrate potential selection MOS transistor PM1 sub-unit and the substrate potential selection MOS transistor PM2 sub-unit on both sides are also connected to the source and drain terminals of the power MOS transistor PM0 sub-unit.

6. The integrated layout structure capable of quickly selecting the power MOS substrate potential according to claim 1, characterized in that: A second metal layer is disposed laterally on the upper and lower sides of the basic functional unit, respectively. The second metal layer is provided with a gate control signal of the power MOS transistor PM0, a gate control signal of the substrate potential selection MOS transistor PM1, and a gate control signal of the substrate potential selection MOS transistor PM2, which are both laterally penetrating the second metal layer. The gate control signal of the substrate potential selection MOS transistor PM1 and the gate control signal of the substrate potential selection MOS transistor PM2 respectively control the substrate potential selection MOS transistor PM1 and the substrate potential selection MOS transistor PM2 to select and output the source end or the drain end of the power MOS transistor PM0 as the substrate potential of the power MOS transistor PM0.

7. The integrated layout structure capable of quickly selecting the power MOS substrate potential according to claim 1, characterized in that: In the basic functional unit, an N-type doped active area is used as a substrate contact and is arranged on the upper and lower sides of the basic functional unit, and the output ends of the MOS for substrate potential selection on both sides are fully connected to the substrate contact integrated structure using a first layer of metal.

Images