Passivation layer manufacturing method, TOPCon battery and manufacturing method of TOPCon battery

Abstract

According to the passivation layer manufacturing method, the TOPCon battery and the manufacturing method of the TOPCon battery, a high-quality, uniform and compact oxidation protection layer is formed through the strong oxidizing property of ozone, the effect of protecting a silicon wafer is achieved, the oxidation protection layer and a silicon oxide layer jointly serve as a tunneling oxide layer, the compactness is good, a good field passivation effect can be formed on the surface of a silicon substrate, and the performance of the TOPCon battery is improved. Meanwhile, bombardment damage of plasma to the surface of the silicon wafer is reduced, and surface recombination is reduced. The intrinsic polycrystalline silicon layer can bear internal expansion of phosphorus sources in the in-situ doped polycrystalline silicon layer in a subsequent high-temperature annealing process to play a buffering role, so that the number of the phosphorus sources entering the silicon substrate through the tunneling oxide layer is reduced, the passivation quality is ensured, and the service life of the silicon substrate is prolonged. Meanwhile, phosphorus atoms in the in-situ doped polycrystalline silicon layer can enter the intrinsic polycrystalline silicon layer for doping through annealing, and field passivation and gettering are provided. The mask can prevent the polycrystalline silicon layer from being damaged by subsequent wet cleaning. Therefore, the efficiency of the TOPCon battery can be improved.

Description

Technical Field

[0001] The present application relates to the field of photovoltaic technology, and in particular to a passivation layer manufacturing method, a TOPCon cell and a manufacturing method thereof. Background Art

[0002] High-efficiency crystalline silicon solar cells - Tunnel Oxide Passivated Contact solar cells (TOPCon), which use a tunnel oxide passivated contact structure, namely an ultra-thin SiO2 layer + doped polysilicon (i-poly Si) layer. This structure allows electrons to tunnel through the oxide layer while blocking hole recombination, increasing the open circuit voltage (Voc) and short circuit current (Jsc), significantly reducing carrier recombination caused by direct contact between the metal and the silicon substrate, and greatly improving cell efficiency.

[0003] However, the inventors have found that the current process has some problems:

[0004] (1) The PECVD method has a faster production speed than the LPCVD method and can produce doped polysilicon layers with different doping concentrations and dopants. However, in the process of using ionized nitrous oxide plasma and silicon atoms on the surface of the silicon substrate to generate a tunneling oxide layer, the plasma will destroy the silicon surface, causing plasma bombardment damage.

[0005] (2) The phosphorus sources in the in-situ doped polysilicon will enter the silicon substrate in large quantities through the tunneling layer during the subsequent annealing process. The phosphorus atom content in the silicon substrate is enriched around the oxide layer, affecting the passivation quality.

[0006] The above problems will limit the further improvement of TOPCon high-efficiency battery efficiency. Summary of the Invention

[0007] The present application provides a passivation layer manufacturing method, a TOPCon battery and a manufacturing method thereof, which improve the efficiency of the TOPCon battery.

[0008] The embodiment of the present application is implemented as follows:

[0009] In a first aspect, the present invention provides a method for manufacturing a passivation layer, comprising the following steps:

[0010] Ozone is introduced to oxidize the polished surface of the silicon wafer to form an oxide protective layer;

[0011] depositing a silicon oxide layer on the oxide protection layer;

[0012] depositing an intrinsic polysilicon layer on the silicon oxide layer;

[0013] depositing an in-situ doped polysilicon layer on the intrinsic polysilicon layer;

[0014] A mask is deposited on the in-situ doped polysilicon layer.

[0015] In an optional embodiment, in the step of introducing ozone to oxidize the polished surface of the silicon wafer to form an oxide protective layer, the flow rate of the ozone is 500 sccm-1000 sccm, and the time is 100 s-200 s.

[0016] In an optional embodiment, in the step of depositing the silicon oxide layer on the oxidation protection layer, a laughing gas atmosphere is introduced to deposit the silicon oxide layer;

[0017] Set the time for introducing nitrous oxide to 50S-150S, the temperature to 430℃-450℃, the nitrous oxide flow rate to 8000sccm-12000sccm, the RF power to 11KHz-15KHz, the RF duty cycle to 20ms / 2000ms, and the pressure to 1000mtorr-1500mtorr.

[0018] In an optional embodiment, in the step of depositing an intrinsic polysilicon layer on the silicon oxide layer, a silane atmosphere is introduced to deposit the intrinsic polysilicon layer, and the time for introducing the silane atmosphere is set to 80S-100S, the temperature is 430℃-450℃, the silane flow rate is 2500sccm-3200sccm, the hydrogen flow rate is 8000sccm-10000sccm, the RF power is 11KHz-15KHz, the RF duty cycle is 30ms / 540ms, and the pressure is 2500mtorr-3000mtorr.

[0019] In an optional embodiment, in the step of depositing the in-situ doped polysilicon layer on the intrinsic polysilicon layer, a phosphorus-doped polysilicon layer containing carbon is deposited in-situ.

[0020] In an optional embodiment, a silane, phosphine, methane and hydrogen atmosphere is introduced to deposit an in-situ doped carbon-containing phosphorus-doped polysilicon layer;

[0021] Set the time for introducing the atmosphere to 600S-800S, the temperature to 430℃-450℃, the silane flow rate to 2500sccm-3200sccm, the 2% phosphine flow rate to 2800sccm-3200sccm, the methane flow rate to 200sccm-1000sccm, the hydrogen flow rate to 6000sccm-9000sccm, the RF power to 11KHz-15KHz, the RF duty cycle to 30ms / 540ms, and the pressure to 3300mtorr-3700mtorr.

[0022] In an optional embodiment, in the step of depositing a mask on the in-situ doped polysilicon layer, laughing gas is introduced to deposit a silicon dioxide mask;

[0023] Set the time to 30S-100S, the temperature to 430℃-450℃, the silane flow rate to 1000sccm-2000sccm, the nitrous oxide flow rate to 6000sccm-8000sccm, the RF power to 10KHz-12KHz, the RF duty cycle to 30ms / 480ms, and the pressure to 1200mtorr-1500mtorr.

[0024] In a second aspect, the present invention provides a method for manufacturing a TOPCon battery, comprising the following steps:

[0025] Pre-treatment process: The silicon wafer is cleaned and textured, boron is diffused to prepare PN junction, BSG is removed from the back and edge, and the back is alkaline polished;

[0026] Polysilicon passivation layer fabrication step: fabricating a passivation layer on the back side of the silicon wafer using the passivation layer fabrication method described in any of the aforementioned embodiments;

[0027] Post-processing steps: annealing, PSG removal, RCA cleaning, front ALD to generate aluminum oxide film, front PECVD to coat SiNx film, back PECVD to coat SiNx film, metallization printing on the front and back of silicon wafers, pre-sintering and light injection treatment of silicon wafers, and laser sintering of silicon wafers.

[0028] In a third aspect, the present invention provides a TOPCon cell, which is manufactured using the TOPCon cell manufacturing method described in the aforementioned embodiment, and includes a silicon wafer and a passivation layer located on the back of the silicon wafer, wherein the passivation layer includes an oxidation protection layer, a silicon oxide layer, an intrinsic polysilicon layer, an in-situ doped polysilicon layer and a mask stacked in sequence.

[0029] In an optional embodiment, the thickness of the oxidation protection layer is 0.2-0.7 nm;

[0030] The thickness of the silicon oxide layer is 1.0 nm to 1.3 nm;

[0031] The thickness of the intrinsic polysilicon layer is 20nm-40nm;

[0032] The thickness of the in-situ doped polysilicon layer is 70nm-110nm;

[0033] The thickness of the mask is 10nm-30nm.

[0034] The beneficial effects of this application include:

[0035] The strong oxidizing properties of ozone are used to form a high-quality, uniform, and dense oxide layer to protect the silicon wafer. Furthermore, ozone-generated oxide layers are relatively gentle and do not damage the silicon substrate surface. During the deposition of the oxide layer on top of the oxide layer, plasma bombardment occurs directly on the oxide layer, preventing direct plasma bombardment of the silicon wafer and minimizing damage to the wafer surface and plasma. Ozone oxidation alone results in a loose and porous oxide layer, which cannot effectively passivate or tunnel. Therefore, the oxide layer and silicon oxide layer together act as a dense tunneling oxide layer, providing excellent field passivation on the silicon substrate surface while simultaneously reducing plasma damage to the wafer surface and minimizing surface recombination. The tunneling oxide layer, through quantum tunneling, allows efficient electron transfer to the polysilicon layer while simultaneously blocking the flow of holes, ensuring efficient electron transfer while minimizing carrier recombination losses. An intrinsic polysilicon layer refers to a polysilicon layer that has not been intentionally doped. This means it contains neither significant concentrations of n-type dopants (such as phosphorus or arsenic) nor p-type dopants (such as boron). This type of polysilicon has relatively high resistivity, and its electrical properties are primarily determined by defects and naturally occurring impurities in the material. In-situ doping of the polysilicon layer involves directly introducing dopants during the polysilicon deposition process to create a polysilicon layer with specific electrical properties. This method allows for precise control of doping concentration and distribution, avoiding the complexity and potential problems of subsequent ion implantation or diffusion processes. The intrinsic polysilicon layer can accommodate the internal diffusion of phosphorus atoms from the in-situ doped polysilicon layer during the subsequent high-temperature annealing process, acting as a buffer. This reduces the number of phosphorus atoms that penetrate the tunneling oxide layer into the silicon substrate and reduces the concentration of phosphorus atoms in the silicon substrate around the oxide layer, thereby ensuring passivation quality. Simultaneously, the annealing process allows phosphorus atoms from the in-situ doped polysilicon layer to enter the intrinsic polysilicon layer for doping, providing field passivation and impurity gettering. The mask prevents damage to the polysilicon layer during subsequent wet cleaning. Therefore, the passivation layer manufactured by the passivation layer manufacturing method of the present application can improve the efficiency of the TOPCon battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0037] Figure 1 This is a schematic structural diagram of the TOPCon battery according to an embodiment of the present application.

[0038] Icons: 01-silicon wafer; 02-pyramid structure; 03-polished surface; 04-oxidation protection layer; 05-silicon oxide layer; 06-intrinsic polysilicon layer; 07-in-situ doped polysilicon layer; 08-mask. DETAILED DESCRIPTION

[0039] As used herein:

[0040] "Prepared from" is synonymous with "comprising." As used herein, the terms "comprising," "including," "having," "containing," or any other variations thereof, are intended to cover a non-exclusive inclusion. For example, a composition, process, method, article, or apparatus that comprises the listed elements is not necessarily limited to only those elements but may include other elements not expressly listed or inherent to such composition, process, method, article, or apparatus.

[0041] When an amount, concentration, or other value or parameter is expressed as a range, a preferred range, or a range defined by a series of upper preferred values ​​and lower preferred values, this should be understood as specifically disclosing all ranges formed by any pairing of any range upper limit or preferred value with any range lower limit or preferred value, regardless of whether the range is disclosed alone. For example, when a range of "1 to 5" is disclosed, the described range should be interpreted as including the range "1 to 4", "1 to 3", "1 to 2", "1 to 2 and 4 to 5", "1 to 3 and 5", etc. When a numerical range is described herein, unless otherwise stated, the range is intended to include its end values ​​and all integers and fractions within the range.

[0042] This application discloses a TOPCon battery manufacturing method, which includes the following steps:

[0043] (1) Pre-treatment process: The silicon wafer 01 is cleaned and textured, and the boron diffusion is performed to prepare the PN junction, and the back and edge BSG is removed and the back is alkaline polished;

[0044] The pre-treatment process in the production of TOPCon batteries lays a good foundation for subsequent processes and ensures the quality and performance of the final product.

[0045] In detail, the purpose of cleaning and texturing is to remove pollutants on the surface of the silicon wafer 01 and to increase the surface area by texturing to improve light absorption efficiency.

[0046] Cleaning: Chemical solutions such as hydrofluoric acid (HF), nitric acid (HNO3) or sulfuric acid (H2SO4) are usually used for cleaning to remove the natural oxide layer and other organic / inorganic contaminants on the surface of the silicon wafer 01.

[0047] Texturing: For single-crystal silicon, alkaline solutions (such as KOH or NaOH) are commonly used for anisotropic etching to form a pyramid structure 02; for polycrystalline silicon, acid etching (such as a mixture of HF and HNO3) may be used to form a random texture to increase the light capture effect.

[0048] The purpose of boron diffusion to create a PN junction is to form a p-type layer by doping boron atoms on the surface of the silicon wafer (01). This layer then forms a PN junction with the n-type substrate. This PN junction is the core component of the solar cell, responsible for converting light energy into electrical energy. The diffusion process involves placing the silicon wafer (01) in a high-temperature furnace containing a boron source gas (such as boron tribromide (BBr3)) at temperatures between 800°C and 1100°C. This step creates a heavily doped p-type region on the surface of the silicon wafer (01).

[0049] Backside and edge BSG removal aims to remove the borosilicate glass (BSG) formed during the diffusion process to prevent it from adversely affecting subsequent processes. This removal method typically uses a hydrofluoric acid (HF) solution to etch away the BSG layer. This step is not limited to the backside but also includes the edges, as BSG at the edges can cause short circuits or other electrical problems.

[0050] Backside alkaline polishing is used to improve backside quality and reduce surface defects. It is also sometimes used to adjust backside reflectivity to optimize cell efficiency. This treatment involves using an alkaline solution (such as KOH or NaOH) to perform a slight etching to remove a small amount of silicon material, resulting in a smoother surface.

[0051] The above four steps constitute the key pre-processing process in TOPCon battery manufacturing. Each step is designed to lay a good foundation for subsequent processes and ensure that the final product has high efficiency and reliability.

[0052] (2) Polysilicon passivation layer fabrication process: The passivation layer is mainly used to reduce carrier recombination caused by surface defects, thereby improving device efficiency. The passivation layer fabrication method mainly includes the following steps:

[0053] Ozone is introduced to oxidize the polished surface 03 of the silicon wafer 01 to form an oxide protective layer 04;

[0054] A silicon oxide layer 05 is deposited on the oxidation protection layer 04, and the silicon oxide layer 05 and the oxidation protection layer 04 are stacked together to serve as a tunneling oxide layer;

[0055] Depositing an intrinsic polysilicon layer 06 on the silicon oxide layer 05;

[0056] Depositing an in-situ doped polysilicon layer 07 on the intrinsic polysilicon layer 06;

[0057] A mask 08 is deposited on the in-situ doped polysilicon layer 07 .

[0058] The above-mentioned passivation layer fabrication method utilizes the strong oxidizing properties of ozone to form a high-quality, uniform, and dense oxide protection layer 04 (also known as silicon dioxide layer 05), which plays a role in protecting silicon wafer 01. Moreover, the ozone-generated oxide protection layer 04 is relatively gentle and does not damage the surface of the silicon substrate. Thus, during the process of depositing the oxide layer on the oxide protection layer 04, plasma bombardment on the oxide protection layer 04 prevents the plasma from directly bombarding the silicon wafer 01, thereby reducing damage to the surface of the silicon wafer 01 and the plasma. If only ozone oxidation is used, the resulting oxide layer is loose and porous, unable to form an effective passivation and tunneling effect. Therefore, the oxide protection layer 04 and the silicon oxide layer 05 together act as a tunneling oxide layer with good density, not only forming a good field passivation effect on the silicon substrate surface, but also reducing plasma bombardment damage to the surface of the silicon wafer 01 and reducing surface recombination. The tunneling oxide layer allows electrons to be efficiently transmitted to the polysilicon layer through the quantum tunneling effect, while blocking the flow of holes, ensuring electron transmission efficiency while minimizing carrier recombination losses. The intrinsic polysilicon layer 06 is a polysilicon layer that has not been intentionally doped. This means it contains neither significant concentrations of n-type dopants (such as phosphorus or arsenic) nor p-type dopants (such as boron). This type of polysilicon has a relatively high resistivity, and its electrical properties are primarily determined by defects and naturally occurring impurities within the material. In-situ doping of the polysilicon layer 07 involves directly introducing dopants during the polysilicon deposition process to form a polysilicon layer with specific electrical properties. This method allows for precise control of doping concentration and distribution, avoiding the complexity and potential problems associated with subsequent ion implantation or diffusion processes. The intrinsic polysilicon layer 06 acts as a buffer for the internal diffusion of phosphorus atoms from the in-situ doped polysilicon layer 07 during the subsequent high-temperature annealing process. This acts as a buffer, reducing the number of phosphorus atoms that penetrate the tunneling oxide layer into the silicon substrate and reducing the concentration of phosphorus atoms within the silicon substrate around the oxide layer, thereby ensuring passivation quality. Furthermore, during the annealing process, phosphorus atoms from the in-situ doped polysilicon layer 07 can enter the intrinsic polysilicon layer 06 for doping, providing field passivation and gettering. The mask 08 can prevent the subsequent wet cleaning from damaging the polysilicon layer. Therefore, the passivation layer manufactured by the passivation layer manufacturing method of the present application can improve the efficiency of the TOPCon cell.

[0059] (3) Post-processing steps: annealing, PSG removal, RCA cleaning, front ALD to generate aluminum oxide film, front PECVD to coat SiNx film, back PECVD to coat SiNx film, metallization printing on the front and back of silicon wafer 01, pre-sintering and light injection treatment of silicon wafer 01, and laser sintering of silicon wafer 01.

[0060] The post-processing step is to improve the conversion efficiency of TOPCon cells and enhance their long-term stability and reliability.

[0061] Specifically, annealing repairs crystal defects, reduces stress, and improves material quality. Its importance stems from the fact that high-temperature treatment eliminates damage and defects caused by previous processes, increasing carrier lifetime within the silicon wafer 01 and thereby boosting cell efficiency. Furthermore, annealing allows phosphorus atoms from the in-situ doped polysilicon layer 07 during the polysilicon fabrication process to enter the intrinsic polysilicon layer 06, providing field passivation and gettering.

[0062] PSG removal (phosphosilicate glass, PSG) removes the phosphorus-rich silicon dioxide layer (PSG) formed during the diffusion process to prevent it from absorbing water and contaminating subsequent processes. If the PSG layer is not removed in a timely manner, it will affect the quality of subsequent films and may cause device performance degradation.

[0063] RCA cleaning thoroughly cleans the surface of the silicon wafer 01, removing organic matter, metal ions, and other contaminants. This ensures surface cleanliness and safeguards the battery's electrical performance and long-term stability. The main steps include an SC-1 clean (ammonia-hydrogen peroxide solution) to remove organic contaminants and particles, followed by a deionized water rinse and an SC-2 clean (hydrochloric acid-hydrogen peroxide solution) to remove metal ions and other inorganic contaminants. Finally, rinse the wafer 01 with plenty of deionized water to ensure that all chemical residues are completely removed. The wafer 01 is then dried using nitrogen blow-drying or spin drying.

[0064] Aluminum oxide film (Al2O3) is generated on the front side of silicon wafer 01 by Atomic Layer Deposition (ALD) method. Aluminum oxide has excellent surface passivation ability for p-type silicon; it can provide good negative charge density, reduce the interface recombination rate, and realize the front passivation of TOPCon battery.

[0065] The front side is coated with SiNx film by PECVD, and the silicon nitride film is deposited by plasma enhanced chemical vapor deposition (Plasma Enhanced CVD). The functions of the silicon nitride film are: as an anti-reflection layer to reduce light reflection loss; as a surface passivation layer to improve the carrier lifetime; and as a packaging protection layer to prevent the intrusion of environmental moisture / oxygen.

[0066] The back side PECVD SiNx film has similar functions to the front side, but focuses more on increasing back reflection and improving light capture efficiency.

[0067] Screen printing is used to form electrodes for current collection and conduction. Silver paste (front) and aluminum paste (back) are typically applied to the silicon wafer using a screen printer. The front-side fine grid lines affect the cell's light shielding area and series resistance. The back-side is printed with either all-aluminum or a dotted open-hole structure (such as in PERC cells).

[0068] Pre-sintering (Drying & Firing / Pre-firing) is to dry the solvent in the metal slurry; preliminarily solidify the electrode structure; and prepare for the high-temperature sintering stage.

[0069] Light injection (or light soaking) stimulates carriers through illumination, simulating the charge state under actual operating conditions. This process accelerates the stabilization of certain material defects (such as boron-oxygen complexes), improves the stability of battery efficiency (resisting LID degradation), and is used to activate battery performance during testing.

[0070] Laser sintering (or laser annealing) aims to locally heat the metal electrode, promoting ohmic contact between the metal and the silicon substrate while avoiding extensive thermal damage. Its advantages include precise control of the sintering area, improved electrode adhesion and conductivity, and compatibility with low-temperature processes.

[0071] In the step of introducing ozone to oxidize the polished surface 03 of the silicon wafer 01 to form the oxide protective layer 04, the ozone flow rate is 500 sccm-1000 sccm, and the time is 100s-200s, thereby oxidizing a 0.2nm-0.7nm ozone silicon oxide layer 05 (i.e., the oxide protective layer 04) on the surface of the silicon wafer 01. The thickness of the oxide protective layer 04 can be any value within the range of 0.2nm-0.7nm, such as 0.2nm, 0.3nm, 0.4nm, 0.5nm, 0.6nm, 0.7nm, etc.

[0072] It should be noted that if the thickness of the oxidation protection layer 04 is too small, for example, less than 0.2nm, then it cannot form effective protection on the surface of the silicon wafer 01 and cannot reduce the damage caused by plasma bombardment. If the thickness of the oxidation protection layer 04 is too large, for example, greater than 0.7nm, then it will affect the density of the subsequent PECVD nitrous oxide-generated oxide layer and reduce the passivation effect.

[0073] In the step of depositing the silicon oxide layer 05 on the oxidation protection layer 04, a laughing gas (N2O) atmosphere is introduced to deposit the silicon oxide layer 05;

[0074] The time for introducing nitrous oxide is set to 50S-150S, the temperature is 430℃-450℃, the nitrous oxide flow rate is 8000sccm-12000sccm, the RF power is 11KHz-15KHz, the RF duty cycle is 20ms / 2000ms, and the pressure is 1000mtorr-1500mtorr, thereby forming a silicon oxide layer 05 of 1.0nm-1.3nm. The thickness of the silicon oxide layer 05 can be any value within the range of 1.0nm-1.3nm, such as 1.0nm, 1.1nm, 1.2nm, 1.3nm, etc. The silicon oxide layer 05 and the oxidation protection layer 04 are superimposed on each other as a tunneling oxide layer, so the thickness of the tunneling oxide layer is any value within the range of 1.2nm-2.0nm.

[0075] In the step of depositing the intrinsic polysilicon layer 06 on the silicon oxide layer 05, a silane atmosphere is introduced to deposit the intrinsic polysilicon layer 06, and the time for introducing the silane atmosphere is set to 80S-100S, the temperature is 430℃-450℃, the silane flow rate is 2500sccm-3200sccm, the hydrogen flow rate is 8000sccm-10000sccm, the RF power is 11KHz-15KHz, the RF duty cycle is 30ms / 540ms, and the pressure is 2500mtorr-3000mtorr, so that the thickness of the intrinsic polysilicon layer 06 is 20nm-40nm. The thickness of the intrinsic polysilicon layer 06 can specifically be 20nm, 25nm, 30nm, 35nm, 40nm or any value within the range of 20nm-40nm.

[0076] It should be noted that the heavily doped polysilicon used in the prior art TOPCon may cause parasitic absorption, resulting in optical loss and reduced photoelectric conversion efficiency.

[0077] In order to improve the above problem, in the step of depositing the in-situ doped polysilicon layer 07 on the intrinsic polysilicon layer 06 , a phosphorus-doped polysilicon layer in-situ doped with carbon is deposited.

[0078] The refractive index and extinction coefficient of carbon-containing phosphorus-doped polysilicon are lower than those of conventional phosphorus-doped polysilicon, which can reduce parasitic absorption of long waves. In addition, carbon and silicon both have four electrons in their outer layers and are elements of the same main group, making them easy to form four covalent bonds. Carbon can be substitutionally doped in polysilicon, replacing the position of silicon without changing the crystal structure. Therefore, carbon-doped polysilicon can substitute to form covalent bonds, resulting in a stable structure without affecting the crystal structure of polysilicon. In addition, carbon atoms can capture hydrogen atoms, adjust the work function of the material, and affect the diffusion and activation of phosphorus atoms, thereby improving the passivation quality, reducing surface recombination, and thus increasing the implicit turn-on voltage and reducing the recombination current.

[0079] In the present application, a silane, phosphine, methane and hydrogen atmosphere is introduced to deposit an in-situ doped carbon-containing phosphorus-doped polysilicon layer;

[0080] The time for introducing the atmosphere is set to 600S-800S, the temperature is 430℃-450℃, the silane flow rate is 2500sccm-3200sccm, the 2% phosphine flow rate is 2800sccm-3200sccm, the methane flow rate is 200sccm-1000sccm, the hydrogen flow rate is 6000sccm-9000sccm, the RF power is 11KHz-15KHz, the RF duty cycle is 30ms / 540ms, and the pressure is 3300mtorr-3700mtorr, thereby generating an in-situ doped polysilicon layer 07 containing carbon and phosphorus. The thickness of the in-situ doped polysilicon layer 07 is 70nm-110nm, which can be 70nm, 80nm, 90nm, 100nm, 110nm or any value within the range of 70nm-110nm.

[0081] It should be noted that low carbon concentrations have limited or no effect, while high carbon concentrations can affect the silver-silicon contact, increasing contact resistivity and hindering electron transport. Therefore, the carbon content is controlled by controlling the reaction temperature and methane flow rate to maintain an appropriate carbon concentration.

[0082] The reason for choosing methane as the carbon source for doping is that, on the one hand, using other carbon sources, such as carbon dioxide, will actually form silicon oxide, rather than replacing the existing carbon to form carbon-containing crystalline silicon. On the other hand, using nitrogen to dope nitrogen-containing crystalline silicon is also unsuccessful because, firstly, nitrogen is difficult to ionize in the PECVD environment. Secondly, even if a small amount is ionized, it will produce a trivalent and a tetravalent silicon nitride compound, rather than substitutionally doped nitrogen-containing crystalline silicon.

[0083] In the present application, in the step of depositing the mask 08 on the in-situ doped polysilicon layer 07, laughing gas is introduced to deposit the silicon dioxide mask 08;

[0084] Set the time to 30S-100S, the temperature to 430℃-450℃, the silane flow rate to 1000sccm-2000sccm, the nitrous oxide flow rate to 6000sccm-8000sccm, the RF power to 10KHz-12KHz, the RF duty cycle to 30ms / 480ms, and the pressure to 1200mtorr-1500mtorr, thereby generating a 10nm-30nm thick silicon dioxide mask 08. The specific thickness can be 10nm, 15nm, 20nm, 25nm, 30nm or any value within the range of 10nm-30nm.

[0085] The present application also discloses a TOPCon cell, which is manufactured using the above-mentioned TOPCon cell manufacturing method. The TOPCon includes a silicon wafer 01 and a passivation layer located on the back of the silicon wafer 01. The passivation layer includes an oxidation protection layer 04, a silicon oxide layer 05, an intrinsic polysilicon layer 06, an in-situ doped polysilicon layer 07 and a mask 08 stacked in sequence; the front of the silicon wafer 01 has a pyramid structure 02. The pyramid structure 02 can capture and guide more light into the interior of the silicon material, reducing the proportion of light energy directly reflected back into the air, thereby increasing light absorption efficiency and reducing light reflection loss, thereby improving the overall conversion efficiency of the solar cell.

[0086] Among them, the thickness of the oxidation protection layer 04 is 0.2-0.7nm; the thickness of the silicon oxide layer 05 is 1.0nm-1.3nm; the thickness of the intrinsic polysilicon layer 06 is 20nm-40nm; the thickness of the in-situ doped polysilicon layer 07 is 70nm-110nm; and the thickness of the mask 08 is 10nm-30nm.

[0087] The present application is described in further detail below with reference to the examples.

[0088] Example 1

[0089] S1: Inserting the alkali-polished silicon wafer 01 into the graphite boat, sending the graphite boat into the PECVD quartz tube deposition furnace chamber through the silicon nitride slurry, and closing the furnace door;

[0090] S2: Heating and vacuuming: heating to the set temperature, then keeping the temperature constant, and vacuuming simultaneously during the heating process;

[0091] Specifically, in step S2, the time is set to 80 s, the temperature is set to 430 °C, and the pressure is set to 120 mtorr;

[0092] S3: Leak detection: Check the vacuum maintenance;

[0093] S4: ozone is passed through, and ozone oxidation forms an oxidation protection layer 04 on the polished surface 03.

[0094] Specifically, in step S4, the ozone flow rate is 500 sccm and the time is 115 seconds. A 0.2 nm thick ozone silicon oxide layer 05 is oxidized on the surface of the silicon wafer 01;

[0095] S5: Purge with nitrogen.

[0096] S6: Pre-charge: switch to laughing gas atmosphere;

[0097] S7: Oxide deposition: depositing tunnel oxide layer;

[0098] Specifically, in step S7, the time is set to 140s, the temperature is set to 440°C, the nitrous oxide flow rate is set to 12000sccm, the RF power is set to 15KHz, the RF duty cycle is set to 20ms / 2000ms, and the pressure is set to 1500mtorr. A 1.3nm silicon oxide layer 05 is generated, and the 0.2nm ozone silicon oxide layer 05 in step S4 is superimposed. The resulting tunneling silicon oxide layer 05 has a thickness of 1.5nm.

[0099] S8: Evacuate: evacuate;

[0100] S9: Pre-filling: switch to silane atmosphere;

[0101] S10: Intrinsic silicon layer deposition: depositing an intrinsic poly silicon layer;

[0102] Specifically, in step S10, the time is set to 100 seconds, the temperature is 430° C., the silane flow rate is 3200 sccm, the hydrogen flow rate is 8000 sccm, the RF power is 12 kHz, the RF duty cycle is 30 ms / 540 ms, and the pressure is 2700 mtorr; the intrinsic silicon thickness is 40 nm;

[0103] S11: Pre-filling: switching silane, phosphine, methane and hydrogen atmospheres;

[0104] S12: In-situ doped polysilicon layer 07 deposition: depositing an in-situ doped carbon-containing phosphorus-doped polysilicon layer;

[0105] Specifically, in step S12, the time is set to 800S, the temperature is 430°C, the silane flow rate is 3200sccm, the 2% phosphine flow rate is 3200sccm, the methane flow rate is 1000sccm, the hydrogen flow rate is 9000sccm, the RF power is 15KHz, the RF duty cycle is 30ms / 540ms, and the pressure is 3500mtorr; the thickness of the poly silicon containing carbon in situ doped with phosphorus is 110nm.

[0106] S13: Evacuate: evacuate;

[0107] S14: Mask 08 preparation: generating silicon dioxide mask 08;

[0108] Specifically, the S14 time is 50S, the temperature is 430°C, the silane flow rate is 1500sccm, the nitrous oxide flow rate is 7000sccm, the RF power is 10KHz, the RF duty cycle is 30ms / 480ms, and the pressure is 1200mtorr; the thickness of the silicon dioxide mask 08 is 20nm.

[0109] S15: Evacuate: evacuate;

[0110] S16: Return to normal pressure: Fill with nitrogen to restore normal pressure;

[0111] S17: Boat out: Open the furnace door, and the silicon nitride slurry pulls the graphite boat out of the quartz tube;

[0112] Example 2

[0113] S1: Inserting the alkali-polished silicon wafer 01 into the graphite boat, sending the graphite boat into the PECVD quartz tube deposition furnace chamber through the silicon nitride slurry, and closing the furnace door;

[0114] S2: Heating and vacuuming: heating to the set temperature, then keeping the temperature constant, and vacuuming simultaneously during the heating process;

[0115] Specifically, in step S2, the time is set to 80 s, the temperature is set to 430 °C, and the pressure is set to 120 mtorr;

[0116] S3: Leak detection: Check the vacuum maintenance;

[0117] S4: ozone is passed through, and ozone oxidation forms an oxidation protection layer 04 on the polished surface 03.

[0118] Specifically, in step S4, the ozone flow rate is 700 sccm and the time is 125 seconds. A 0.4 nm thick ozone silicon oxide layer 05 is oxidized on the surface of the silicon wafer 01;

[0119] S5: Purge with nitrogen.

[0120] S6: Pre-charge: switch to laughing gas atmosphere;

[0121] S7: Oxide deposition: depositing tunnel oxide layer;

[0122] Specifically, in step S7, the time is set to 125 seconds, the temperature is set to 440°C, the nitrous oxide flow rate is set to 11500 seem, the RF power is set to 14 kHz, the RF duty cycle is set to 20 ms / 2000 ms, and the pressure is set to 1500 mtorr. A 1.2 nm thick silicon oxide layer 05 is formed, and the 0.4 nm ozone oxide silicon layer 05 in step S4 is superimposed. The resulting tunneling silicon oxide layer 05 is 1.6 nm thick.

[0123] S8: Evacuate: evacuate;

[0124] S9: Pre-filling: switch to silane atmosphere;

[0125] S10: Intrinsic silicon layer deposition: depositing an intrinsic poly silicon layer;

[0126] Specifically, in step S10, the time is set to 80 seconds, the temperature is 430° C., the silane flow rate is 2800 sccm, the hydrogen flow rate is 8000 sccm, the RF power is 12 kHz, the RF duty cycle is 30 ms / 540 ms, and the pressure is 2700 mtorr; the intrinsic silicon thickness is 30 nm;

[0127] S11: Pre-filling: switching silane, phosphine, methane and hydrogen atmospheres;

[0128] S12: In-situ doped polysilicon layer 07 deposition: depositing an in-situ doped carbon-containing phosphorus-doped polysilicon layer;

[0129] Specifically, in step S12, the time is set to 800S, the temperature is 430°C, the silane flow rate is 3200sccm, the 2% phosphine flow rate is 3200sccm, the methane flow rate is 800sccm, the hydrogen flow rate is 9000sccm, the RF power is 15KHz, the RF duty cycle is 30ms / 540ms, and the pressure is 3500mtorr; the thickness of the poly silicon containing carbon in situ doped with phosphorus is 100nm.

[0130] S13: Evacuate: evacuate;

[0131] S14: Mask 08 preparation: generating silicon dioxide mask 08;

[0132] Specifically, the S14 time is 50S, the temperature is 430°C, the silane flow rate is 1500sccm, the nitrous oxide flow rate is 7000sccm, the RF power is 10KHz, the RF duty cycle is 30ms / 480ms, and the pressure is 1200mtorr; the thickness of the silicon dioxide mask 08 is 20nm.

[0133] S15: Evacuate: evacuate;

[0134] S16: Return to normal pressure: Fill with nitrogen to restore normal pressure;

[0135] S17: Boat out: Open the furnace door, and the silicon nitride slurry pulls the graphite boat out of the quartz tube;

[0136] Example 3

[0137] S1: Inserting the alkali-polished silicon wafer 01 into the graphite boat, sending the graphite boat into the PECVD quartz tube deposition furnace chamber through the silicon nitride slurry, and closing the furnace door;

[0138] S2: Heating and vacuuming: heating to the set temperature, then keeping the temperature constant, and vacuuming simultaneously during the heating process;

[0139] Specifically, in step S2, the time is set to 80 s, the temperature is set to 430 °C, and the pressure is set to 120 mtorr;

[0140] S3: Leak detection: Check the vacuum maintenance;

[0141] S4: ozone is passed through, and ozone oxidizes the polished surface 03 to form an oxidation protection layer 04;

[0142] Specifically, in step S4, the ozone flow rate is 800 sccm and the time is 130 seconds. A 0.5 nm thick ozone silicon oxide layer 05 is oxidized on the surface of the silicon wafer 01;

[0143] S5: nitrogen purge;

[0144] S6: Pre-charge: switch to laughing gas atmosphere;

[0145] S7: Oxide deposition: depositing tunnel oxide layer;

[0146] Specifically, in step S7, the time is set to 120 seconds, the temperature is set to 440°C, the nitrous oxide flow rate is set to 11000 sccm, the RF power is set to 14 kHz, the RF duty cycle is set to 20 ms / 2000 ms, and the pressure is set to 1500 mtorr. A 1.1 nm thick silicon oxide layer 05 is formed, and the 0.5 nm ozone oxide silicon layer 05 in step S4 is superimposed. The resulting tunneling silicon oxide layer 05 is 1.6 nm thick.

[0147] S8: Evacuate: evacuate;

[0148] S9: Pre-filling: switch to silane atmosphere;

[0149] S10: Intrinsic silicon layer deposition: depositing an intrinsic poly silicon layer;

[0150] Specifically, in step S10, the time is set to 90 seconds, the temperature is 430° C., the silane flow rate is 2800 sccm, the hydrogen flow rate is 8000 sccm, the RF power is 12 kHz, the RF duty cycle is 30 ms / 540 ms, and the pressure is 2800 mtorr; the intrinsic silicon thickness is 32 nm;

[0151] S11: Pre-filling: switching silane, phosphine, methane and hydrogen atmospheres;

[0152] S12: In-situ doped polysilicon layer 07 deposition: depositing an in-situ doped carbon-containing phosphorus-doped polysilicon layer;

[0153] Specifically, in step S12, the time is set to 800S, the temperature is 430°C, the silane flow rate is 3100sccm, the 2% phosphine flow rate is 3200sccm, the methane flow rate is 600sccm, the hydrogen flow rate is 9000sccm, the RF power is 15KHz, the RF duty cycle is 30ms / 540ms, and the pressure is 3500mtorr; the thickness of the poly silicon containing carbon in situ doped with phosphorus is 103nm.

[0154] S13: Evacuate: evacuate;

[0155] S14: Mask 08 preparation: generating silicon dioxide mask 08;

[0156] Specifically, the S14 time is 50 seconds, the temperature is 430° C., the silane flow rate is 1500 sccm, the nitrous oxide flow rate is 7000 sccm, the RF power is 10 kHz, the RF duty cycle is 30 ms / 480 ms, and the pressure is 1200 mtorr; the thickness of the silicon dioxide mask 08 is 20 nm;

[0157] S15: Evacuate: evacuate;

[0158] S16: Return to normal pressure: Fill with nitrogen to restore normal pressure;

[0159] S17: Boat out: Open the furnace door, and the silicon nitride slurry pulls the graphite boat out of the quartz tube;

[0160] Example 4

[0161] S1: Inserting the alkali-polished silicon wafer 01 into the graphite boat, sending the graphite boat into the PECVD quartz tube deposition furnace chamber through the silicon nitride slurry, and closing the furnace door;

[0162] S2: Heating and vacuuming: heating to the set temperature, then keeping the temperature constant, and vacuuming simultaneously during the heating process;

[0163] Specifically, in step S2, the time is set to 80 s, the temperature is set to 430 °C, and the pressure is set to 120 mtorr;

[0164] S3: Leak detection: Check the vacuum maintenance;

[0165] S4: ozone is passed through, and ozone oxidation forms an oxidation protection layer 04 on the polished surface 03.

[0166] Specifically, in step S4, the ozone flow rate is 1000 sccm and the time is 145 seconds. A 0.7 nm thick ozone silicon oxide layer 05 is oxidized on the surface of the silicon wafer 01;

[0167] S5: nitrogen purge;

[0168] S6: Pre-charge: switch to laughing gas atmosphere;

[0169] S7: Oxide deposition: depositing tunnel oxide layer;

[0170] Specifically, in step S7, the time is set to 80 seconds, the temperature is set to 450°C, the nitrous oxide flow rate is set to 8000 sccm, the RF power is set to 14 kHz, the RF duty cycle is set to 20 ms / 2000 ms, and the pressure is set to 1500 mtorr. A 0.6 nm thick silicon oxide layer 05 is formed, and the 0.7 nm ozone oxide silicon layer 05 in step S4 is superimposed. The resulting tunneling silicon oxide layer 05 has a thickness of 1.3 nm.

[0171] S8: Evacuate: evacuate;

[0172] S9: Pre-filling: switch to silane atmosphere;

[0173] S10: Intrinsic silicon layer deposition: depositing an intrinsic poly silicon layer;

[0174] Specifically, in step S10, the time is set to 100 seconds, the temperature is 430° C., the silane flow rate is 2800 sccm, the hydrogen flow rate is 10000 sccm, the RF power is 12 kHz, the RF duty cycle is 30 ms / 540 ms, and the pressure is 2900 mtorr; the intrinsic silicon thickness is 40 nm;

[0175] S11: Pre-filling: switching silane, phosphine, methane and hydrogen atmospheres;

[0176] S12: In-situ doped polysilicon layer 07 deposition: depositing an in-situ doped carbon-containing phosphorus-doped polysilicon layer;

[0177] Specifically, in step S12, the time is set to 800S, the temperature is 430°C, the silane flow rate is 3000sccm, the 2% phosphine flow rate is 3000sccm, the methane flow rate is 1000sccm, the hydrogen flow rate is 9000sccm, the RF power is 15KHz, the RF duty cycle is 30ms / 540ms, and the pressure is 3500mtorr; the thickness of the polysilicon containing carbon in situ doped with phosphorus is 115nm.

[0178] S13: Evacuate: evacuate;

[0179] S14: Mask 08 preparation: generating silicon dioxide mask 08;

[0180] Specifically, the S14 time is 50S, the temperature is 430°C, the silane flow rate is 1500sccm, the nitrous oxide flow rate is 7000sccm, the RF power is 10KHz, the RF duty cycle is 30ms / 480ms, and the pressure is 1200mtorr; the thickness of the silicon dioxide mask 08 is 20nm.

[0181] S15: Evacuate: evacuate;

[0182] S16: Return to normal pressure: Fill with nitrogen to restore normal pressure;

[0183] S17: Boat out: Open the furnace door, and the silicon nitride slurry pulls the graphite boat out of the quartz tube;

[0184] Example 5

[0185] S1: Inserting the alkali-polished silicon wafer 01 into the graphite boat, sending the graphite boat into the PECVD quartz tube deposition furnace chamber through the silicon nitride slurry, and closing the furnace door;

[0186] S2: Heating and vacuuming: heating to the set temperature, then keeping the temperature constant, and vacuuming simultaneously during the heating process;

[0187] Specifically, in step S2, the time is set to 80 s, the temperature is set to 430 °C, and the pressure is set to 120 mtorr;

[0188] S3: Leak detection: Check the vacuum maintenance;

[0189] S4: ozone is passed through, and ozone oxidizes the polished surface 03 to form an oxidation protection layer 04;

[0190] Specifically, in step S4, the ozone flow rate is 500 sccm and the time is 100 s. A 0.1 nm thick ozone silicon oxide layer 05 is oxidized on the surface of the silicon wafer 01;

[0191] S5: nitrogen purge;

[0192] S6: Pre-charge: switch to laughing gas atmosphere;

[0193] S7: Oxide deposition: depositing tunnel oxide layer;

[0194] Specifically, in step S7, the time is set to 150s, the temperature is set to 450°C, the nitrous oxide flow rate is set to 12000sccm, the RF power is set to 15KHz, the RF duty cycle is set to 20ms / 2000ms, and the pressure is set to 1500mtorr. A 1.3nm silicon oxide layer 05 is formed, and the 0.2nm ozone silicon oxide layer 05 in step S4 is superimposed. The resulting tunneling silicon oxide layer 05 has a thickness of 1.5nm.

[0195] S8: Evacuate: evacuate;

[0196] S9: Pre-filling: switch to silane atmosphere;

[0197] S10: Intrinsic silicon layer deposition: depositing an intrinsic poly silicon layer;

[0198] Specifically, in step S10, the time is set to 80 seconds, the temperature is 430° C., the silane flow rate is 2800 sccm, the hydrogen flow rate is 8000 sccm, the RF power is 12 kHz, the RF duty cycle is 30 ms / 540 ms, and the pressure is 2700 mtorr; the intrinsic silicon thickness is 30 nm;

[0199] S11: Pre-filling: switching silane, phosphine, methane and hydrogen atmospheres;

[0200] S12: In-situ doped polysilicon layer 07 deposition: depositing an in-situ doped carbon-containing phosphorus-doped polysilicon layer;

[0201] Specifically, in step S12, the time is set to 800S, the temperature is 430°C, the silane flow rate is 3200sccm, the 2% phosphine flow rate is 3200sccm, the methane flow rate is 800sccm, the hydrogen flow rate is 9000sccm, the RF power is 15KHz, the RF duty cycle is 30ms / 540ms, and the pressure is 3500mtorr; the thickness of the poly silicon containing carbon in situ doped with phosphorus is 100nm.

[0202] S13: Evacuate: evacuate;

[0203] S14: Mask 08 preparation: generating silicon dioxide mask 08;

[0204] Specifically, the S14 time is 50S, the temperature is 430°C, the silane flow rate is 1500sccm, the nitrous oxide flow rate is 7000sccm, the RF power is 10KHz, the RF duty cycle is 30ms / 480ms, and the pressure is 1200mtorr; the thickness of the silicon dioxide mask 08 is 20nm.

[0205] S15: Evacuate: evacuate;

[0206] S16: Return to normal pressure: Fill with nitrogen to restore normal pressure;

[0207] S17: Boat out: Open the furnace door, and the silicon nitride slurry pulls the graphite boat out of the quartz tube;

[0208] Example 6

[0209] S1: Inserting the alkali-polished silicon wafer 01 into the graphite boat, sending the graphite boat into the PECVD quartz tube deposition furnace chamber through the silicon nitride slurry, and closing the furnace door;

[0210] S2: Heating and vacuuming: heating to the set temperature, then keeping the temperature constant, and vacuuming simultaneously during the heating process;

[0211] Specifically, in step S2, the time is set to 80 s, the temperature is set to 430 °C, and the pressure is set to 120 mtorr;

[0212] S3: Leak detection: Check the vacuum maintenance;

[0213] S4: ozone is passed through, and ozone oxidizes the polished surface 03 to form an oxidation protection layer 04;

[0214] Specifically, in step S4, the ozone flow rate is 1000 sccm and the time is 180 seconds. A 0.8 nm thick ozone silicon oxide layer 05 is oxidized on the surface of the silicon wafer 01;

[0215] S5: nitrogen purge;

[0216] S6: Pre-charge: switch to laughing gas atmosphere;

[0217] S7: Oxide deposition: depositing tunnel oxide layer;

[0218] Specifically, in step S7, the time is set to 80 seconds, the temperature is set to 450°C, the nitrous oxide flow rate is set to 8000 sccm, the RF power is set to 14 kHz, the RF duty cycle is set to 20 ms / 2000 ms, and the pressure is set to 1500 mtorr. A 0.6 nm thick silicon oxide layer 05 is formed, and the 0.8 nm ozone oxide silicon layer 05 in step S4 is superimposed. The resulting tunneling silicon oxide layer 05 has a thickness of 1.4 nm.

[0219] S8: Evacuate: evacuate;

[0220] S9: Pre-filling: switch to silane atmosphere;

[0221] S10: Intrinsic silicon layer deposition: depositing an intrinsic poly silicon layer;

[0222] Specifically, in step S10, the time is set to 80 seconds, the temperature is 430° C., the silane flow rate is 2800 sccm, the hydrogen flow rate is 8000 sccm, the RF power is 12 kHz, the RF duty cycle is 30 ms / 540 ms, and the pressure is 2700 mtorr; the intrinsic silicon thickness is 30 nm;

[0223] S11: Pre-filling: switching silane, phosphine, methane and hydrogen atmospheres;

[0224] S12: In-situ doped polysilicon layer 07 deposition: depositing an in-situ doped carbon-containing phosphorus-doped polysilicon layer;

[0225] Specifically, in step S12, the time is set to 800S, the temperature is 430°C, the silane flow rate is 3200sccm, the 2% phosphine flow rate is 3200sccm, the methane flow rate is 800sccm, the hydrogen flow rate is 9000sccm, the RF power is 15KHz, the RF duty cycle is 30ms / 540ms, and the pressure is 3500mtorr; the thickness of the poly silicon containing carbon in situ doped with phosphorus is 100nm.

[0226] S13: Evacuate: evacuate;

[0227] S14: Mask 08 preparation: generating silicon dioxide mask 08;

[0228] Specifically, the S14 time is 50S, the temperature is 430°C, the silane flow rate is 1500sccm, the nitrous oxide flow rate is 7000sccm, the RF power is 10KHz, the RF duty cycle is 30ms / 480ms, and the pressure is 1200mtorr; the thickness of the silicon dioxide mask 08 is 20nm.

[0229] S15: Evacuate: evacuate;

[0230] S16: Return to normal pressure: Fill with nitrogen to restore normal pressure;

[0231] S17: Boat out: Open the furnace door, and the silicon nitride slurry pulls the graphite boat out of the quartz tube;

[0232] Example 7

[0233] S1: Inserting the alkali-polished silicon wafer 01 into the graphite boat, sending the graphite boat into the PECVD quartz tube deposition furnace chamber through the silicon nitride slurry, and closing the furnace door;

[0234] S2: Heating and vacuuming: heating to the set temperature, then keeping the temperature constant, and vacuuming simultaneously during the heating process;

[0235] Specifically, in step S2, the time is set to 80 s, the temperature is set to 430 °C, and the pressure is set to 120 mtorr;

[0236] S3: Leak detection: Check the vacuum maintenance;

[0237] S4: ozone is passed through, and ozone oxidizes the polished surface 03 to form an oxidation protection layer 04;

[0238] Specifically, in step S4, the ozone flow rate is 1000 sccm and the time is 145 seconds. A 0.7 nm thick ozone silicon oxide layer 05 is oxidized on the surface of the silicon wafer 01;

[0239] S5: nitrogen purge;

[0240] S6: Pre-charge: switch to laughing gas atmosphere;

[0241] S7: Oxide deposition: depositing tunnel oxide layer;

[0242] Specifically, in step S7, the time is set to 80 seconds, the temperature is set to 450°C, the nitrous oxide flow rate is set to 8000 sccm, the RF power is set to 14 kHz, the RF duty cycle is set to 20 ms / 2000 ms, and the pressure is set to 1500 mtorr. A 0.6 nm thick silicon oxide layer 05 is formed, and the 0.7 nm ozone oxide silicon layer 05 in step S4 is superimposed. The resulting tunneling silicon oxide layer 05 has a thickness of 1.3 nm.

[0243] S8: Evacuate: evacuate;

[0244] S9: Pre-filling: switch to silane atmosphere;

[0245] S10: Intrinsic silicon layer deposition: depositing an intrinsic poly silicon layer;

[0246] Specifically, in step S10, the time is set to 100 seconds, the temperature is 430° C., the silane flow rate is 2800 sccm, the hydrogen flow rate is 10000 sccm, the RF power is 12 kHz, the RF duty cycle is 30 ms / 540 ms, and the pressure is 2900 mtorr; the intrinsic silicon thickness is 40 nm;

[0247] S11: Pre-filling: switching silane, phosphine, methane and hydrogen atmospheres;

[0248] S12: In-situ doped polysilicon layer 07 deposition: depositing an in-situ phosphorus doped polysilicon layer;

[0249] Specifically, in step S12, the time is set to 800S, the temperature is 430°C, the silane flow rate is 3000sccm, the 2% phosphine flow rate is 3000sccm, the hydrogen flow rate is 9000sccm, the RF power is 15KHz, the RF duty cycle is 30ms / 540ms, and the pressure is 3500mtorr; the thickness of the in-situ phosphorus-doped polysilicon is 115nm.

[0250] S13: Evacuate: evacuate;

[0251] S14: Mask 08 preparation: generating silicon dioxide mask 08;

[0252] Specifically, the S14 time is 50S, the temperature is 430°C, the silane flow rate is 1500sccm, the nitrous oxide flow rate is 7000sccm, the RF power is 10KHz, the RF duty cycle is 30ms / 480ms, and the pressure is 1200mtorr; the thickness of the silicon dioxide mask 08 is 20nm.

[0253] S15: Evacuate: evacuate;

[0254] S16: Return to normal pressure: Fill with nitrogen to restore normal pressure;

[0255] S17: Boat out: Open the furnace door, and the silicon nitride slurry pulls the graphite boat out of the quartz tube;

[0256] Example 8

[0257] S1: Inserting the alkali-polished silicon wafer 01 into the graphite boat, sending the graphite boat into the PECVD quartz tube deposition furnace chamber through the silicon nitride slurry, and closing the furnace door;

[0258] S2: Heating and vacuuming: heating to the set temperature, then keeping the temperature constant, and vacuuming simultaneously during the heating process;

[0259] Specifically, in step S2, the time is set to 80 s, the temperature is set to 430 °C, and the pressure is set to 120 mtorr;

[0260] S3: Leak detection: Check the vacuum maintenance;

[0261] S4: ozone is passed through, and ozone oxidizes the polished surface 03 to form an oxidation protection layer 04;

[0262] Specifically, in step S4, the ozone flow rate is 1000 sccm and the time is 145 seconds. A 0.7 nm thick ozone silicon oxide layer 05 is oxidized on the surface of the silicon wafer 01;

[0263] S5: nitrogen purge;

[0264] S6: Pre-charge: switch to laughing gas atmosphere;

[0265] S7: Oxide deposition: depositing tunnel oxide layer;

[0266] Specifically, in step S7, the time is set to 80 seconds, the temperature is set to 450°C, the nitrous oxide flow rate is set to 8000 sccm, the RF power is set to 14 kHz, the RF duty cycle is set to 20 ms / 2000 ms, and the pressure is set to 1500 mtorr. A 0.6 nm thick silicon oxide layer 05 is formed, and the 0.7 nm ozone oxide silicon layer 05 in step S4 is superimposed. The resulting tunneling silicon oxide layer 05 has a thickness of 1.3 nm.

[0267] S8: Evacuate: evacuate;

[0268] S9: Pre-filling: switch to silane atmosphere;

[0269] S10: Intrinsic silicon layer deposition: depositing an intrinsic poly silicon layer;

[0270] Specifically, in step S10, the time is set to 100 seconds, the temperature is 430° C., the silane flow rate is 2800 sccm, the hydrogen flow rate is 10000 sccm, the RF power is 12 kHz, the RF duty cycle is 30 ms / 540 ms, and the pressure is 2900 mtorr; the intrinsic silicon thickness is 40 nm;

[0271] S11: Pre-filling: switching silane, phosphine, methane and hydrogen atmospheres;

[0272] S12: In-situ doped polysilicon layer 07 deposition: depositing an in-situ doped carbon-containing phosphorus-doped polysilicon layer;

[0273] Specifically, in step S12, the time is set to 800S, the temperature is 430°C, the silane flow rate is 3000sccm, the 2% phosphine flow rate is 3000sccm, the methane flow rate is 100sccm, the hydrogen flow rate is 9000sccm, the RF power is 15KHz, the RF duty cycle is 30ms / 540ms, and the pressure is 3500mtorr; the thickness of the poly silicon containing carbon in situ doped with phosphorus is 115nm.

[0274] S13: Evacuate: evacuate;

[0275] S14: Mask 08 preparation: generating silicon dioxide mask 08;

[0276] Specifically, the S14 time is 50S, the temperature is 430°C, the silane flow rate is 1500sccm, the nitrous oxide flow rate is 7000sccm, the RF power is 10KHz, the RF duty cycle is 30ms / 480ms, and the pressure is 1200mtorr; the thickness of the silicon dioxide mask 08 is 20nm.

[0277] S15: Evacuate: evacuate;

[0278] S16: Return to normal pressure: Fill with nitrogen to restore normal pressure;

[0279] S17: Boat out: Open the furnace door, and the silicon nitride slurry pulls the graphite boat out of the quartz tube;

[0280] Example 9

[0281] S1: Inserting the alkali-polished silicon wafer 01 into the graphite boat, sending the graphite boat into the PECVD quartz tube deposition furnace chamber through the silicon nitride slurry, and closing the furnace door;

[0282] S2: Heating and vacuuming: heating to the set temperature, then keeping the temperature constant, and vacuuming simultaneously during the heating process;

[0283] Specifically, in step S2, the time is set to 80 s, the temperature is set to 430 °C, and the pressure is set to 120 mtorr;

[0284] S3: Leak detection: Check the vacuum maintenance;

[0285] S4: ozone is passed through, and ozone oxidizes the polished surface 03 to form an oxidation protection layer 04;

[0286] Specifically, in step S4, the ozone flow rate is 1000 sccm and the time is 145 seconds. A 0.7 nm thick ozone silicon oxide layer 05 is oxidized on the surface of the silicon wafer 01;

[0287] S5: nitrogen purge;

[0288] S6: Pre-charge: switch to laughing gas atmosphere;

[0289] S7: Oxide deposition: depositing tunnel oxide layer;

[0290] Specifically, in step S7, the time is set to 80 seconds, the temperature is set to 450°C, the nitrous oxide flow rate is set to 8000 sccm, the RF power is set to 14 kHz, the RF duty cycle is set to 20 ms / 2000 ms, and the pressure is set to 1500 mtorr. A 0.6 nm thick silicon oxide layer 05 is formed, and the 0.7 nm ozone oxide silicon layer 05 in step S4 is superimposed. The resulting tunneling silicon oxide layer 05 has a thickness of 1.3 nm.

[0291] S8: Evacuate: evacuate;

[0292] S9: Pre-filling: switch to silane atmosphere;

[0293] S10: Intrinsic silicon layer deposition: depositing an intrinsic poly silicon layer;

[0294] Specifically, in step S10, the time is set to 100 seconds, the temperature is 430° C., the silane flow rate is 2800 sccm, the hydrogen flow rate is 10000 sccm, the RF power is 12 kHz, the RF duty cycle is 30 ms / 540 ms, and the pressure is 2900 mtorr; the intrinsic silicon thickness is 40 nm;

[0295] S11: Pre-filling: switching silane, phosphine, methane and hydrogen atmospheres;

[0296] S12: In-situ doped polysilicon layer 07 deposition: depositing an in-situ doped carbon-containing phosphorus-doped polysilicon layer;

[0297] Specifically, in step S12, the time is set to 800S, the temperature is 430°C, the silane flow rate is 3000sccm, the 2% phosphine flow rate is 3000sccm, the methane flow rate is 1100sccm, the hydrogen flow rate is 9000sccm, the RF power is 15KHz, the RF duty cycle is 30ms / 540ms, and the pressure is 3500mtorr; the thickness of the poly silicon containing carbon in situ doped with phosphorus is 115nm.

[0298] S13: Evacuate: evacuate;

[0299] S14: Mask 08 preparation: generating silicon dioxide mask 08;

[0300] Specifically, the S14 time is 50S, the temperature is 430°C, the silane flow rate is 1500sccm, the nitrous oxide flow rate is 7000sccm, the RF power is 10KHz, the RF duty cycle is 30ms / 480ms, and the pressure is 1200mtorr; the thickness of the silicon dioxide mask 08 is 20nm.

[0301] S15: Evacuate: evacuate;

[0302] S16: Return to normal pressure: Fill with nitrogen to restore normal pressure;

[0303] S17: Boat out: Open the furnace door, and the silicon nitride slurry pulls the graphite boat out of the quartz tube;

[0304] Comparison group 1

[0305] The difference from Example 1 is that the step of generating the oxidation protection layer 04 on the surface of the silicon wafer 01 by passing ozone is omitted, and the in-situ doped polysilicon layer 07 does not contain carbon.

[0306] Comparison group 2

[0307] The difference from Example 2 is that the step of generating the oxidation protection layer 04 on the surface of the silicon wafer 01 by passing ozone is omitted, and the in-situ doped polysilicon layer 07 does not contain carbon.

[0308] Comparison group 3

[0309] The difference from Example 3 is that the step of generating the oxidation protection layer 04 on the surface of the silicon wafer 01 by passing ozone is omitted, and the in-situ doped polysilicon layer 07 does not contain carbon.

[0310] Comparison group 4

[0311] The difference from Example 4 is that the step of generating the oxidation protection layer 04 on the surface of the silicon wafer 01 by passing ozone is omitted, and the in-situ doped polysilicon layer 07 does not contain carbon.

[0312] Comparison group 5

[0313] The difference from Example 5 is that the step of generating the oxidation protection layer 04 on the surface of the silicon wafer 01 by passing ozone is omitted, and the in-situ doped polysilicon layer 07 does not contain carbon.

[0314] Comparison group 6

[0315] The difference from Example 6 is that the step of generating the oxidation protection layer 04 on the surface of the silicon wafer 01 by passing ozone is omitted, and the in-situ doped polysilicon layer 07 does not contain carbon.

[0316] Comparison group 7

[0317] The difference from Example 7 is that the step of generating the oxidation protection layer 04 on the surface of the silicon wafer 01 by passing ozone is omitted, and the in-situ doped polysilicon layer 07 does not contain carbon.

[0318] Comparison group 8

[0319] The difference from Example 8 is that the step of generating the oxidation protection layer 04 on the surface of the silicon wafer 01 by passing ozone is omitted, and the in-situ doped polysilicon layer 07 does not contain carbon.

[0320] Comparison group 9

[0321] The difference from Example 9 is that the step of generating the oxidation protection layer 04 on the surface of the silicon wafer 01 by passing ozone is omitted, and the in-situ doped polysilicon layer 07 does not contain carbon.

[0322] The TOPCcon cells of Examples 1-9 and Comparative Groups 1-9 were processed and manufactured into finished products for performance testing. The results of Eta (conversion efficiency), Voc (open circuit voltage), Isc (short circuit current), and FF (fill factor) are shown in Tables 1-9 below:

[0323] Table 1, Performance comparison between Example 1 and Comparative Group 1

[0324] Eta Voc Isc FF Comparison group 1 25.899 0.7385 13.8015 85.050 Example 1 26.048 0.7395 13.8427 85.170 difference 0.149 0.0010 0.0412 0.120

[0325] According to Table 1, the overall efficiency of the battery in Example 1 is improved by 0.149% compared with that in Comparative Group 1.

[0326] Table 2, Performance comparison of Example 2 and Comparative Group 2

[0327]

[0328]

[0329] According to Table 2, the overall efficiency of the battery in Example 2 is improved by 0.201% compared with that in Comparative Group 2.

[0330] Table 3, Performance comparison of Example 3 and Comparative Group 3

[0331] Eta Voc Isc FF Comparison group 3 26.030 0.7385 13.8527 85.165 Example 3 26.282 0.7410 13.9229 85.265 difference 0.251 0.0025 0.0702 0.100

[0332] According to Table 3, the overall efficiency of the battery in Example 3 is improved by 0.251% compared with that in Comparative Group 3.

[0333] Table 4, Performance comparison of Example 4 and Comparative Group 4

[0334] Eta Voc Isc FF Comparison group 4 25.876 0.7384 13.7992 85.000 Example 4 26.064 0.7398 13.8519 85.130 difference 0.188 0.0014 0.0527 0.130

[0335] According to Table 4, the overall efficiency of the battery in Example 4 is improved by 0.188% compared with that in Comparative Group 4.

[0336] Table 5, Performance comparison of Example 5 and Comparative Group 5

[0337]

[0338]

[0339] According to Table 5, the overall efficiency of the battery in Example 5 is improved by 0.108% compared with that in Comparative Group 5.

[0340] Table 6, Performance comparison of Example 6 and Comparative Group 6

[0341] Eta Voc Isc FF Comparison group 6 25.971 0.7397 13.8037 85.134 Example 6 26.110 0.7401 13.8597 85.197 difference 0.139 0.0004 0.0560 0.063

[0342] According to Table 6, the overall efficiency of the battery in Example 6 is improved by 0.139% compared with that in Comparative Group 6.

[0343] Table 7, Performance comparison of Example 7 and Comparative Group 7

[0344] Eta Voc Isc FF Comparison group 7 25.938 0.7403 13.7995 84.982 Example 7 26.000 0.7418 13.7998 85.013 difference 0.063 0.0015 0.0003 0.031

[0345] According to Table 7, the overall efficiency of the battery in Example 7 is improved by 0.063% compared with that in Comparative Group 7.

[0346] Table 8, Performance comparison of Example 8 and Comparative Group 8

[0347]

[0348]

[0349] According to Table 8, the overall efficiency of the battery in Example 8 is improved by 0.106% compared with that in Comparative Group 8.

[0350] Table 9, Performance comparison of Example 9 and Comparative Group 9

[0351] Eta Voc Isc FF Comparison group 9 26.115 0.7391 13.8617 85.317 Example 9 26.204 0.7401 13.9214 85.125 difference 0.089 0.0010 0.0597 -0.192

[0352] According to Table 9, the overall efficiency of the battery in Example 9 is improved by 0.089% compared with that in Comparative Group 9.

[0353] In summary, the present application has at least the following advantages over the prior art:

[0354] 1. Ozone generates an oxidation protection layer 04, which can reduce the damage to the surface of the silicon wafer 01 caused by plasma during the process of generating the silicon oxide layer 05 by the laughing gas plasma, resulting in plasma bombardment damage. However, if only ozone oxidation is used, the generated oxide layer is loose and porous, and cannot form effective passivation. Therefore, the tunneling oxide layer generated by ozone oxidation and laughing gas ionization has good density, which can not only form a good field passivation effect on the surface of the silicon substrate, but also reduce the damage to the surface of the silicon wafer 01 caused by plasma bombardment and reduce surface recombination.

[0355] 2. The intrinsic polysilicon layer 06 can support the internal diffusion of phosphorus atoms in the in-situ doped polysilicon layer 07 during the high-temperature annealing process, acting as a buffer, thereby reducing the number of phosphorus atoms that enter the silicon substrate through the tunneling oxide layer and reducing silicon substrate recombination. At the same time, through the annealing process, the phosphorus atoms in the in-situ doped polysilicon layer 07 will also enter the intrinsic polysilicon layer 06 for doping, providing field passivation and doping.

[0356] 3. The refractive index and extinction coefficient of in-situ doped silicon containing carbon and phosphorus are lower than those of conventional phosphorus-doped polysilicon, which can reduce parasitic absorption of long waves.

[0357] 4. Both carbon and silicon have 4 electrons in their outer layers and are elements of the same main group. Carbon doped polysilicon can substitute to form covalent bonds, which has a stable structure and does not affect the crystal structure of polysilicon.

[0358] 5. Carbon atoms can capture hydrogen atoms, adjust the work function of the material, and affect the diffusion and activation of phosphorus atoms, thereby improving the passivation quality, reducing surface recombination, and thus increasing the implicit turn-on voltage and reducing the recombination current.

[0359] 6. The composite current density J0 of the polysilicon passivation layer on the back of the TOPCon high-efficiency cell can be reduced from 3-5fA to 1-1.5fA, the implicit open circuit voltage iVoc is increased by 2-3mV, the reflectivity of the test cell to long-wave light is increased from 40-45% to 60%-70%, and the short-circuit current density Jsc is increased by 0.1mA / cm

[0360] -0.2mA / cm 2 , which can improve battery efficiency by more than 0.15%.

[0361] The above are merely specific embodiments of the present application and are not intended to limit the present application. Those skilled in the art will readily appreciate that various modifications and variations are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A method for manufacturing a passivation layer, characterized in that: The steps include: Ozone is introduced to oxidize the polished surface of the silicon wafer to form an oxide protective layer; depositing a silicon oxide layer on the oxide protection layer; depositing an intrinsic polysilicon layer on the silicon oxide layer; depositing an in-situ doped polysilicon layer on the intrinsic polysilicon layer; A mask is deposited on the in-situ doped polysilicon layer.

2. The method for manufacturing a passivation layer according to claim 1, wherein: In the step of introducing ozone to oxidize the polished surface of the silicon wafer to form an oxide protective layer, the flow rate of the ozone is 500 sccm-1000 sccm, and the time is 100S-200S.

3. The method for manufacturing a passivation layer according to claim 1, wherein: In the step of depositing the silicon oxide layer on the oxidation protection layer, feeding laughing gas atmosphere to deposit the silicon oxide layer; Set the time for introducing nitrous oxide to 50S-150S, the temperature to 430℃-450℃, the nitrous oxide flow rate to 8000sccm-12000sccm, the RF power to 11KHz-15KHz, the RF duty cycle to 20ms / 2000ms, and the pressure to 1000mtorr-1500mtorr.

4. The method for manufacturing a passivation layer according to claim 1, wherein: In the step of depositing an intrinsic polysilicon layer on the silicon oxide layer, a silane atmosphere is introduced to deposit the intrinsic polysilicon layer, and the time for introducing the silane atmosphere is set to 80S-100S, the temperature is 430℃-450℃, the silane flow rate is 2500sccm-3200sccm, the hydrogen flow rate is 8000sccm-10000sccm, the RF power is 11KHz-15KHz, the RF duty cycle is 30ms / 540ms, and the pressure is 2500mtorr-3000mtorr.

5. The method for manufacturing a passivation layer according to claim 1, wherein: In the step of depositing an in-situ doped polysilicon layer on the intrinsic polysilicon layer, a phosphorus-doped polysilicon layer containing carbon is in-situ doped is deposited.

6. The method for manufacturing a passivation layer according to claim 5, wherein: Passing silane, phosphine, methane and hydrogen atmosphere to deposit an in-situ doped carbon-containing phosphorus-doped polysilicon layer; Set the time for introducing the atmosphere to 600S-800S, the temperature to 430℃-450℃, the silane flow rate to 2500sccm-3200sccm, the 2% phosphine flow rate to 2800sccm-3200sccm, the methane flow rate to 200sccm-1000sccm, the hydrogen flow rate to 6000sccm-9000sccm, the RF power to 11KHz-15KHz, the RF duty cycle to 30ms / 540ms, and the pressure to 3300mtorr-3700mtorr.

7. The method for manufacturing a passivation layer according to claim 1, wherein: In the step of depositing a mask on the in-situ doped polysilicon layer, laughing gas is introduced to deposit a silicon dioxide mask; Set the time to 30S-100S, the temperature to 430℃-450℃, the silane flow rate to 1000sccm-2000sccm, the nitrous oxide flow rate to 6000sccm-8000sccm, the RF power to 10KHz-12KHz, the RF duty cycle to 30ms / 480ms, and the pressure to 1200mtorr-1500mtorr.

8. A TOPCon battery manufacturing method, characterized in that: The steps include: Pre-treatment process: The silicon wafer is cleaned and textured, boron is diffused to prepare PN junction, BSG is removed from the back and edge, and the back is alkaline polished; A polysilicon passivation layer manufacturing process: a passivation layer is manufactured on the back side of the silicon wafer using the passivation layer manufacturing method according to any one of claims 1 to 7; Post-processing steps: annealing, PSG removal, RCA cleaning, front ALD to generate aluminum oxide film, front PECVD to coat SiNx film, back PECVD to coat SiNx film, metallization printing on the front and back of silicon wafers, pre-sintering and light injection treatment of silicon wafers, and laser sintering of silicon wafers.

9. A TOPCon battery, characterized in that: The TOPCon cell is manufactured using the TOPCon cell manufacturing method according to claim 8, comprising a silicon wafer and a passivation layer located on the back of the silicon wafer, wherein the passivation layer comprises an oxidation protection layer, a silicon oxide layer, an intrinsic polysilicon layer, an in-situ doped polysilicon layer and a mask stacked in sequence.

10. The TOPCon battery according to claim 9, characterized in that The thickness of the oxidation protection layer is 0.2-0.7 nm; The thickness of the silicon oxide layer is 1.0 nm to 1.3 nm; The thickness of the intrinsic polysilicon layer is 20nm-40nm; The thickness of the in-situ doped polysilicon layer is 70nm-110nm; The thickness of the mask is 10nm-30nm.

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