Test board life monitoring device and method
By automatically monitoring the cumulative loss value and loss threshold of vulnerable devices on the test board, the problem that ATE test board life monitoring relies on manual inspection is solved, and efficient and accurate life monitoring is achieved, ensuring the reliability of chip testing.
Patent Information
- Application Number
- CN202510848460.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-23
- Publication Date
- 2025-09-02
AI Technical Summary
In the prior art, the life monitoring of ATE test boards depends on manual inspection, which is inefficient and there is a possibility of missed inspection by subjective factors, resulting in test failure.
A test board life monitoring device and method is provided, including a data storage module, a data processing module and a monitoring module. By automatically monitoring the cumulative loss value and loss threshold of vulnerable devices on the test board, real-time monitoring of the life of the test board, and alarm information is issued under preset conditions.
It realizes automated monitoring of the life of ATE test boards, improves the efficiency and accuracy of life monitoring, ensures the reliability of chip testing, and promptly detects and repairs aging and faulty test boards.
Smart Images
Figure CN120577673A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present application relate to the field of automated testing equipment, and in particular to a device and method for monitoring the life of a test board. Background Art
[0002] With the advancement of semiconductor technology, the integration and complexity of chips are increasing, and the requirements for chip testing are also gradually increasing. Automatic test equipment (ATE) can be used to verify the functions and performance of chips and is widely used in chip mass production testing. As a core component of ATE, the service life and performance stability of ATE test boards are crucial.
[0003] Currently, life monitoring of ATE test boards relies on manual inspection.
[0004] However, manual inspection is not only inefficient, but also has the possibility of missed inspections due to subjective factors, leading to ATE test failures. Summary of the Invention
[0005] In view of this, embodiments of the present application provide a test board life monitoring device and method to at least partially solve the above-mentioned problems.
[0006] According to a first aspect of an embodiment of the present application, a test board life monitoring device is provided, which includes: a data storage module, a data processing module and a monitoring module; the data storage module is used to store the cumulative loss value and loss threshold of each of the at least one vulnerable device included in the test board, wherein the test board is used for chip testing, the cumulative loss value is used to indicate the loss already incurred by the vulnerable device, and the loss threshold is used to indicate the maximum loss that the vulnerable device can withstand; the data processing module is used to obtain the loss value increment of the vulnerable device, and update the cumulative loss value of the vulnerable device in the data storage module by the sum of the loss value increment and the cumulative loss value of the vulnerable device, wherein the loss value increment is used to indicate the loss incurred by the vulnerable device after completing a chip test; the monitoring module is used to monitor the life of the test board according to the cumulative loss value and the loss threshold of the at least one vulnerable device in the data storage module, and to issue an alarm message when the life monitoring result meets a preset condition.
[0007] In one possible implementation, the device further includes: a data acquisition module; the data acquisition module is used to obtain the loss parameters of the fragile device after completing a chip test; and the data processing module is used to determine the loss value increment of the fragile device based on the loss parameters.
[0008] In one possible implementation, the data storage module is arranged on the test board, and the data storage module is electrically connected to the chip testing equipment; the data storage module is used to store the identification code of the test board, and associate the identification code of the test board with the cumulative loss value and loss threshold of each of the vulnerable components in the test board.
[0009] In one possible implementation, the device also includes: a display module; the monitoring module is used to obtain the identification code of the test board, and according to the identification code of the test board, obtain the cumulative loss value, the loss value increment and the loss threshold of each of the vulnerable devices in at least one vulnerable device included in the test board; the display module is used to display the identification code of the test board, and the cumulative loss value, the loss value increment and the loss threshold of each of the vulnerable devices in the test board associated with the identification code of the test board through a user prompt information interface.
[0010] In one possible implementation, the monitoring module is used to send an alarm message to the display module for display when the cumulative loss value of at least one of the vulnerable components is greater than or equal to the loss threshold, and / or when the sum of the cumulative loss value of at least one of the vulnerable components and the loss value increment is greater than or equal to the loss threshold.
[0011] According to a second aspect of an embodiment of the present application, a test board life monitoring method is provided, which includes: obtaining a cumulative loss value and a loss threshold of each vulnerable device in at least one vulnerable device included in the test board, wherein the test board is used for chip testing, the cumulative loss value is used to indicate the loss already incurred by the vulnerable device, and the loss threshold is used to indicate the maximum loss that the vulnerable device can withstand; obtaining a loss value increment of the vulnerable device, and updating the cumulative loss value of the vulnerable device by the sum of the loss value increment and the cumulative loss value of the vulnerable device, wherein the loss value increment is used to indicate the loss incurred by the vulnerable device after completing a chip test; performing life monitoring on the test board based on the cumulative loss value and the loss threshold of the at least one vulnerable device, and issuing an alarm message when the life monitoring result meets a preset condition.
[0012] In a possible implementation, obtaining the incremental loss value of the fragile device includes: obtaining a loss parameter of the fragile device after completing a chip test; and determining the incremental loss value of the fragile device according to the loss parameter.
[0013] In one possible implementation, obtaining the cumulative loss value and loss threshold of each of the at least one vulnerable device included in the test board includes: obtaining an identification code of the test board; and determining the cumulative loss value and loss threshold of each of the vulnerable devices in the test board based on the identification code of the test board.
[0014] In one possible implementation, the method further includes: displaying the identification code of the test board, and the cumulative loss value, the loss value increment, and the loss threshold of each of the vulnerable components in the test board associated with the identification code of the test board through a user prompt information interface.
[0015] In one possible implementation, the life of the test board is monitored based on the cumulative loss value and the loss threshold of at least one of the vulnerable components, and an alarm message is issued when the life monitoring result meets a preset condition, including: outputting an alarm message if the cumulative loss value of at least one of the vulnerable components is greater than or equal to the loss threshold, and / or the sum of the cumulative loss value of at least one of the vulnerable components and the loss value increment is greater than or equal to the loss threshold; and displaying the alarm message through the user prompt information interface.
[0016] According to an embodiment of the present application, a test board life monitoring device is provided, comprising: a data storage module, a data processing module, and a monitoring module. The data storage module can store the cumulative loss value and loss threshold of each vulnerable component of at least one vulnerable component included in the test board, wherein the test board is used for chip testing, the cumulative loss value indicates the loss incurred by the vulnerable component, and the loss threshold indicates the maximum loss that the vulnerable component can withstand. The data processing module can obtain the incremental loss value of the vulnerable component and update the cumulative loss value of the vulnerable component in the data storage module using the sum of the incremental loss value and the cumulative loss value of the vulnerable component, wherein the incremental loss value indicates the loss incurred by the vulnerable component after completing a chip test. The monitoring module can monitor the life of the test board based on the cumulative loss value and the loss threshold of the at least one vulnerable component in the data storage module, and issue an alarm when the life monitoring result meets preset conditions. This enables real-time monitoring of the service life of the test board during chip mass production testing, allowing testers to promptly identify and repair test boards that have aged due to long-term testing, thereby ensuring the reliability of chip testing. Compared with the existing technology, the test board life monitoring device provided by this solution realizes the automatic monitoring of the life of the ATE test board, which can improve the efficiency and accuracy of the test board life monitoring, thereby ensuring the reliability of ATE chip testing. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.
[0018] Figure 1 is a schematic diagram of a test board life monitoring device provided in an embodiment of the present application;
[0019] Figure 2 is a schematic diagram of another test board life monitoring device provided in an embodiment of the present application;
[0020] Figure 3 This is a schematic diagram of the working principle of a data acquisition module provided in an embodiment of the present application;
[0021] Figure 4 This is a schematic diagram of the working principle of a data processing module provided in an embodiment of the present application;
[0022] Figure 5 is a schematic diagram of a data storage module provided in an embodiment of the present application;
[0023] Figure 6 is a schematic diagram of another test board life monitoring device provided in an embodiment of the present application;
[0024] Figure 7 This is a schematic diagram of the working principle of a display module provided in an embodiment of the present application;
[0025] Figure 8 This is a flow chart of a test board life monitoring method provided in an embodiment of the present application. DETAILED DESCRIPTION
[0026] In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and in detail described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the embodiments of the present application, all other embodiments obtained by ordinary technicians in this field should fall within the scope of protection of the embodiments of the present application.
[0027] As mentioned above, with the advancement of semiconductor technology, the integration and complexity of chips are increasing, and the requirements for chip testing are also gradually increasing. Automatic test equipment (ATE) can be used to detect the functions and performance of chips and is widely used in chip mass production testing. As a core component of ATE, the operating life and performance stability of ATE test boards are crucial. Currently, the life monitoring of ATE test boards relies on manual inspection. However, manual inspection is not only inefficient, but also has the potential for missed detections due to subjective factors, leading to ATE test failures.
[0028] In one embodiment of the present application, a test board life monitoring device is provided. The device comprises a data storage module, a data processing module, and a monitoring module. The data storage module can store the cumulative loss value and loss threshold of each vulnerable component of the test board, wherein the test board is used for chip testing, the cumulative loss value indicates the loss incurred by the vulnerable component, and the loss threshold indicates the maximum loss the vulnerable component can withstand. The data processing module can obtain the incremental loss value of the vulnerable component and update the cumulative loss value of the vulnerable component in the data storage module using the sum of the incremental loss value and the cumulative loss value of the vulnerable component, wherein the incremental loss value indicates the loss incurred by the vulnerable component after completing a chip test. The monitoring module can monitor the life of the test board based on the cumulative loss value and the loss threshold of the at least one vulnerable component in the data storage module, and issue an alarm when the life monitoring result meets preset conditions. This enables real-time monitoring of the service life of the test board during chip mass production testing, allowing testers to promptly identify and repair test boards that have aged due to long-term testing, thereby ensuring the reliability of chip testing. Compared with the existing technology, the test board life monitoring device provided by this solution realizes the automatic monitoring of the life of the ATE test board, which can improve the efficiency and accuracy of the test board life monitoring, thereby ensuring the reliability of ATE chip testing.
[0029] The test board life monitoring device provided by this application is described below through examples.
[0030] Figure 1 Schematic diagram of a test board life monitoring device provided in an embodiment of the present application. Figure 1As shown, the test board life monitoring device 100 includes: a data storage module 101, a data processing module 102, and a monitoring module 103. The data storage module 101 can store the cumulative loss value and loss threshold of each vulnerable device in at least one vulnerable device included in the test board, wherein the test board is used for chip testing, the cumulative loss value is used to indicate the loss that has occurred in the vulnerable device, and the loss threshold is used to indicate the maximum loss that the vulnerable device can withstand. The data processing module 102 can obtain the loss value increment of the vulnerable device and update the cumulative loss value of the vulnerable device in the data storage module 101 by summing the loss value increment and the cumulative loss value of the vulnerable device, wherein the loss value increment is used to indicate the loss incurred by the vulnerable device after completing a chip test. The monitoring module 103 can monitor the life of the test board based on the cumulative loss value and loss threshold of at least one vulnerable device in the data storage module 101, and issue an alarm message when the life monitoring result meets the preset conditions.
[0031] A test board is a circuit board that connects the device under test (DUT) to the test equipment (such as ATE) during the mass production test of chips. Fragile components on the test board are components that are easily damaged due to physical properties, electrical properties, or operating environment, such as relays, sockets (test sockets), and LED indicators. It is understandable that since the test board needs to support frequent operations, signal switching, or circuit protection requirements to achieve chip performance and function testing, the test board usually contains at least one fragile component (such as a relay or socket).
[0032] The data storage module 101 can store the cumulative loss value and loss threshold of each vulnerable device in at least one vulnerable device included in the test board. The cumulative loss value of a vulnerable device refers to a loss value quantified based on reference factors such as the number of uses, time and / or current load of the vulnerable device, which is used to indicate the loss that has occurred in the vulnerable device. The loss threshold is a critical value determined by device specifications, experimental data or reliability models, which is used to indicate the maximum loss that a vulnerable device can withstand before failure. A vulnerable device can have cumulative loss values and loss thresholds in multiple dimensions. In one example, the data storage module 101 records the number of times relay 1 in the test board has been operated, that is, the cumulative loss value is 10 times, and the maximum number of switching times, that is, the loss threshold is 10. 8 The path damage value, i.e., the cumulative loss value, of path 1 of relay 1 is 0.2, and the maximum path damage value, i.e., the loss threshold, is 1.
[0033] The data processing module 102 can obtain the incremental loss value of the vulnerable device. The incremental loss value of the vulnerable device refers to the quantified loss value generated by the vulnerable device after completing a chip test. In chip mass production testing, each chip can have multiple test items. A chip test is considered to be completed when a chip completes all the test items to be tested. In one example, the DC-DC chip mass production test has four test items: static current test, conversion efficiency test, voltage accuracy test, and frequency test. After completing a chip test, the data processing module 102 reads the cumulative loss value of each vulnerable device stored in the data storage module 101, and adds the cumulative loss value of each vulnerable device read to the corresponding incremental loss value, transmits the new added value to the data storage module 101, and replaces the cumulative loss value of each vulnerable device in the data storage module 101, so as to update the loss value generated by the vulnerable devices on the test board after each chip test in real time.
[0034] The monitoring module 103 can monitor the life of the test board based on the cumulative loss value and loss threshold of at least one vulnerable component in the data storage module 101, and when the life monitoring result meets the preset conditions, it issues an alarm message to remind the test personnel to repair the failed vulnerable components on the test board.
[0035] In an embodiment of the present application, a test board life monitoring device 100 includes a data storage module 101, a data processing module 102, and a monitoring module 103. The data storage module 101 can store the cumulative wear value and wear threshold of each vulnerable component of at least one vulnerable component included in the test board. The test board is used for chip testing, where the cumulative wear value indicates the wear incurred by the vulnerable component, and the wear threshold indicates the maximum wear the vulnerable component can withstand. The data processing module 102 can obtain the wear value increment of the vulnerable component and update the cumulative wear value of the vulnerable component in the data storage module 101 using the sum of the wear value increment and the cumulative wear value. The wear value increment indicates the wear incurred by the vulnerable component after completing a single chip test. The monitoring module 103 can monitor the life of the test board based on the cumulative wear value and wear threshold of the at least one vulnerable component in the data storage module 101, and issue an alarm when the life monitoring result meets preset conditions. This enables real-time monitoring of the test board's service life during chip mass production testing, allowing testers to promptly identify and repair test boards that have aged due to prolonged testing, thereby ensuring the reliability of chip testing. Compared with the prior art, the test board life monitoring device 100 provided in this solution realizes automatic monitoring of the life of the ATE test board, which can improve the efficiency and accuracy of the test board life monitoring, thereby ensuring the reliability of ATE chip testing.
[0036] Figure 2Schematic diagram of another test board life monitoring device provided in an embodiment of the present application. Figure 2 As shown, the test board life monitoring device 100 further includes a data acquisition module 104. The data acquisition module 104 can obtain the wear parameters of the fragile device after completing a chip test, and the data processing module 102 can determine the wear value increment of the fragile device based on the wear parameters.
[0037] The test board life monitoring device 100 further includes a data acquisition module 104. In one example, the data acquisition module 104 is a program code with a data acquisition function embedded after a chip mass production test program, and the data processing module 102 is a program code with a data processing function embedded after the data acquisition module 104, wherein the chip mass production test program is used for chip testing.
[0038] Figure 3 This is a schematic diagram of the working principle of a data acquisition module provided in an embodiment of the present application. Figure 3 As shown, data acquisition module 104 collects and records the wear parameters generated by each vulnerable component on the test board during the chip testing process. These wear parameters are related to the lifespan of the vulnerable components on the test board, such as the number of relay actuations, the maximum voltage and current flowing through the relay contact path, and their duration, the number of socket probe presses, the current and duration flowing through each socket probe path, and the current and duration of the LED light emission. In one example, at the beginning of each chip test, the test board's socket contacts the chip under test once, meaning the robot presses the chip onto the socket once. In this case, data acquisition module 104 records each socket press.
[0039] Figure 4 This is a schematic diagram of the working principle of a data processing module provided in an embodiment of the present application. Figure 4As shown, the data processing module 102 can obtain the loss parameters generated by each vulnerable device on the test board during the chip testing process recorded by the data acquisition module 104, and determine the loss value increment of the vulnerable device through the vulnerable device life algorithm in the data processing module 102. The vulnerable device life algorithm in the data processing module 102 includes a relay times algorithm, a relay path electric shock damage algorithm, a socket press times algorithm, a socket probe current damage algorithm, etc. Specifically, the relay times algorithm and the socket press times algorithm count the number of actions collected to quantify the number of actions. The relay path electric shock damage algorithm quantifies the maximum voltage, current and duration collected flowing through the relay electric shock path into a relay path electric shock damage loss coefficient, where the relay path electric shock damage coefficient = (applied voltage × current × duration) ÷ (rated voltage × rated current × rated usage time). The socket probe current damage algorithm quantifies the collected current and duration flowing through the socket probe into a socket probe current damage coefficient, where the socket probe current damage coefficient = (current flowing × duration of current flow) ÷ (maximum current flow capacity × maximum current flow duration).
[0040] During a chip test, the data acquisition module 104 records the wear parameters of each vulnerable component in each of at least one test item included in the chip test. After each record, the corresponding vulnerable component lifetime algorithm of the data acquisition module 104 is invoked and the results calculated by the lifetime algorithm are temporarily recorded in the data processing module 102. After the chip test is completed, the processed data results temporarily recorded in the data processing module 102 for each vulnerable component are added together to obtain the incremental wear value of each vulnerable component during the chip test.
[0041] In one example, a chip test includes two test items. Data acquisition module 104 collects and records the voltage, current, and duration applied to relay 1 channel 1 in the first test item. Using the electrical circuit electric shock damage algorithm, the electric shock damage coefficient for relay 1 channel 1 is calculated to be 0.01, which is temporarily stored in data processing module 102. Data acquisition module 104 collects and records the voltage, current, and duration applied to relay 1 channel 1 in the second test item. Using the electrical circuit electric shock damage algorithm, the electric shock damage coefficient is calculated to be 0.02, which is temporarily stored in data processing module 102. After completing both test items in this chip test, 0.01 and 0.02 are added together to obtain a loss value increment of 0.03 for relay 1 channel 1 in this chip test.
[0042] In an embodiment of the present application, the test board life monitoring device 100 further includes a data acquisition module 104. The data acquisition module 104 can obtain the loss parameters of a fragile device after completing a chip test. The data processing module 102 can determine the loss value increment of the fragile device based on the loss parameters. Through automated data acquisition and processing, the loss parameters of the fragile devices on the test board during the chip test process can be accurately quantified as loss value increments, and the workload of manual intervention and recording can be reduced, thereby improving the efficiency of chip testing. Moreover, using different life algorithms for the loss parameters of different fragile devices can make the assessment of the test board life more accurate and targeted.
[0043] Figure 5 is a schematic diagram of a data storage module provided in an embodiment of the present application, such as Figure 5 As shown, data storage module 101 is disposed on the test board and electrically connected to the chip testing equipment. Data storage module 101 can store the test board's identification code and associate the test board's identification code with the accumulated loss value and loss threshold of each vulnerable component on the test board.
[0044] Data storage module 101 is mounted on a test board and electrically connected to chip test equipment. In one example, ATE performs read and write operations on data storage module 101 via a connection line and IO port communication, and data storage module 101 is retained even after power failure. Data storage module 101 is a non-volatile memory, such as a Nor-Flash device.
[0045] A specific memory address in data storage module 101 stores an identification code (SN) for each test board, which uniquely identifies each test board. Different test boards have different identification codes. Each test board's identification code is associated with the cumulative loss value and loss threshold of each vulnerable component in that test board. The cumulative loss value and loss threshold of each vulnerable component are then stored item by item at the corresponding memory address in data storage module 101.
[0046] In an embodiment of the present application, a data storage module 101 is arranged on a test board, and the data storage module 101 is electrically connected to a chip testing device. The data storage module 101 can store an identification code of the test board, and associate the identification code of the test board with the cumulative loss value and loss threshold of each vulnerable component in the test board. Through the identification code of each test board stored in the data storage module 101, the loss generated and the maximum tolerable loss of the test board corresponding to the identification code can be viewed, thereby realizing the management of the life status of each test board and the monitoring of the life of each test board.
[0047] Figure 6 This is a schematic diagram of another test board life monitoring device provided in an embodiment of the present application. Figure 6As shown, the test board life monitoring device 100 further includes a display module 105. The monitoring module 103 can obtain an identification code of the test board and, based on the test board identification code, obtain the cumulative loss value, loss value increment, and loss threshold of each vulnerable component in at least one vulnerable component included in the test board. The display module 105 can display the test board identification code, as well as the cumulative loss value, loss value increment, and loss threshold of each vulnerable component in the test board associated with the test board identification code, through a user prompt information interface.
[0048] Monitoring module 103 can read the identification code of the test board stored in data storage module 101 on the test board. Based on the identification code, it can read the cumulative loss value and loss threshold of each vulnerable component on the test board associated with the identification code from data storage module 101. After a chip test is completed, monitoring module 103 can obtain the loss value increment for that chip test based on the cumulative loss value written to data storage module 101 by data processing module 102. At the same time, monitoring module 103 can send the cumulative loss value, loss value increment, and loss threshold of each vulnerable component on the test board to display module 105.
[0049] Figure 7 This is a schematic diagram showing the working principle of a display module provided in an embodiment of the present application. Figure 7 As shown, the display module 105 can receive the cumulative loss value, loss value increment and loss threshold of each vulnerable component in the test board sent by the monitoring module 103, and display the identification code of the test board and the cumulative loss value, loss value increment and loss threshold of each vulnerable component in the test board associated with the identification code of the test board through a user prompt interface.
[0050] In an embodiment of the present application, the test board life monitoring device 100 also includes a display module 105. The monitoring module 103 can obtain the identification code of the test board, and according to the identification code of the test board, obtain the cumulative loss value, loss value increment and loss threshold of each vulnerable device in at least one vulnerable device included in the test board. The display module 105 can display the identification code of the test board, as well as the cumulative loss value, loss value increment and loss threshold of each vulnerable device in the test board associated with the identification code of the test board through a user prompt information interface, and can comprehensively monitor the life status data of the test board, so that the life status of the test board can be analyzed and the use efficiency of the test system can be improved. Moreover, the life status of the vulnerable devices on the test board is intuitively displayed through the user prompt interface, so that the tester can intuitively understand the life status of each vulnerable device on the test board, so that he can respond and make decisions in time, thereby improving the reliability and stability of the test system.
[0051] In one possible implementation, the monitoring module 103 may also send an alarm message to the display module 105 for display when the cumulative loss value of at least one vulnerable component is greater than or equal to the loss threshold, and / or when the sum of the cumulative loss value and the loss value increment of at least one vulnerable component is greater than or equal to the loss threshold.
[0052] In one example, the monitoring module 103 is a program code having monitoring and alarm modules embedded after the data processing module 102 .
[0053] After a chip test is completed, the data processing module 102 updates the cumulative loss value in the data storage module 101. At this time, the monitoring module 103 compares the cumulative loss value of each vulnerable component with the loss threshold. Optionally, the cumulative loss value can be subtracted from the loss threshold. If the result is less than zero, it means that the cumulative loss value is greater than or equal to the loss threshold. If the cumulative loss value of at least one vulnerable component is greater than or equal to the loss threshold, the monitoring module 103 sends an alarm message and a maintenance reminder message for the vulnerable component whose cumulative loss value is greater than or equal to the loss threshold to the display module 105 for display (for example, Figure 7 ) and outputs an invalid chip test result. It is understood that if the cumulative loss value of at least one vulnerable component on the test board after the chip test is completed is greater than or equal to the loss threshold, it means that one or more vulnerable components on the test board have failed during the chip test, and the test board has partially or completely failed. Therefore, the results of the chip test using the partially or completely failed test board are also invalid.
[0054] After a chip test is completed, the monitoring module 103 simultaneously accumulates the incremental loss value for this chip test on top of the updated cumulative loss value. If the sum of the cumulative loss value and the incremental loss value of at least one vulnerable component is greater than or equal to the loss threshold, an alarm message and a maintenance reminder message for the vulnerable component whose sum of the cumulative loss value and the incremental loss value is greater than or equal to the loss threshold are sent to the display module 105 for display. It will be understood that if the sum of the cumulative loss value and the incremental loss value of at least one vulnerable component is greater than or equal to the loss threshold, this indicates that, based on the loss incurred by the vulnerable components on the test board during the current chip test, one or more vulnerable components are insufficient to support the next similar test. In this case, an alarm message is sent to the display module 105 for display, and the test of the next chip is aborted, thereby avoiding failure in the next chip test.
[0055] After receiving the alarm information sent by the monitoring module 103, the display module 105 will prominently display the alarm information and information about the vulnerable components that require maintenance. The chip test program will not proceed to the next chip test until the tester performs maintenance on the test board or confirms the information on the page. It should be noted that after issuing the alarm information, the monitoring module 103 will simultaneously send a command to the control module of the chip test equipment to terminate the chip test. In response to the command, the control module of the chip test equipment will suspend the chip test equipment from continuing to perform the chip test.
[0056] In an embodiment of the present application, the monitoring module 103 can also send an alarm message to the display module 105 for display when the cumulative loss value of at least one vulnerable component is greater than or equal to the loss threshold, and / or when the sum of the cumulative loss value and the loss value increment of at least one vulnerable component is greater than or equal to the loss threshold. This can intuitively display that there are vulnerable components on the test board that are approaching or reaching the loss threshold, thereby prompting the operator to repair the corresponding components on the test board in a timely manner, thereby avoiding the decline or loss of test efficiency caused by erroneous testing or failed testing due to the life limit of the test board, and can extend the service life of the test board, thereby improving the efficiency and reliability of chip mass production testing.
[0057] Figure 8 This is a flow chart of a test board life monitoring method provided by an embodiment of the present application. Figure 8 As shown, the test board life monitoring method includes the following steps 801 to 803:
[0058] Step 801: Obtain a cumulative loss value and a loss threshold of each vulnerable component in at least one vulnerable component included in a test board.
[0059] The test board includes one or more vulnerable devices, and the cumulative loss value and loss threshold of each vulnerable device on the test board are obtained. The test board is used for chip testing, the cumulative loss value is used to indicate the loss that has occurred in the vulnerable device, and the loss threshold is used to indicate the maximum loss that the vulnerable device can withstand.
[0060] Step 802: Obtain the incremental loss value of the fragile component, and update the accumulated loss value of the fragile component by the sum of the incremental loss value and the accumulated loss value of the fragile component.
[0061] Obtain the incremental loss value of the vulnerable device, where the incremental loss value indicates the loss of the vulnerable device after completing a chip test. Add the cumulative loss values corresponding to the expected incremental loss values of the vulnerable device to update the acquired cumulative loss value of the vulnerable device using the new cumulative loss value.
[0062] Step 803: Perform life monitoring on the test board based on the accumulated loss value and loss threshold of at least one vulnerable component, and issue an alarm message when the life monitoring result meets a preset condition.
[0063] Based on the cumulative loss value and loss threshold of at least one vulnerable component, the life of the test board is monitored with reference to preset conditions, and an alarm message is issued when the life monitoring result meets the preset conditions, wherein when the life monitoring result meets the preset conditions, it indicates that the life of at least one vulnerable component on the test board has exceeded the limit.
[0064] In an embodiment of the present application, the cumulative loss value and loss threshold of each vulnerable device in at least one vulnerable device included in the test board are obtained, the loss value increment of the vulnerable device is obtained, and the cumulative loss value of the vulnerable device is updated by the sum of the loss value increment and the cumulative loss value of the vulnerable device. The life of the test board is monitored based on the cumulative loss value and loss threshold of at least one vulnerable device, and an alarm message is issued when the life monitoring result meets the preset conditions. This can realize real-time monitoring of the service life of the test board during the chip mass production test process, so that testers can promptly discover test boards that have aging failures due to long-term testing and perform repairs, thereby ensuring the reliability of chip testing. Compared with the existing technology, this solution realizes automated monitoring of the life of ATE test boards, which can improve the efficiency and accuracy of test board life monitoring, thereby ensuring the reliability of ATE chip testing.
[0065] In a possible implementation, when obtaining the loss value increment of a fragile device, a loss parameter of the fragile device after completing a chip test may be obtained, and the loss value increment of the fragile device may be determined based on the loss parameter.
[0066] Obtain the wear parameters of a vulnerable component after completing a single chip test. These parameters are related to the lifespan of the vulnerable components on the test board, such as the number of relay actuations, the maximum voltage, current, and duration flowing through the relay contact path, the number of socket probe depressions, the current and duration flowing through each socket probe path, and the current and duration of the LED light emission. Based on these wear parameters, calculate the incremental wear value for each vulnerable component using the corresponding lifetime algorithm.
[0067] It should be noted that the specific content of the life algorithm corresponding to each vulnerable component can be found in the description of the aforementioned embodiment and will not be repeated here.
[0068] In an embodiment of the present application, the loss parameters of a fragile device after completing a chip test are obtained, and the incremental loss value of the fragile device is determined based on the loss parameters. Through automated data acquisition and processing, the loss parameters of the fragile devices on the test board during the chip test can be accurately quantified as incremental loss values. This reduces the workload of manual intervention and recording, improving the efficiency of chip testing. Furthermore, using different lifespan algorithms for the loss parameters of different fragile devices can make the assessment of the test board lifespan more accurate and targeted.
[0069] In one possible implementation, when obtaining the cumulative loss value and loss threshold of each vulnerable device in at least one vulnerable device included in the test board, the identification code of the test board can be obtained, and based on the identification code of the test board, the cumulative loss value and loss threshold of each vulnerable device in the test board can be determined.
[0070] Each test board has a unique identification code, or ID-SN, which is associated with the cumulative loss value and loss threshold of each vulnerable component on that board. By obtaining the identification code of the test board being tested, the cumulative loss value and loss threshold of each vulnerable component on that board can be determined based on that identification code.
[0071] In an embodiment of the present application, the identification code of the test board is obtained, and based on the identification code of the test board, the cumulative loss value and loss threshold of each vulnerable component in the test board are determined. Through the identification code of each test board, the loss already incurred and the maximum tolerable loss of the test board corresponding to the identification code can be viewed, thereby realizing the management of the life status of each test board and the monitoring of the life of each test board.
[0072] In one possible implementation, the test board life monitoring method can also display the identification code of the test board, as well as the cumulative loss value, loss value increment and loss threshold of each vulnerable component in the test board associated with the identification code of the test board through a user prompt information interface.
[0073] Based on the accumulated loss value, loss value increment and loss threshold of each vulnerable component on the test board, the identification code of the test board and the accumulated loss value, loss value increment and loss threshold of each vulnerable component on the test board associated with the identification code of the test board can be displayed through the user prompt information interface. In one example, the user prompt information interface is as follows: Figure 7 shown.
[0074] In an embodiment of the present application, a user prompt information interface displays the identification code of the test board, as well as the cumulative loss value, loss value increment, and loss threshold of each vulnerable component on the test board associated with the test board identification code. This user prompt interface can intuitively display the life status of vulnerable components on the test board, allowing testers to intuitively understand the life status of each vulnerable component on the test board, allowing them to make timely responses and decisions, thereby improving the reliability and stability of the test system.
[0075] In one possible implementation, the life of the test board is monitored based on the cumulative loss value and loss threshold of at least one vulnerable component, and an alarm message is issued when the life monitoring result meets the preset conditions. If the cumulative loss value of at least one vulnerable component is greater than or equal to the loss threshold, and / or the sum of the cumulative loss value and the loss value increment of at least one vulnerable component is greater than or equal to the loss threshold, the alarm message can be output and displayed through the user prompt information interface.
[0076] After a chip test is completed, based on the updated cumulative loss value of each vulnerable component, the loss threshold and the loss value increment generated by the test, if the cumulative loss value of at least one vulnerable component is greater than or equal to the loss threshold, and / or the sum of the cumulative loss value and the loss value increment of at least one vulnerable component is greater than or equal to the loss threshold, an alarm message is output and displayed through the user prompt information interface.
[0077] In an embodiment of the present application, when the cumulative loss value of at least one vulnerable component is greater than or equal to the loss threshold, and / or the sum of the cumulative loss value and the loss value increment of at least one vulnerable component is greater than or equal to the loss threshold, an alarm message is output, and the alarm message is displayed through a user prompt information interface. By outputting the alarm message, it is shown that there are vulnerable components on the test board that are close to or have reached the loss threshold, so that the operator can be prompted to repair the corresponding components on the test board in time, thereby avoiding the decline or loss of test efficiency caused by erroneous testing or failure testing due to the life limit of the test board.
[0078] It should be understood that the various embodiments in this specification are described in a progressive manner. References to the same or similar parts of the various embodiments can be made to each other, and each embodiment focuses on the differences from the other embodiments. In particular, the method embodiments are generally similar to the methods described in the apparatus embodiments, so their description is relatively simple. For relevant details, references to the descriptions of the other embodiments can be made.
[0079] It should be understood that the foregoing description of this specification is based on specific embodiments. Other embodiments are within the scope of the claims. In some cases, the actions or steps recited in the claims can be performed in an order different from that described in the embodiments and still achieve the desired results. Furthermore, the processes depicted in the accompanying drawings do not necessarily require the specific order shown or the sequential order to achieve the desired results. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.
[0080] It should be understood that an element described herein in the singular or shown in the drawings as only one does not limit the number of the element to one. In addition, modules or elements described or shown herein as separate may be combined into a single module or element, and modules or elements described or shown herein as single may be split into multiple modules or elements.
[0081] It should also be understood that the terms and expressions used herein are for descriptive purposes only, and the one or more embodiments of this specification should not be limited to these terms and expressions. The use of these terms and expressions does not mean to exclude any equivalent features of the illustrations and descriptions (or portions thereof), and it should be recognized that various modifications that may exist should also be included in the scope of the claims. Other modifications, variations, and substitutions may also exist. Accordingly, the claims should be deemed to cover all such equivalents.
Claims
1. A test board life monitoring device, characterized in that: include: Data storage module, data processing module and monitoring module; The data storage module is configured to store a cumulative loss value and a loss threshold value of each vulnerable device in at least one vulnerable device included in a test board, wherein the test board is used for chip testing, the cumulative loss value is used to indicate the loss incurred by the vulnerable device, and the loss threshold is used to indicate the maximum loss that the vulnerable device can withstand; The data processing module is configured to obtain a loss value increment of the fragile device, and update the accumulated loss value of the fragile device in the data storage module by the sum of the loss value increment and the accumulated loss value of the fragile device, wherein the loss value increment is used to indicate the loss generated by the fragile device after completing one chip test; The monitoring module is used to monitor the life of the test board according to the cumulative loss value and the loss threshold of the at least one vulnerable component in the data storage module, and to issue an alarm message when the life monitoring result meets a preset condition.
2. The device according to claim 1, characterized in that The device further comprises: a data acquisition module; The data acquisition module is used to obtain the loss parameters of the fragile device after completing a chip test; The data processing module is used to determine the loss value increment of the fragile component according to the loss parameter.
3. The device according to claim 2, characterized in that The data storage module is arranged on the test board, and the data storage module is electrically connected to the chip testing equipment; The data storage module is used to store the identification code of the test board and associate the identification code of the test board with the accumulated loss value and loss threshold of each of the vulnerable components in the test board.
4. The device according to claim 3, characterized in that The device further comprises: a display module; The monitoring module is configured to obtain an identification code of the test board, and obtain, based on the identification code of the test board, a cumulative loss value, a loss value increment, and a loss threshold value of each of at least one vulnerable component included in the test board; The display module is used to display the identification code of the test board, and the cumulative loss value, the loss value increment and the loss threshold of each vulnerable component in the test board associated with the identification code of the test board through a user prompt information interface.
5. The device according to claim 4, characterized in that The monitoring module is used to send an alarm message to the display module for display when the cumulative loss value of at least one of the vulnerable components is greater than or equal to the loss threshold, and / or when the sum of the cumulative loss value of at least one of the vulnerable components and the loss value increment is greater than or equal to the loss threshold.
6. A test board life monitoring method, characterized in that: include: Obtaining a cumulative loss value and a loss threshold value of each vulnerable device in at least one vulnerable device included in a test board, wherein the test board is used for chip testing, the cumulative loss value is used to indicate the loss incurred by the vulnerable device, and the loss threshold is used to indicate the maximum loss that the vulnerable device can withstand; Obtaining a loss value increment of the vulnerable device, and updating the accumulated loss value of the vulnerable device by summing the loss value increment of the vulnerable device and the accumulated loss value, wherein the loss value increment is used to indicate the loss generated by the vulnerable device after completing one chip test; The life of the test board is monitored according to the accumulated loss value and the loss threshold of the at least one vulnerable component, and an alarm message is issued when the life monitoring result meets a preset condition.
7. The method according to claim 6, characterized in that The obtaining of the loss value increment of the vulnerable component includes: Obtaining a loss parameter of the vulnerable device after completing a chip test; A loss value increment of the vulnerable component is determined based on the loss parameter.
8. The method according to claim 7, characterized in that The obtaining of the cumulative loss value and the loss threshold of each of the at least one vulnerable component included in the test board includes: Obtaining an identification code of the test board; According to the identification code of the test board, the cumulative loss value and the loss threshold of each of the vulnerable components in the test board are determined.
9. The method according to claim 8, characterized in that The method also includes: displaying the identification code of the test board, and the cumulative loss value, the loss value increment and the loss threshold of each vulnerable component in the test board associated with the identification code of the test board through a user prompt information interface.
10. The method according to claim 9, characterized in that The method includes: performing life monitoring on the test board according to the cumulative loss value and the loss threshold of the at least one vulnerable component, and issuing an alarm message when the life monitoring result meets a preset condition, including: If the accumulated loss value of at least one of the vulnerable components is greater than or equal to the loss threshold, and / or the sum of the accumulated loss value and the loss value increment of at least one of the vulnerable components is greater than or equal to the loss threshold, output an alarm message; The alarm information is displayed through the user prompt information interface.