Time-to-digital converter, analog-to-digital converter and image sensor
By delaying the comparison signals in traditional TDC circuits, the clock signal flip time is controlled, and the high power consumption problem caused by continuous flip of multi-phase clock signals is solved, and a low power consumption and high precision time-digital converter design is realized.
Patent Information
- Application Number
- CN202510725203.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-30
- Publication Date
- 2025-09-02
AI Technical Summary
In traditional time-digital converter (TDC) circuits, the continuous flip of multi-phase clock signals leads to high power consumption, making it difficult to take into account low power consumption and high quantization accuracy.
By introducing a logic operation unit to delay the comparison signal, the turn time of the multi-phase clock signal is controlled, and the second latch operation is enabled only under certain conditions, reducing the continuous turn time of the multi-phase clock signal.
It effectively reduces the power consumption of TDC circuits while maintaining high quantization accuracy to meet the needs of low power consumption and high precision.
Smart Images
Figure CN120578031A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of image processing, and in particular to a time-to-digital converter, an analog-to-digital converter, and an image sensor. Background Art
[0002] Image sensors used in specialized applications, such as those in the medical field, must balance low power consumption with high quantization accuracy. The time-to-digital converter (TDC), a common module in the analog-to-digital converter (ADC) of the image sensor's readout circuit, is a major contributor to image sensor power consumption.
[0003] Image sensors typically use column-level readout, so each column of pixels has its own dedicated TDC circuit. In a traditional TDC circuit, the column comparator's output comparison signal, cmpout, is ANDed with the quantization enable signal, tdc_en, to generate the TDC clock toggle enable signal, dll_run. While the enable signal, dll_run, is high, the multi-phase dll clock continuously counts. When the comparison signal, cmpout, flips low, the enable signal, dll_run, transitions low. The multi-phase dll clock maintains the level at the moment the comparison signal, cmpout, flips low and is input to the decoder.
[0004] In a traditional TDC circuit, the multi-phase dll clock starts to flip continuously when the quantization enable signal tdc_en is at a high level, and the flipping process continues until the comparison signal cmpout flips to a low level, resulting in high power consumption of the TDC circuit. Summary of the Invention
[0005] The present invention aims at providing a time-to-digital converter, comprising: a logic operation unit, a delay unit, a first latch, a second latch, a decoder, a third latch, and a frequency division unit, wherein: the logic operation unit has a first input terminal inputting a quantization enable signal, a second input terminal inputting a comparison signal output by a column comparator, a third input terminal coupled to the output terminal of the delay unit, a first output terminal coupled to the enable terminal of the first latch, and a second output terminal coupled to the enable terminal of the second latch; the logic operation unit is adapted to output a first enable signal to the enable terminal of the first latch when the quantization enable signal and the comparison signal are both at a first level; and output a second enable signal to the second latch when the delay signal and the quantization enable signal are both at the first level and the comparison signal is at a second level. The enable terminal of the register; the first level is different from the second level; the delay unit, whose input terminal inputs the comparison signal, and whose output terminal outputs the delay signal, wherein the delay signal is obtained by delaying the comparison signal for a preset time length; the first latch, whose output terminal is coupled to the frequency divider and the first input terminal of the decoder, outputs the first clock signal in the multi-phase clock signal; the second latch, whose output terminal is coupled to the second input terminal of the decoder, outputs the other clock signals in the multi-phase clock signal; the multi-phase clock signal includes N clock signals, N is a positive integer and N≥2; the other clock signals are obtained by performing phase shifting based on the first clock signal; the decoder, whose output terminal is coupled to the third latch, the output result of the decoder is the lowest n-bit value of the quantization result, and 2 n-1 =N; a frequency dividing unit, whose input end inputs the first clock signal, which includes Mn output ends, and each of the Mn output ends is connected to the third latch; M is the bit length corresponding to the quantization result; the third latch, whose output end outputs the digital code corresponding to the quantization result.
[0006] The comparison signal is delayed to obtain a delayed signal. When it is detected that the delayed signal and the quantization enable signal are both at the first level and the comparison signal is at the second level, the logic operation unit outputs a second enable signal to the enable terminal of the second latch to enable the second latch. In other words, the operating time of the second latch is equal to the preset delay duration. This significantly reduces the continuous toggle duration of the multi-phase clock signal and reduces the power consumption of the TDC circuit.
[0007] Optionally, the logic operation unit includes: a first AND gate circuit, a first inverter, and a second AND gate circuit, wherein:
[0008] Optionally, the first AND gate circuit has a first input terminal inputting the quantization enable signal, a second input terminal inputting the delay signal, an output terminal coupled to the first input terminal of the second AND gate circuit, and an output terminal coupled to the first output terminal of the logic operation unit; the first inverter has a first input terminal inputting the comparison signal, and an output terminal coupled to the second input terminal of the second AND gate circuit; the second AND gate circuit has an output terminal coupled to the second output terminal of the logic operation unit.
[0009] Optionally, the logic operation unit includes: a NAND gate circuit, a second inverter and a first NOR gate circuit, wherein: the first input end of the NAND gate circuit inputs the quantization enable signal, the second input end of the NAND gate circuit inputs the delay signal, and the output end is coupled to the input end of the second inverter and the first input end of the first NOR gate circuit; the output end of the second inverter is coupled to the first output end of the logic operation unit; the second input end of the first NOR gate circuit inputs the comparison signal, and the output end is coupled to the second output end of the logic operation unit.
[0010] Optionally, the logic operation unit includes: a third inverter, a fourth inverter, a second NOR gate circuit, a fifth inverter and a third NOR gate circuit, wherein: the third inverter has an input end inputting the quantization enable signal, and an output end coupled to the first input end of the second NOR gate circuit; the fourth inverter has an input end inputting the delay signal, and an output end coupled to the second input end of the second NOR gate circuit; the second NOR gate circuit has an output end coupled to the input end of the fifth inverter and the first output end of the logic operation unit; the fifth inverter has an output end coupled to the first input end of the third NOR gate circuit; the third NOR gate circuit has a second input end inputting the comparison signal, and an output end coupled to the second output end of the logic operation unit.
[0011] Optionally, the preset time length is associated with an equivalent input impedance of the third latch.
[0012] Optionally, the preset duration is not less than the latching time of the third latch.
[0013] Optionally, both the first latch and the second latch are D latches.
[0014] In a second aspect, the present invention further provides an analog-to-digital converter, comprising any one of the above-mentioned time-to-digital converters.
[0015] In a third aspect, the present invention further provides an image sensor comprising the analog-to-digital converter described above. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 This is a timing diagram of a readout process of a pixel signal of an existing image sensor;
[0017] Figure 2 This is a schematic diagram of the quantization timing of an existing time-to-digital converter;
[0018] Figure 3 It is a structural diagram of an existing TDC;
[0019] Figure 4 is a schematic structural diagram of a time-to-digital converter according to an embodiment of the present invention;
[0020] Figure 5 1 is a schematic structural diagram of a logic operation unit in an embodiment of the present invention;
[0021] Figure 6 is a schematic structural diagram of another logic operation unit in an embodiment of the present invention;
[0022] Figure 7 1 is a schematic structural diagram of another logic operation unit in an embodiment of the present invention;
[0023] Figure 8 This is a working timing diagram of a time-to-digital converter in an embodiment of the present invention. DETAILED DESCRIPTION
[0024] like Figure 1 As shown in FIG, a timing diagram of the readout process of a conventional image sensor pixel signal is given. In the pixel signal readout process, the pixel is first reset and its reset voltage V rst Save to V bitline Pull the TDC quantization enable signal tdc_en from low level to high level, and the counter in the TDC starts counting. At the same time, the ramp generator starts to generate a small ramp, that is, Figure 1 Medium V ramp The first descent.
[0025] The comparator in the image sensor readout circuit ADC compares the analog signal V ramp and V bitline The level of the column comparator outputs the comparison signal cmpout between the two voltage signals (i.e. V ramp and V bitline ) is flipped, the counter stops counting. rst During this period, the counter clock keeps turning over and counting. When the comparison signal cmpout turns over, the clock stops turning over and the generated digital code D rst is stored in a latch. At this time, the potential of each clock signal is fixed, forming a digital code D rst, stored in latch. Then reset cmpout, pixel transmits light-sensitive signal, V bitline Gradually decreases to a stable value V sig , V rst -V sig This is the signal intensity of the light response. After that, tdc_en is pulled high for the second time, and the ramp generator generates a large ramp, repeating the above counting and quantization process. sig During the period, the counter flips and quantizes V sig , generate digital code D sig . Use D sig Subtract D rst That is the analog signal V rst -V sig This quantization operation, which performs the difference between the two quantizations, can remove readout noise caused by non-ideal effects such as offset, clock delay, and comparator charge injection. This technique, known as Correlated Double Sampling (CDS), is widely used in image sensors.
[0026] TDC count quantization typically uses a multi-phase delay-locked loop (DLL) clock signal (hereinafter referred to as a multi-phase clock signal) to reduce the phase-locked loop (PLL) output frequency requirements for high-precision image processing. Depending on the accuracy requirements, the number of phases in the multi-phase clock signal can be 2, 4, 8, or 16.
[0027] Taking the 8-phase clock signal as an example, dll <3:0> includes the clock signal dll <0> ,dll <1> ,dll <2> and dll <3> , where, from dll <0> to dll <3> The phase is delayed by 45°. Figure 2 As shown in FIG. , a waveform diagram of TDC circuit count quantization is given.
[0028] dll <0> Perform successive frequency division to obtain qck <3> 、qck <4> 、…….qck <3> The frequency is dll <0> 1 / 2, qck <4> The frequency is qck <3> dll<3:0> divides a clock cycle into 8 phases, which are decoded into 3-bit binary numbers 000, 001, 010, ..., 111 in chronological order, and the lower 3-bit digital code qbit<2:0> of the quantization result is obtained. <3> The corresponding level is qbit <3> ,qck <4> The corresponding level is qbit <4> , and so on, the digital code corresponding to the quantization result output by TDC can be obtained.
[0029] In the prior art, image sensors usually use column-level readout, so each column of pixels corresponds to a set of TDC circuits. Figure 3, a structural schematic diagram of an existing TDC is given. Figure 3 The TDC circuit in the embodiment adopts the CDS technology and multi-phase clock mentioned above and can output a single column of 14-bit digital code.
[0030] Figure 3 In the embodiment, the TDC circuit includes an AND gate circuit, a D latch, a decoder and a latch.
[0031] The comparison signal cmpout output by the column comparator and the quantization enable signal tdc_en are input to the AND gate circuit. After the AND operation is performed by the AND gate circuit, the TDC clock inversion enable signal dll_run is obtained.
[0032] The enable signal dll_run is input to the enable terminal (C) of the D-latch (D-latch). The clock signal clk<3:0> is input to the D-latch input terminal. While the enable signal dll_run is high, the multi-phase clock signals dll<3:0> continuously toggle and count. When the comparison signal cmpout toggles low, the enable signal dll_run transitions to a low level. The multi-phase clock signals dll<3:0> maintain the level at the moment the comparison signal cmpout toggles and are input to the decoder input terminal in.
[0033] The decoder's enable terminal en inputs the enable signal dll_run_b, which is obtained by inverting the enable signal dll_run. Figure 3 As shown, after the enable signal dll_run is input to the inverter, the enable signal dll_run_b is obtained. The output terminal of the decoder outputs the lower 3 bits <2:0> of the quantization result.
[0034] When the enable signal dll_run is high, the first clock signal dll in dll<3:0> <0> After the two-way frequency division circuit Div2, we get qbit <3> , input to the latch input in <3> . And, qbit <3> Input to the two-way frequency division circuit Div2 to get qbit <4> And so on. The latch mentioned above includes a latch and a CDS processing module.
[0035] At the moment of cmpout flipping, qbit <3> ~ qbit <13> The high <13:3> bits of the quantization result are directly input into the latch together with the low 3 bits <2:0> of the quantization result, and the latch finally outputs the digital code D<13:0>, which is the D sig -D rst .
[0036] Combined with the above Figures 1 to 3It can be seen that in the counting process of the existing TDC circuit, the multi-phase clock signal dll<3:0> is in a continuous flipping state after the quantization enable signal tdc_en is pulled high, and continues until the flipping moment of the comparison signal cmpout, such as Figure 1 The higher the image brightness and the faster the line rate, the longer the shadow portion will occupy in the image sensor's operating time, resulting in greater power consumption.
[0037] In an embodiment of the present invention, a delay process is performed on the comparison signal to obtain a delayed signal. When it is detected that the delayed signal and the quantization enable signal are both at a first level, and the comparison signal is at a second level, the logic operation unit outputs a second enable signal to the enable terminal of the second latch to enable the second latch. In other words, the operating time of the second latch is equal to the preset delay duration. This significantly reduces the continuous toggle duration of the multi-phase clock signal and reduces the power consumption of the TDC circuit.
[0038] That is, the second latch is enabled only when the quantization enable signal and the delay signal are both at a high level and the comparison signal is at a low level.
[0039] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0040] The embodiment of the present invention provides a time-to-digital converter, referring to Figure 4 .
[0041] In an embodiment of the present invention, the time-to-digital converter may include: a logic operation unit, a delay unit, a first latch, a second latch, a decoder, a latch, and a frequency division unit.
[0042] In an embodiment of the present invention, the first input terminal of the logic operation unit can input the quantization enable signal tdc_en, the second input terminal of the logic operation unit can input the comparison signal cmpout output by the column comparator, and the third input terminal of the logic operation unit can be coupled to the output terminal of the delay unit; the first output terminal of the logic operation unit is coupled to the enable terminal of the first latch, and the second output terminal of the logic operation unit is coupled to the enable terminal of the second latch.
[0043] In an embodiment of the present invention, for the logic operation unit, when it is detected that the quantization enable signal and the delay signal are both at the first level, the first enable signal is output to the enable end of the first latch to enable the first latch; when it is detected that either the quantization enable signal or the delay signal is at the first level and the other is at the second level, the output of the first enable signal is stopped and the first latch is not enabled.
[0044] When it is detected that the delay signal and the quantization enable signal are both at the first level and the comparison signal is at the second level, the logic operation unit can output the second enable signal to the enable end of the second latch to enable the second latch; when either the delay signal or the quantization enable signal is not at the first level, the logic operation unit will not output the second enable signal; or, when the comparison signal is at the first level, regardless of whether the delay signal and the quantization enable signal are both at the first level, the logic operation unit will not output the second enable signal.
[0045] In a specific implementation, the logic operation unit outputs a first enable signal via its first output terminal, and outputs a second enable signal via its second output terminal.
[0046] In a specific implementation, the first level may be a high level described in the field of digital circuit technology, and the second level may be a low level described in the field of digital circuit technology.
[0047] Therefore, in the embodiment of the present invention, the second latch is enabled only when the quantization enable signal and the delay signal are both at a high level and the comparison signal is at a low level.
[0048] Reference Figure 5 , a structural diagram of a logic operation unit in an embodiment of the present invention is given.
[0049] Figure 5 In the embodiment, the logic operation unit may include: a first AND gate circuit, a first inverter and a second AND gate circuit.
[0050] In a specific implementation, the first input terminal of the first AND gate circuit can be coupled to the first input terminal of the logic operation unit and input the quantization enable signal tdc_en; the second input terminal of the first AND gate circuit can be coupled to the third input terminal of the logic operation unit and input the delay signal cmpout_dly; the output terminal of the first AND gate circuit can be coupled to the first input terminal of the second AND gate circuit, and the output terminal of the first AND gate circuit is coupled to the first output terminal of the logic operation unit.
[0051] The first AND gate circuit performs an AND operation on the quantization enable signal tdc_en and the delay signal cmpout_dly. The obtained AND operation result is output to the first input terminal of the second AND gate circuit. The first AND operation result is also output via the first output terminal of the logic operation unit. In other words, the first output terminal of the logic operation unit outputs the first AND operation result.
[0052] The first input terminal of the first inverter inputs the comparison signal cmpout, and the output terminal of the first inverter is coupled to the second input terminal of the second AND gate circuit. The first inverter inverts the input comparison signal cmpout to obtain a first inversion result.
[0053] The output of the second AND gate circuit is coupled to the second output of the logic operation unit. Alternatively, the output of the second AND gate circuit serves as the second output of the logic operation unit. The second AND gate circuit performs an AND operation on the first AND operation result and the first inverted result to obtain a second AND operation result.
[0054] Reference Figure 6 , a structural diagram of another logic operation unit in an embodiment of the present invention is given.
[0055] Figure 6 In the embodiment, the logic operation unit may include: a NAND gate circuit, a second inverter, and a first NOR gate circuit, wherein:
[0056] The first input terminal of the NAND gate circuit inputs the quantization enable signal tdc_en, the second input terminal of the NAND gate circuit inputs the delay signal cmp_dly, and the output terminal of the NAND gate circuit is coupled to the input terminal of the second inverter and the first input terminal of the first NOR gate circuit;
[0057] The output terminal of the second inverter is coupled to the first output terminal of the logic operation unit, and the second inverter inverts the output of the NAND gate circuit and outputs the obtained second inverted result through the first output terminal of the logic operation unit;
[0058] The second input terminal of the first NOR gate circuit is input with the comparison signal cmpout, and the output terminal of the first NOR gate circuit is coupled to the second output terminal of the logic operation unit.
[0059] Reference Figure 7 , gives a structural diagram of another logic operation unit in an embodiment of the present invention.
[0060] Figure 7 In the embodiment, the logic operation unit includes a third inverter, a fourth inverter, a second NOR gate circuit, a fifth inverter and a third NOR gate circuit, wherein:
[0061] The input terminal of the third inverter inputs the quantization enable signal tdc_en, the output terminal of the third inverter is coupled to the first input terminal of the second NOR gate circuit; the third inverter outputs a third inverted result;
[0062] The input terminal of the fourth inverter inputs the delayed signal, the output terminal of the fourth inverter is coupled to the second input terminal of the second NOR gate circuit; the fourth inverter outputs a fourth inverted result;
[0063] The output terminal of the second NOR gate circuit is coupled to the input terminal of the fifth inverter and the first output terminal of the logic operation unit;
[0064] The output terminal of the fifth inverter is coupled to the first input terminal of the third NOR gate circuit;
[0065] The second input terminal of the third NOR gate circuit is input with the comparison signal cmpout, and the output terminal of the third NOR gate circuit is coupled to the second output terminal of the logic operation unit.
[0066] It is understandable that the specific structure of the logic operation unit is not limited to the above Figures 5 to 7 Any operation unit capable of implementing the following functions may be used as the logic operation unit described in the embodiment of the present invention: when the delay signal and the quantization enable signal tdc_en are both at the first level and the comparison signal cmpout is at the second level, generating and outputting the second enable signal.
[0067] In an embodiment of the present invention, the input terminal of the delay unit can input the comparison signal cmpout, and the output terminal of the delay unit can output the delay signal cmpout_dly. The delay unit can delay the comparison signal cmpout for a preset time length.
[0068] In a specific implementation, the preset time length may be associated with the equivalent input impedance of the third latch, may be no less than the latch time of the latch, and may be in the nanosecond (ns) level.
[0069] In some embodiments, the preset time length may be less than 10 ns.
[0070] In the embodiment of the present invention, the output terminal of the first latch may be coupled to the first input terminal of the decoder and the frequency divider, and may output the first clock signal of the multi-phase clock signal.
[0071] The output terminal of the second latch can be coupled to the second input terminal of the decoder, and can output other clock signals in the multi-phase clock signal.
[0072] In a specific implementation, the multi-phase clock signal may include N clock signals, where N is a positive integer and N≥2. Other clock signals in the multi-phase clock signal may be obtained by performing an offset based on the first clock signal.
[0073] Taking the multi-phase clock signal as an 8-phase clock signal as an example, combined with Figure 2 , the multi-phase clock signal includes 4 clock signals, which are dll <0> ,dll <1> ,dll <2> and dll <3> ,dll <0> For the first clock signal, dll <1> ,dll <2> and dll <3> with dll <0> Same frequency, dll <0> The phase is 0, dll <1> The phase is 45°, dll <2> The phase is 90°, dll <3> The phase is 135°.
[0074] In a specific implementation, the input terminal of the first latch inputs the clock signal clk <0> The input terminal of the second latch inputs the clock signal clk <n-1:1>The output terminal of the first latch outputs the multi-phase clock signal dllx<0>, and the output terminal of the second latch outputs the multi-phase clock signal dllx<N-1:1>.
[0075] In an embodiment of the present invention, the output terminal of the decoder can be coupled to the third latch, and the output terminal result of the decoder is the lowest n-bit value of the quantization result, and 2 n-1 =N.
[0076] In a specific implementation, the first input terminal of the decoder inputs the first clock signal in the multi-phase clock signal, and the second input terminal of the decoder inputs the other clock signals in the multi-phase clock signal; the enable signal input to the enable terminal of the decoder is inverted with the enable signal input to the enable terminal of the first latch.
[0077] Specifically, the first input terminal in of the decoder <0> Import dll <0> , the second input terminal of the decoder in <n-1:1>Import dll <n-1:1>The enable terminal of the decoder inputs the enable signal dll0_run_b. The enable signal dll0_run_b is the inverse of the enable signal dll0_run.
[0078] Taking the multi-phase clock signal including 4 clock signals as an example, the first input terminal in of the decoder <0> Enter the input dll <0> The second input terminal in<3:1> of the decoder inputs dll<3:1>. The output terminal of the decoder outputs the lower 3 bits qbit<2:0> of the quantization result.
[0079] In the embodiment of the present invention, the input end of the frequency dividing unit inputs the first clock signal dll <0> , the frequency division unit includes Mn output terminals and Mn two-frequency division circuits, wherein:
[0080] The first clock signal dll is input to the input end of the first divide-by-two circuit <0> , an output terminal of the first divide-by-two frequency circuit is coupled to the third latch;
[0081] An input terminal of the second divide-by-two frequency circuit is coupled to an output terminal of the first divide-by-two frequency circuit, and an output terminal of the second divide-by-two frequency circuit is coupled to a third latch;
[0082] An input terminal of the third divide-by-two frequency circuit is coupled to an output terminal of the second divide-by-two frequency circuit, and an output terminal of the third divide-by-two frequency circuit is coupled to a third latch;
[0083] And so on.
[0084] Take M as 14 and N as 4 as an example. The first clock signal dll is input to the input end of the first divide-by-two circuit. <0> The output of the first divide-by-two circuit outputs qbit <3> ,qbit <3> The frequency of the first clock signal dll <0> The output of the second divide-by-two circuit outputs qbit <4> ,qbit <4> The frequency is qbit <3> Similarly, the output of the 11th two-way frequency divider circuit outputs qbit <13> .
[0085] In the embodiment of the present invention, the output terminal of the third latch can output a digital code corresponding to the quantization result. The digital code D output by the third latch <m:0>That is the digital code corresponding to the quantization result.
[0086] In a specific implementation, both the first latch and the second latch can be D latches.
[0087] It is understandable that the first latch and the second latch may also be other types of latches and are not limited to the above-mentioned D latch.
[0088] The specific working principle and timing of the time-to-digital converter provided in the above embodiment of the present invention are described below.
[0089] like Figure 8 FIG. 1 shows a working timing diagram of a time-to-digital converter in an embodiment of the present invention. Figure 8 In the example, M is 14 and N is 4.
[0090] Figure 8 The dotted line portion in FIG. 1 is a waveform diagram of the dll clock in the prior art.
[0091] The comparison signal cmpout is delayed to obtain the delayed signal cmpout_dly. The time difference between the falling edge of the comparison signal and the falling edge of the delayed signal (i.e., the delay duration) is t dly . t dly It is possible to ensure that the third latch stores the levels of each clock signal, and the specific duration may be related to the input impedance of the third latch.
[0092] Figure 8 In the , dllx<3:1> is valid only when the quantization enable signal tdc_en is high, the comparison signal cmpout is low and the delay signal cmpout_dly is high. dly Because qck<13:3> is generated by dll <0> Frequency division is obtained, so dll <0> qck<13:3> is valid when the quantization enable signal tdc_en is high and the delay signal cmpout_dly is high. <0> Counting starts when the quantization enable signal tdc_en is high, and stops when the delay signal cmpout_dly flips to a low level. The flipping time is Figure 8 t in cnt .
[0093] When the delay signal cmpout_dly turns to a low level, the clock levels inputted into the input terminals of the third latch are latched to form the digital code D<13:0>.
[0094] Compared with the prior art, the time-to-digital converter provided in the embodiment of the present invention has an actual quantization time of t cnt , while the actual quantization time of the existing time-to-digital converter is t cnt -t dly Due to t dly The existence of introduces quantization bias k. Considering that image sensors usually use CDS operation, (D sig +k)-(D rst +k) = D sig -D rst , which is still the digital output of the traditional solution, so the quantization deviation k will not affect the quantization result of the signal light intensity.
[0095] In summary, in the embodiments of the present invention, a delay process is performed on the comparison signal to obtain a delayed signal. When it is detected that the delayed signal and the quantization enable signal are both at the first level, and the comparison signal is at the second level, the logic operation unit outputs a second enable signal to the enable terminal of the second latch to enable the second latch. In other words, the operating time of the second latch is equal to the preset delay duration. This significantly reduces the continuous toggle duration of the multi-phase clock signal, thereby reducing the power consumption of the TDC circuit.
[0096] The present invention also provides an analog-to-digital converter, comprising the time-to-digital converter provided by any one of the above embodiments.
[0097] The present invention also provides an image sensor, comprising the above-mentioned analog-to-digital converter.
[0098] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.
Claims
1. A time-to-digital converter, characterized in that: include: A logic operation unit, a delay unit, a first latch, a second latch, a decoder, a third latch, and a frequency division unit, wherein: The logic operation unit has a first input terminal inputting a quantization enable signal, a second input terminal inputting a comparison signal output by the column comparator, a third input terminal coupled to the output terminal of the delay unit, a first output terminal coupled to the enable terminal of the first latch, and a second output terminal coupled to the enable terminal of the second latch; The logic operation unit is adapted to output a first enable signal to the enable terminal of the first latch when the quantization enable signal and the comparison signal are both at a first level; and output a second enable signal to the enable terminal of the second latch when the delay signal and the quantization enable signal are both at the first level and the comparison signal is at a second level; the first level is different from the second level; The delay unit has an input terminal inputting the comparison signal and an output terminal outputting a delay signal, wherein the delay signal is obtained by delaying the comparison signal for a preset time length; The first latch has an output terminal coupled to the frequency divider and the first input terminal of the decoder, and outputs a first clock signal in the multi-phase clock signal; The second latch, having an output terminal coupled to the second input terminal of the decoder, outputs other clock signals in the multi-phase clock signal; the multi-phase clock signal includes N clock signals, where N is a positive integer and N≥2; the other clock signals are obtained by performing phase shifting on the first clock signal; The decoder, whose output terminal is coupled to the third latch, has an output result that is the lowest n-bit value of the quantization result, and 2 n-1 =N; The frequency dividing unit has an input terminal inputting the first clock signal and includes Mn output terminals, and each of the Mn output terminals is connected to the third latch; M is a bit length corresponding to the quantization result; The third latch has an output terminal that outputs a digital code corresponding to the quantization result.
2. The time-to-digital converter according to claim 1, wherein The logic operation unit includes: a first AND gate circuit, a first inverter and a second AND gate circuit, wherein: The first AND gate circuit has a first input terminal inputting the quantization enable signal, a second input terminal inputting the delay signal, an output terminal coupled to the first input terminal of the second AND gate circuit, and an output terminal coupled to the first output terminal of the logic operation unit; The first inverter has a first input terminal inputting the comparison signal, and an output terminal coupled to the second input terminal of the second AND gate circuit; An output terminal of the second AND gate circuit is coupled to a second output terminal of the logic operation unit.
3. The time-to-digital converter according to claim 1, wherein The logic operation unit includes: a NAND gate circuit, a second inverter and a first NOR gate circuit, wherein: The NAND gate circuit has a first input terminal inputting the quantization enable signal, a second input terminal inputting the delay signal, and an output terminal coupled to the input terminal of the second inverter and the first input terminal of the first NOR gate circuit; The second inverter has an output terminal coupled to the first output terminal of the logic operation unit; The first NOR gate circuit has a second input terminal inputting the comparison signal, and an output terminal coupled to the second output terminal of the logic operation unit.
4. The time-to-digital converter according to claim 1, wherein: The logic operation unit includes: a third inverter, a fourth inverter, a second NOR gate circuit, a fifth inverter and a third NOR gate circuit, wherein: The third inverter has an input terminal inputting the quantization enable signal and an output terminal coupled to the first input terminal of the second NOR gate circuit; The fourth inverter has an input terminal inputting the delayed signal and an output terminal coupled to the second input terminal of the second NOR gate circuit; The second NOR gate circuit has an output terminal coupled to the input terminal of the fifth inverter and the first output terminal of the logic operation unit; The fifth inverter has an output terminal coupled to the first input terminal of the third NOR gate circuit; The third NOR gate circuit has a second input terminal inputting the comparison signal, and an output terminal coupled to the second output terminal of the logic operation unit.
5. The time-to-digital converter according to claim 1, wherein: The preset time length is associated with the equivalent input impedance of the third latch.
6. The time-to-digital converter according to claim 5, wherein: The preset time length is not less than the latching time of the third latch.
7. The time-to-digital converter according to claim 1, wherein: The first latch is a D latch, and the second latch is a D latch.
8. An analog-to-digital converter, characterized in that The method comprises the time-to-digital converter according to any one of claims 1 to 7.
9. An image sensor, characterized in that: comprising the analog-to-digital converter of claim 8.