Electronic device, data processing method, device, medium, and program product

Abstract

The application discloses an electronic device, a data processing method, a device, a medium and a program product in the technical field of computers. In various boards, a first memory is used to store processor identification information corresponding to the boards; a second memory is used to store marking information of slots included in the various boards, and the first memory and the second memory are gated by a gate on a second link. Any processor can access the first memory and the second memory through a second connector in each board and through the second link, so as to confirm silk screen information of slots of the various boards according to data stored in the first memory and the second memory, and positioning of the slots of the various boards and devices connected thereto is completed. The scheme does not need to trigger the lamps of the various slots to flash one by one, and the positioning efficiency of the physical slots can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, and particularly relates to an electronic device, a data processing method, a device, a medium and a program product. BACKGROUND

[0002] Generally, an indicator light can be arranged at a physical slot, and the physical position of the device connected at the physical slot is located by triggering the light of the specific slot to flicker. In a high-density server, the number of physical slots is large, and the light of each slot needs to be triggered to flicker one by one, which leads to low positioning efficiency of the physical slot.

[0003] Therefore, how to improve the positioning efficiency of the physical slot is a problem to be solved by those skilled in the art. SUMMARY

[0004] Therefore, the present application aims to provide an electronic device, a data processing method, a device, a medium and a program product to improve the positioning efficiency of the physical slot.

[0005] In a first aspect, the present application provides an electronic device, comprising: at least one processor and at least one board card; wherein any target board card in the at least one board card comprises: a first connector, a second connector, a gate, a first memory and a second memory; the first connector is connected with the gate through a first link; the second connector is connected with the gate and the second memory through a second link; the gate is further connected with the first memory; the gate is used for: gating the first link or the second link; the first memory is used for: storing the processor identification information corresponding to the target board card; the second memory is used for: storing the marking information of the slots included in each board card; and correspondingly, the first connector and the second connector in each board card are connected with any one processor.

[0006] In a second aspect, the present application provides a data processing method applied to an electronic device, the electronic device comprising at least one processor and at least one board card; wherein any target board card in the at least one board card comprises a first connector, a second connector, a gate, a first memory and a second memory; the first connector is connected to the gate through a first link; the second connector is connected to the gate and the second memory through a second link; the gate is further connected to the first memory; the gate is configured to gate the first link or the second link; the first memory is configured to store processor identification information corresponding to the target board card; the second memory is configured to store marking information of slots included in each board card; the first connector and the second connector in each board card are connected to any one processor; correspondingly, the data processing method comprises: after the second link in the target board card is connected, any processor controls a basic input / output system to read the processor identification information from the first memory and read the marking information of slots included in the target board card from the second memory; and determines silk screen information of the slots included in the target board card according to the processor identification information and the marking information of the slots included in the target board card.

[0007] In a third aspect, the present application provides an electronic device comprising a memory configured to store a computer program; and a processor configured to execute the computer program to implement the data processing method disclosed above.

[0008] In a fourth aspect, the present application provides a non-volatile storage medium configured to store a computer program, wherein the computer program is executed by a processor to implement the data processing method disclosed above.

[0009] In a fifth aspect, the present application provides a computer program product comprising computer programs / instructions, which are executed by a processor to implement the steps of the data processing method disclosed above.

[0010] According to the above scheme, the present application provides an electronic device comprising at least one processor and at least one board card; wherein any target board card in the at least one board card comprises a first connector, a second connector, a gate, a first memory and a second memory; the first connector is connected to the gate through a first link; the second connector is connected to the gate and the second memory through a second link; the gate is further connected to the first memory; the gate is configured to gate the first link or the second link; the first memory is configured to store processor identification information corresponding to the target board card; the second memory is configured to store marking information of slots included in each board card; correspondingly, the first connector and the second connector in each board card are connected to any one processor.

[0011] It can be seen that the application has the following beneficial effects: in each board card, the first memory is used to store the processor identification information corresponding to the board card; the second memory is used to store the marking information of the slot included in each board card, and the first memory and the second memory are gated by the gate of the second link, so that any processor can access the first memory and the second memory through the second connector in each board card and through the second link, thereby confirming the silk screen information of the slot of each board card according to the data stored in the first memory and the second memory, and positioning the slot of each board card and the connected equipment is completed. The scheme does not need to trigger the lamps of each slot to flash one by one, and the positioning efficiency of the physical slot can be improved.

[0012] Correspondingly, the data processing device, medium and program product provided by the application also have the above technical effects. BRIEF DESCRIPTION OF DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description only constitute a part of the embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of the provided drawings.

[0014] Figure 1 An electronic device schematic diagram disclosed by the present application;

[0015] Figure 2 Another electronic device schematic disclosed by the present application;

[0016] Figure 3 A data processing method flow chart disclosed by the present application;

[0017] Figure 4 Another electronic device schematic diagram disclosed by the present application;

[0018] Figure 5 A server structure diagram provided by the present application;

[0019] Figure 6 A terminal structure diagram provided by the present application. DETAILED DESCRIPTION

[0020] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments only constitute a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the present application.

[0021] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0022] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0023] Typically, an indicator light can be set at a physical slot to trigger the light in a specific slot to flash, thereby locating the physical location of the device connected to that slot. In high-density servers, there are many physical slots, and the need to trigger the light in each slot to flash individually results in low physical slot location efficiency. Therefore, this application provides a solution that can improve the efficiency of physical slot location.

[0024] See also Figure 1 As shown, an embodiment of the present application discloses an electronic device comprising: at least one processor and at least one board; wherein any target board in the at least one board comprises: a first connector, a second connector, a selector, a first memory, and a second memory; the first connector is connected to the selector via a first link; the second connector is connected to the selector and the second memory via a second link; and the selector is further connected to the first memory. The at least one processor may be provided on a motherboard. The board may be specifically a server expansion card or a riser card.

[0025] Among them, the selector is used to select the first link or the second link; the first memory is used to store the processor identification information corresponding to the target board; the second memory is used to store the label information of the slots included in each board, such as the label information of slot 0 is SLOT0; accordingly, the first connector and the second connector in each board are connected to any processor.

[0026] In one example, the first connector is an MCIO connector, and the second connector is an I2C (Inter-Integrated Circuit Bus) connector. Accordingly, the I2C connector on each board is connected to the processor via the motherboard-side I2C connector (i.e., the motherboard-side second connector). To extend the I2C link, an I2C switch (i.e., an expander) can be provided between the processor and the motherboard-side I2C connector. For example, a processor is connected to an I2C switch, and the I2C switch's eight outputs are connected to eight motherboard-side I2C connectors, which are then connected to eight I2C connectors on the board. Accordingly, the MCIO connector on each board is connected to a port on a processor via the motherboard-side MCIO connector (i.e., the motherboard-side first connector). For example, a processor has four ports, each of which is connected to a motherboard-side MCIO connector, and each motherboard-side MCIO connector is connected to the first connector on each board. In one embodiment, the processor is connected to multiple connectors (e.g., multiple motherboard-side I2C connectors) via an expander (e.g., an I2C switch), and each connector is connected to the second connector on a different board. That is: any processor is connected to multiple motherboard-side second connectors through an expander, and each motherboard-side second connector is respectively connected to the second connector in a different board; any processor is connected to multiple motherboard-side first connectors, and each motherboard-side first connector is respectively connected to the first connector in a different board.

[0027] In one embodiment, the gate includes: a selector (such as Figure 2 MUX in the ) and the signaler connected to the selector (such as Figure 2 IO EXPANDER in the signal device is used to: output for connecting the first link (such as Figure 2 or outputs a first signal for connecting a second link (such as MCIO I2C in Figure 2 The selector is used to: connect the first link and disconnect the second link according to the first signal; or connect the second link and disconnect the first link according to the second signal.

[0028] When the electronic device is powered on, the signaler is configured to output a high signal by default, so that the first link can access the first memory. Specifically, the signaler is configured to output a first signal if the electronic device is powered on. In an embodiment, the arbitrary processor is configured to control the basic input / output system to write a second signal in the signaler when the second link in the target board card is connected, so that the signaler outputs the second signal. The arbitrary processor is configured to control the basic input / output system to write the first signal in the signaler when the first link in the target board card is connected, so that the signaler outputs the first signal. In an embodiment, the signaler is configured to output a high signal as the first signal and a low signal as the second signal.

[0029] In order to store the processor identification information corresponding to the target board card in the first memory, the processor connected to the target board card is configured to control the basic input / output system to write the processor identification information corresponding to the target board card in the first memory when the first link in the target board card is connected. In an embodiment, the processor connected to the target board card is configured to control the basic input / output system to write the number and port number of the processor connected to the target board card in the first memory as the processor identification information when the first link in the target board card is connected. For example, if the number of the processor is 000 and the port number is 0001, the processor identification information can be 0000001.

[0030] In an embodiment, the second memory is further configured to store the board card information of the target board card, such as the board card manufacturer, the number, etc.

[0031] In an embodiment, the second memory is configured to construct a physical position table based on the marking information of the slot included in each board card and store the physical position table. The physical position table can refer to Table 1, and the content of Table 1 can be referred to Figure 2 . The physical position table is burned in the second memory.

[0032] Table 1

[0033]

[0034] In an embodiment, any processor is configured to: when the second link in the target board card is connected, control the basic input / output system to read the processor identification information from the first memory and read the marking information of the slot included in the target board card from the second memory; determine the silk screen information of the slot included in the target board card according to the processor identification information and the marking information of the slot included in the target board card. For example, the number 000 of the processor is spliced with the port number 0001 of the processor to obtain the processor identification information 0000001, wherein 000 represents CPU0 and the port number 0001 represents port PE0, so when the marking information of the slot is SLOT0, the silk screen information of the slot can be recorded as: CPU0_PE0_SLOT0. Correspondingly, the processor can record the silk screen information and generate a target log based on the recording content, and display the target log. The processor can splice the processor identification information corresponding to the target board card and the marking information of the slot included in the target board card into the silk screen information.

[0035] After any processor determines the silk screen information of the slot included in the target board card by means of the basic input / output system, the basic input / output system can send it to the management controller connected to the processor, such as the BMC (Baseboard Management Controller), and the management controller records all the silk screen information and generates a target log based on the silk screen information, and displays the target log.

[0036] In an embodiment, any processor is configured to: when the second link in the target board card is connected, control the basic input / output system to read the processor identification information from the first memory and read the marking information of the slot included in the target board card from the second memory; determine the silk screen information of the slot included in the target board card according to the processor identification information and the marking information of the slot included in the target board card. For example, the number 000 of the processor is spliced with the port number 0001 of the processor to obtain the processor identification information 0000001, wherein 000 represents CPU0 and the port number 0001 represents port PE0, so when the marking information of the slot is SLOT0, the silk screen information of the slot can be recorded as: CPU0_PE0_SLOT0. Correspondingly, the processor can record the silk screen information and generate a target log based on the recording content, and display the target log. The processor can splice the processor identification information corresponding to the target board card and the marking information of the slot included in the target board card into the silk screen information. Figure 2

[0037] Table 2

[0038]

[0039] It should be noted that the first connector in any of the board cards is connected to the slot included in the board card, and the slot is used to connect a network card, a disk array or an acceleration card. One slot can be provided with one or more ports for connecting a PCIE device.

[0040] ​It can be seen that in the various board cards, the first memory is used to store the processor identification information corresponding to the board card; the second memory is used to store the marking information of the slot included in each board card, and the first memory and the second memory are gated by the gate in the second link, so that the processor can access the first memory and the second memory through the second connector in each board card and through the second link, thereby confirming the silk screen information of the slot of each board card according to the data stored in the first memory and the second memory, and positioning the slot of each board card and the connected equipment is completed. The scheme does not need to trigger the lights of each slot to flash one by one, and the positioning efficiency of the physical slot can be improved.

[0041] Please refer to Figure 2 , a BMC and two CPUs are arranged on the mainboard, 4 ports of each CPU are connected with 4 MCIO connectors, and each MCIO connector is connected with the MCIO connector of an expansion card (i.e. a board card); the BIOS (Basic Input Output System) is expanded to 8 I2C through the I2C switch, and is connected with 8 I2C connectors on the mainboard, each I2C connector is connected with the I2C connector of an expansion card; in this design, 8 expansion cards can be connected, and the internal structures of the various expansion cards are the same.

[0042] Specifically, each expansion card includes an I2C connector, an MCIO connector, a slot PCIE SLOT, a selector MUX (Multiplexer, which can be referred to as a multiplexer), a signaler IO EXPANDER (which can be referred to as an input-output expander), a second memory BOARD EEPROM (Electrically Erasable Programmable Read-Only Memory, Electrically Erasable Programmable Read-Only Memory), and a first memory silk screen EEPROM. The MUX is used to gate two different I2C signals (MCIO I2C and Header I2C) to one road to the silk screen EEPROM; the silk screen EEPROM is used to store the logic source of the uplink PCIE signal on the expansion card, i.e. the CPU and the CPU port number connected upstream of the expansion card; the IO EXPANDER is used to output the MUX_SEL signal to control the MUX gating function; the BOARD EEPROM is used to store the physical information of the PCIE SLOT in all expansion cards, and these information forms a physical location table.

[0043] The I2C connectors on the mainboard are connected according to Table 1. For example, I2C connector 0 is connected to the expansion card at the position of SLOT0, I2C connector 1 is connected to the expansion card at the position of SLOT1, I2C connector 2 is connected to the expansion card at the position of SLOT2, and so on, thereby forming a physical position table for defining the correspondence between the I2C connectors on the mainboard and the physical positions of the slots, for example, I2C connector 0 corresponds to LOCATION ID 0 and the corresponding physical position is SLOT0.

[0044] The MCIO connectors on the mainboard are connected according to Table 2, which is used to define the CPU port information corresponding to the MCIO connectors on the mainboard, for example, MCIO connector 0 corresponds to CPU ADDR (CPU number) 000 and VPP ADDR (CPU port number) 0001, indicating that the upstream PCIE of MCIO connector 0 comes from CPU0_PE0.

[0045] The PCIE signals and I2C signals (this I2C is called MCIO I2C) from the CPU on the mainboard to the MCIO connectors on the mainboard are connected to the MCIO connectors on the expansion card through a cable. The MCIO connectors on the expansion card connect the PCIE to the PCIE SLOT slot, and the MCIO I2C is connected to the silk-screen EEPROM on the expansion card after being gated by the MUX.

[0046] In addition, the CPU also outputs another I2C (this I2C is called Header I2C), which is expanded into multiple I2Cs on the mainboard after passing through the I2C Switch, and is connected to multiple I2C connectors on the mainboard, and then connected to the I2C connectors on the expansion card through a cable; the Header I2C is connected to the silk-screen EEPROM on the expansion card after being gated by the MUX, and the IOEXPANDER and Board EEPROM placed on the expansion card are also connected to the Header I2C. The gating function of the MUX is controlled by the MUX_SEL signal output by the Header I2C writing the register of the IOEXPANDER, when the MUX_SEL signal is high, the MCIO I2C is connected to the silk-screen EEPROM, and when the MUX_SEL signal is low, the Header I2C is connected to the silk-screen EEPROM.

[0047] Specifically, when the mainboard is powered on, the MUX_SEL signal on the expansion card is high by default, and the MUX connects the MCIO I2C to the silk-screen EEPROM by default.

[0048] The BIOS writes the CPU ADDD and VPP ADDR values ​​corresponding to each MCIO connector on the motherboard to the silk-screen EEPROM on the expansion card through the MCIO I2C according to the contents defined in the logical location table. For example, 0000001 is written to the EEPROM on the expansion card connected to MCIO connector 0, 0000010 is written to the EEPROM on the expansion card connected to MCIO connector 1, and so on.

[0049] The BIOS writes the IO EXPANDER register through the Header I2C to pull the MUX_SEL signal low, controlling the MUX to connect the Header I2C to the silkscreen EEPROM.

[0050] The BIOS switches the I2C switch to channel 0 and reads the information in the silkscreen EEPROM on the expansion card connected to the I2C connector 0 and the physical location table in the board EEPROM through the header I2C. The BIOS switches the I2C switch to channel 1 and reads the information in the silkscreen EEPROM on the expansion card connected to the I2C connector 1 and the physical location table in the board EEPROM through the header I2C. The BIOS switches the I2C switch to channel 2 and reads the information in the silkscreen EEPROM on the expansion card connected to the I2C connector 2 and the physical location table in the board EEPROM through the header I2C. The same applies to other channels.

[0051] If a network card is connected to the expansion card's slot, the BIOS generates a complete silkscreen of the logical and physical locations of the PCIE network card based on the information it reads. For example, the BIOS reads 0000001 from the silkscreen EEPROM on the expansion card connected to I2C connector 0. According to the logical location table recorded in the BIOS, 0000001 represents CPU0_PE0. According to the physical location table in the expansion card's BOARD EEPROM, I2C connector 0 corresponds to Location ID 0 and a fixed physical location of SLOT 0. Therefore, the complete silkscreen of this PCIE network card is CPU0_PE0_SLOT0. The BIOS reads 0010001 from the silkscreen EEPROM on the expansion card connected to I2C connector 2. According to the logical location table recorded in the BIOS, 0010001 represents CPU1_PE0. According to the physical location table in the BOARD EEPROM on the expansion card, the location ID corresponding to I2C connector 2 is 2 and the fixed physical location is SLOT2. Therefore, the complete silkscreen of this PCIE network card is CPU1_PE0_SLOT2.

[0052] The BIOS can also pass the silk screen information to the BMC for logging and display. The BIOS can rely on any processor to run, for example, a processor dedicated to running the BIOS can be provided on the motherboard, or the BIOS can run with other business processors, graphics processors.

[0053] The embodiment can perform adaptive binding of the logical position and the physical position of the PCIE network card, can automatically obtain the PCIE source and the current physical position of a certain network card device, effectively improves the positioning efficiency of the fault network card, and can timely and accurately locate the physical positions of all network cards in a super large scale data center. Since the logical position and the physical position are adaptively bound, different models can use the technical solution of the embodiment even if they are configured differently.

[0054] A data processing method provided by the embodiment of the application will be introduced below, and the data processing method described below can be mutually referred to with other embodiments described herein.

[0055] The embodiment of the application discloses a data processing method, applied to an electronic device, the electronic device comprising: at least one processor and at least one board card; wherein any target board card in the at least one board card comprises: a first connector, a second connector, a gate, a first memory and a second memory; the first connector is connected with the gate through a first link; the second connector is connected with the gate and the second memory through a second link; the gate is further connected with the first memory; the gate is used for: gating the first link or the second link; the first memory is used for: storing processor identification information corresponding to the target board card; the second memory is used for: storing marking information of slots included in each board card; the second connector in each board card is connected with the processor; the first connector and the second connector in each board card are connected with any one processor;

[0056] Referring to Figure 3 The data processing method disclosed by the embodiment of the application comprises:

[0057] S301, after the second link in the target board card is connected, the processor controls the basic input and output system to read the processor identification information corresponding to the target board card from the first memory in the target board card, and reads the marking information of the slots included in the target board card from the second memory.

[0058] S302, the processor determines the silk screen information of the slots included in the target board card according to the processor identification information corresponding to the target board card and the marking information of the slots included in the target board card.

[0059] The embodiment method can be executed by the BIOS. That is, the BIOS relies on any processor to run to execute S301 and S302.

[0060] In one embodiment, the selector includes: a selector and a signaler connected to the selector; the signaler is used to: output a first signal for connecting a first link; or output a second signal for connecting a second link; the selector is used to: connect the first link and disconnect the second link according to the first signal; or connect the second link and disconnect the first link according to the second signal.

[0061] In one embodiment, the signaler is configured to output a first signal when the electronic device is powered on.

[0062] In one embodiment, the arbitrary processor is configured to: when the second link in the target board is connected, control the basic input and output system to write the second signal into the annunciator, so that the annunciator outputs the second signal.

[0063] In one embodiment, any processor is configured to: when the first link in the target board is connected, control the basic input / output system to write the first signal into the annunciator, so that the annunciator outputs the first signal.

[0064] In one embodiment, the signaler is configured to: output a high-bit signal as the first signal; and output a low-bit signal as the second signal.

[0065] In one embodiment, the processor is connected to a plurality of mainboard-side second connectors via an expander, and each mainboard-side second connector is connected to a second connector in a different board.

[0066] In one embodiment, the processor connected to the target board is configured to: when the first link in the target board is connected, control the basic input and output system to write the processor identification information corresponding to the target board into the first memory.

[0067] In one embodiment, the processor connected to the target board is configured to: when the first link in the target board is connected, control the basic input and output system to write the serial number and port number of the processor connected to the target board into the first memory as processor identification information.

[0068] In one embodiment, the second memory is further configured to store the board information of the target board.

[0069] In one embodiment, the second memory is used to: construct a physical location table based on the marking information of the slots included in each board, and store the physical location table.

[0070] In one embodiment, any processor is used to: when the second link in the target board is connected, control the basic input and output system to read the processor identification information from the first memory, and read the marking information of the slot included in the target board from the second memory; determine the silk screen information of the slot included in the target board based on the processor identification information and the marking information.

[0071] In one embodiment, any processor is configured to record silk screen information, generate a target log based on the recorded content, and display the target log.

[0072] In one embodiment, any processor is configured to: combine the processor identification information and the marking information into silk-screen information.

[0073] In one embodiment, any processor is configured to: when the electronic device is powered on, record the processor identification information corresponding to each board and generate a logic position table.

[0074] In one embodiment, the first connector in any board is connected to a slot included in the board, and the slot is used to connect to a network card, a disk array, or an accelerator card.

[0075] Among them, for more specific working processes of each module and unit in this embodiment, reference can be made to the corresponding contents disclosed in the aforementioned embodiments, which will not be repeated here.

[0076] It can be seen that this embodiment provides a data processing device that can adaptively bind the logical location and physical location of a PCIE network card, and can automatically obtain the PCIE source and current physical location of a certain network card device, effectively improving the efficiency of locating faulty network cards.

[0077] The following describes an electronic device provided in an embodiment of the present application. The electronic device described below can be cross-referenced with other embodiments described herein. The electronic device in this embodiment can include various functional modules such as a processor, a board, a gate, a first memory, and a second memory.

[0078] See also Figure 4 As shown, an embodiment of the present application discloses an electronic device, including: a memory 401 for storing a computer program; a processor 402 for executing the computer program to implement the method disclosed in any of the above embodiments.

[0079] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: selecting the first link or the second link.

[0080] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: storing processor identification information corresponding to the target board.

[0081] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: storing the marking information of the slots included in each board.

[0082] In the embodiment, the processor, when executing the computer program stored in the memory, can implement the following steps: after the second link in the target board card is connected, the basic input / output system is controlled to read the processor identification information from the first memory and read the marking information of the slot included in the target board card from the second memory.

[0083] In the embodiment, the processor, when executing the computer program stored in the memory, can implement the following steps: according to the processor identification information and the marking information, the silk screen information of the slot included in the target board card is determined.

[0084] In the embodiment, the processor, when executing the computer program stored in the memory, can implement the following steps: a first signal for connecting the first link is outputted; or a second signal for connecting the second link is outputted.

[0085] In the embodiment, the processor, when executing the computer program stored in the memory, can implement the following steps: according to the first signal, the first link is connected and the second link is disconnected; or according to the second signal, the second link is connected and the first link is disconnected.

[0086] In the embodiment, the processor, when executing the computer program stored in the memory, can implement the following steps: if the electronic device is started, the first signal is outputted.

[0087] In the embodiment, the processor, when executing the computer program stored in the memory, can implement the following steps: after the second link in the target board card is connected, the basic input / output system is controlled to write the second signal in the signal indicator, so that the signal indicator outputs the second signal.

[0088] In the embodiment, the processor, when executing the computer program stored in the memory, can implement the following steps: after the first link in the target board card is connected, the basic input / output system is controlled to write the first signal in the signal indicator, so that the signal indicator outputs the first signal.

[0089] In the embodiment, the processor, when executing the computer program stored in the memory, can implement the following steps: a high-bit signal is outputted as the first signal; and a low-bit signal is outputted as the second signal.

[0090] In the embodiment, the processor, when executing the computer program stored in the memory, can implement the following steps: after the first link in the target board card is connected, the basic input / output system is controlled to write the processor identification information corresponding to the target board card in the first memory.

[0091] In the embodiment, the processor, when executing the computer program stored in the memory, can implement the following steps: when the first link in the target board card is connected, the basic input / output system is controlled to write the number and port number of the processor connected with the target board card in the first memory as the processor identification information.

[0092] In the embodiment, the processor, when executing the computer program stored in the memory, can implement the following steps: the board card information of the target board card is stored.

[0093] In the embodiment, the processor, when executing the computer program stored in the memory, can implement the following steps: a physical position table is constructed based on the marking information of the slot included in each board card, and the physical position table is stored.

[0094] In the embodiment, the processor, when executing the computer program stored in the memory, can implement the following steps: when the second link in the target board card is connected, the basic input / output system is controlled to read the processor identification information from the first memory and read the marking information of the slot included in the target board card from the second memory; the silk screen information of the slot included in the target board card is determined according to the processor identification information and the marking information.

[0095] In the embodiment, the processor, when executing the computer program stored in the memory, can implement the following steps: the silk screen information is recorded, and the target log is generated based on the recording content, and the target log is displayed.

[0096] In the embodiment, the processor, when executing the computer program stored in the memory, can implement the following steps: the processor identification information and the marking information are spliced into the silk screen information.

[0097] In the embodiment, the processor, when executing the computer program stored in the memory, can implement the following steps: when the electronic device is started, the processor identification information corresponding to each board card is recorded, and a logical position table is generated.

[0098] Further, the embodiment of the application further provides an electronic device. Figure 5 The electronic device can be a server as shown in Figure 6 or a terminal as shown in Figure 5 and Figure 6 are structural diagrams of electronic devices according to an example embodiment, and the contents in the diagrams cannot be considered as any limitation on the use range of the application.

[0099] Figure 5A structural schematic diagram of a server is provided in the embodiment. The server can specifically include at least one processor, at least one memory, a power supply, a communication interface, an input / output interface and a communication bus. The memory is configured to store a computer program, the computer program is loaded and executed by the processor to implement the related steps in the data processing disclosed in any of the foregoing embodiments.

[0100] In the embodiment, the power supply is configured to provide working voltage for each hardware device on the server; the communication interface is configured to create a data transmission channel between the server and external devices, and the communication protocol followed by the communication interface is any communication protocol applicable to the technical solution of the present application, which is not limited specifically herein; the input / output interface is configured to obtain external input data or output data to the outside, and the specific interface type can be selected according to the specific application needs, which is not limited specifically herein.

[0101] In addition, the memory as a carrier for resource storage can be a read-only memory, a random access memory, a magnetic disk or an optical disk, etc., and the resources stored thereon include an operating system, a computer program and data, etc., and the storage mode can be temporary storage or permanent storage.

[0102] The operating system is configured to manage and control each hardware device and the computer program on the server, so as to implement the operation and processing of the processor on the data in the memory, and the operating system can be Windows Server, Netware, Unix, Linux, etc. The computer program can further include a computer program for completing other specific work in addition to the computer program for completing the data processing method disclosed in any of the foregoing embodiments. The data can include the developer information of the application program in addition to the data such as the update information of the application program.

[0103] Figure 6 A structural schematic diagram of a terminal is provided in the embodiment, and the terminal can specifically include but is not limited to a smart phone, a tablet computer, a notebook computer or a desktop computer, etc.

[0104] Generally, the terminal in the embodiment includes a processor and a memory.

[0105] The processor may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor may be implemented in at least one of the following hardware forms: a DSP (Digital Signal Processing), an FPGA (Field-Programmable Gate Array), or a PLA (Programmable Logic Array). The processor may also include a main processor and a coprocessor. The main processor is used to process data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing content required to be displayed on the display. In some embodiments, the processor may also include an AI (Artificial Intelligence) processor, which is used to handle computational operations related to machine learning.

[0106] The memory may include one or more computer non-volatile storage media, which may be non-transitory. The memory may also include high-speed random access memory, and non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the memory is used to store at least the following computer program, wherein, after the computer program is loaded and executed by the processor, it can implement the relevant steps in the data processing method performed by the terminal side disclosed in any of the aforementioned embodiments. In addition, the resources stored in the memory may also include an operating system and data, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system may include Windows, Unix, Linux, etc. The data may include but is not limited to update information of the application.

[0107] In some embodiments, the terminal may further include a display screen, an input and output interface, a communication interface, a sensor, a power supply, and a communication bus.

[0108] Those skilled in the art will understand that Figure 6 The structure shown in the figure does not constitute a limitation to the terminal, and may include more or fewer components than shown in the figure.

[0109] A non-volatile storage medium provided in an embodiment of the present application is introduced below. The non-volatile storage medium described below can be referenced with other embodiments described herein.

[0110] A non-volatile storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the data processing method disclosed in the aforementioned embodiment. The non-volatile storage medium is a computer-readable non-volatile storage medium that, as a carrier for resource storage, may be a read-only memory, random access memory, magnetic disk, or optical disk, etc. The resources stored thereon include an operating system, computer program, and data, etc., and the storage method may be temporary or permanent.

[0111] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: selecting the first link or the second link.

[0112] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: storing processor identification information corresponding to the target board.

[0113] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: storing the marking information of the slots included in each board.

[0114] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: after the second link in the target board is connected, the basic input and output system is controlled to read the processor identification information from the first memory, and the marking information of the slot included in the target board is read from the second memory.

[0115] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: determining the silkscreen information of the slots included in the target board according to the processor identification information and the marking information.

[0116] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: outputting a first signal for connecting the first link; or outputting a second signal for connecting the second link.

[0117] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: connecting the first link and disconnecting the second link according to the first signal; or connecting the second link and disconnecting the first link according to the second signal.

[0118] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: if the electronic device is powered on, a first signal is output.

[0119] In the embodiment, the processor executes the computer program stored in the nonvolatile storage medium, and the following steps can be implemented: when the second link in the target board card is connected, the basic input / output system is controlled to write the second signal in the signal indicator, so that the signal indicator outputs the second signal.

[0120] In the embodiment, the processor executes the computer program stored in the nonvolatile storage medium, and the following steps can be implemented: when the first link in the target board card is connected, the basic input / output system is controlled to write the first signal in the signal indicator, so that the signal indicator outputs the first signal.

[0121] In the embodiment, the processor executes the computer program stored in the nonvolatile storage medium, and the following steps can be implemented: the high-bit signal is output as the first signal; and the low-bit signal is output as the second signal.

[0122] In the embodiment, the processor executes the computer program stored in the nonvolatile storage medium, and the following steps can be implemented: when the first link in the target board card is connected, the basic input / output system is controlled to write the processor identification information corresponding to the target board card in the first memory.

[0123] In the embodiment, the processor executes the computer program stored in the nonvolatile storage medium, and the following steps can be implemented: when the first link in the target board card is connected, the basic input / output system is controlled to write the number of the processor connected by the target board card and the port number in the first memory as the processor identification information.

[0124] In the embodiment, the processor executes the computer program stored in the nonvolatile storage medium, and the following steps can be implemented: the board card information of the target board card is stored.

[0125] In the embodiment, the processor executes the computer program stored in the nonvolatile storage medium, and the following steps can be implemented: a physical position table is constructed based on the marking information of the slot included by each board card, and the physical position table is stored.

[0126] In the embodiment, the processor executes the computer program stored in the nonvolatile storage medium, and the following steps can be implemented: when the second link in the target board card is connected, the basic input / output system is controlled to read the processor identification information from the first memory and read the marking information of the slot included by the target board card from the second memory; and the silk screen information of the slot included by the target board card is determined according to the processor identification information and the marking information.

[0127] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: recording silk screen information, generating a target log based on the recorded content, and displaying the target log.

[0128] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: splicing the processor identification information and the marking information into silk-screen information.

[0129] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: when the electronic device is powered on, the processor identification information corresponding to each board is recorded and a logical location table is generated.

[0130] A computer program product provided in an embodiment of the present application is introduced below. The computer program product described below can be referenced with other embodiments described herein.

[0131] A computer program product comprises a computer program / instruction, which implements the steps of the aforementioned data processing method when executed by a processor.

[0132] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium is used to store a computer program, and when the computer program is executed by a processor, the steps in any of the above embodiments are implemented.

[0133] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: selecting the first link or the second link.

[0134] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: storing processor identification information corresponding to the target board.

[0135] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: storing the marking information of the slots included in each board.

[0136] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: after the second link in the target board is connected, the basic input and output system is controlled to read the processor identification information from the first memory, and the marking information of the slot included in the target board is read from the second memory.

[0137] In the embodiment, the processor executes the computer program stored in the nonvolatile storage medium, and the following steps can be implemented: determining the silk screen information of the slot included in the target board according to the processor identification information and the mark information.

[0138] In the embodiment, the processor executes the computer program stored in the nonvolatile storage medium, and the following steps can be implemented: outputting a first signal for connecting the first link; or outputting a second signal for connecting the second link.

[0139] In the embodiment, the processor executes the computer program stored in the nonvolatile storage medium, and the following steps can be implemented: connecting the first link according to the first signal, and disconnecting the second link; or connecting the second link according to the second signal, and disconnecting the first link.

[0140] In the embodiment, the processor executes the computer program stored in the nonvolatile storage medium, and the following steps can be implemented: outputting the first signal if the electronic device is started.

[0141] In the embodiment, the processor executes the computer program stored in the nonvolatile storage medium, and the following steps can be implemented: when the second link in the target board is connected, controlling the basic input / output system to write the second signal in the signal indicator, so that the signal indicator outputs the second signal.

[0142] In the embodiment, the processor executes the computer program stored in the nonvolatile storage medium, and the following steps can be implemented: when the first link in the target board is connected, controlling the basic input / output system to write the first signal in the signal indicator, so that the signal indicator outputs the first signal.

[0143] In the embodiment, the processor executes the computer program stored in the nonvolatile storage medium, and the following steps can be implemented: outputting a high-bit signal as the first signal; and outputting a low-bit signal as the second signal.

[0144] In the embodiment, the processor executes the computer program stored in the nonvolatile storage medium, and the following steps can be implemented: when the first link in the target board is connected, controlling the basic input / output system to write the processor identification information corresponding to the target board in the first memory.

[0145] In the embodiment, the processor executes the computer program stored in the nonvolatile storage medium, and the following steps can be implemented: when the first link in the target board is connected, controlling the basic input / output system to write the number and port number of the processor connected by the target board in the first memory as the processor identification information.

[0146] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: storing the board information of the target board.

[0147] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: constructing a physical location table based on the marking information of the slots included in each board, and storing the physical location table.

[0148] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: when the second link in the target board is connected, the basic input and output system is controlled to read the processor identification information from the first memory, and read the marking information of the slot included in the target board from the second memory; and the silk screen information of the slot included in the target board is determined based on the processor identification information and the marking information.

[0149] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: recording silk screen information, generating a target log based on the recorded content, and displaying the target log.

[0150] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: splicing the processor identification information and the marking information into silk-screen information.

[0151] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: when the electronic device is powered on, the processor identification information corresponding to each board is recorded to generate a logical location table.

[0152] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0153] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, a hard disk, a removable disk, a CD-ROM, or any other form of non-volatile storage medium known in the art.

[0154] The principles and implementation manners of the present application are described by using specific examples in the present application, and the above examples are only used to help understand the method and its core idea of the present application; meanwhile, for the general technical personnel in the art, the specific implementation manners and application ranges will be changed according to the idea of the present application, and the above description should not be understood as the limitation of the present application.

Claims

1. An electronic device, characterized in that: include: at least one processor and at least one board; Wherein, any target board in the at least one board includes: a first connector, a second connector, a gate, a first memory, and a second memory; the first connector is connected to the gate via a first link; the second connector is connected to the gate and the second memory via a second link; the gate is also connected to the first memory; The gate is used to: gate the first link or the second link; The first memory is used to: store processor identification information corresponding to the target board; The second memory is used to: store the marking information of the slots included in each board; Accordingly, the first connector and the second connector in each board are connected to any processor; Wherein, any processor accesses the first memory and the second memory through the second connector in each board and through the second link, and confirms the silkscreen information of the slot of each board according to the data stored in the first memory and the second memory.

2. The electronic device according to claim 1, wherein The gate device includes: a selector and a signal device connected to the selector; The signaler is used to: output a first signal for connecting the first link; or output a second signal for connecting the second link; The selector is configured to: connect the first link and disconnect the second link according to the first signal; or connect the second link and disconnect the first link according to the second signal.

3. The electronic device according to claim 2, wherein: The annunciator is configured to output the first signal when the electronic device is powered on.

4. The electronic device according to claim 2, wherein: Any processor is configured to: when the second link in the target board is connected, control the basic input and output system to write the second signal into the annunciator, so that the annunciator outputs the second signal.

5. The electronic device according to claim 2, wherein: Any processor is configured to: when the first link in the target board is connected, control a basic input / output system to write the first signal into the annunciator, so that the annunciator outputs the first signal.

6. The electronic device according to claim 2, wherein: The signal device is used to: output a high-bit signal as the first signal; and output a low-bit signal as the second signal.

7. The electronic device according to claim 1, wherein: Any processor is connected to multiple mainboard-side second connectors through an expander, and each mainboard-side second connector is connected to a second connector in a different board. Any processor is connected to a plurality of mainboard-side first connectors, and each mainboard-side first connector is respectively connected to a first connector in a different board.

8. The electronic device according to claim 1, wherein: The processor connected to the target board is used for controlling the basic input and output system to write the processor identification information corresponding to the target board into the first memory when the first link in the target board is connected.

9. The electronic device according to claim 8, wherein: The processor connected to the target board is used to: when the first link in the target board is connected, control the basic input and output system to write the number and port number of the processor connected to the target board into the first memory as the processor identification information.

10. The electronic device according to claim 1, wherein The second memory is further used to store the board information of the target board.

11. The electronic device according to claim 1, wherein The second memory is used to construct a physical location table based on the marking information of the slots included in each board, and store the physical location table.

12. The electronic device according to claim 1, wherein Any processor is used to: when the second link in the target board is connected, control the basic input and output system to read the processor identification information from the first memory and read the marking information of the slot included in the target board from the second memory; determine the silk screen information of the slot included in the target board according to the processor identification information and the marking information of the slot included in the target board.

13. The electronic device according to claim 12, wherein: Any processor is used to: record the silk screen information, generate a target log based on the recorded content, and display the target log.

14. The electronic device according to claim 12, wherein: Any processor is used to: splice the processor identification information and the marking information of the slot included in the target board into the silk screen information.

15. The electronic device according to any one of claims 1 to 14, characterized in that: Any processor is used to: when the electronic device is powered on, record the identification information of the processors corresponding to each board and generate a logic position table.

16. The electronic device according to any one of claims 1 to 14, characterized in that: The first connector in any board is connected to a slot included in the board, and the slot is used to connect to a network card, a disk array or an acceleration card.

17. A data processing method, characterized in that: Applied to an electronic device, the electronic device comprising: at least one processor and at least one board; wherein any target board in the at least one board comprises: a first connector, a second connector, a gate, a first memory, and a second memory; the first connector is connected to the gate via a first link; the second connector is connected to the gate and the second memory via a second link; the gate is also connected to the first memory; The gate is used to: gate the first link or the second link; The first memory is used to: store processor identification information corresponding to the target board; The second memory is used to: store the marking information of the slots included in each board; The first connector and the second connector in each board are connected to any processor; Accordingly, the data processing method includes: After the second link in the target board is connected, any processor controls the basic input and output system to read the processor identification information from the first memory and read the marking information of the slot included in the target board from the second memory; and determines the silkscreen information of the slot included in the target board according to the processor identification information and the marking information of the slot included in the target board.

18. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to execute the computer program to implement the method according to claim 17.

19. A non-volatile storage medium, characterized in that: Used to store a computer program, wherein when the computer program is executed by a processor, the method according to claim 17 is implemented.

20. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instructions are executed by a processor, the method of claim 17 is implemented.

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