Clock node calculation method, layout method and wiring method based on density clustering

Abstract

The invention discloses a clock node calculation method, a layout method and a wiring method based on density clustering, which are used for determining the position of a top node of a clock receiver in a chip module, and the specific steps are as follows: firstly, obtaining plane point locations of all clock receiver pins in the chip module; clustering the plane point locations of the pins of the clock receiver by adopting a clustering algorithm to form a plurality of pin clusters, and determining the geometric center of each pin cluster; connecting lines of geometric centers of all the pin clusters to form a relation network diagram, and converging the relation network diagram to points with the total number not larger than 10 under the condition of a set total wiring path length threshold value D by adopting a geometric convergence algorithm based on a graph theory, and determining the points as top layer nodes, wherein the total number of the points is not larger than 10. The layout of the clock nodes is optimized, and the power consumption and delay of the clock network can be reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip design, and in particular relates to a clock node calculation method, a layout method and a wiring method based on density clustering. Background Art

[0002] In chip design, clock nodes are key driver or bifurcation points in the clock tree network. Their layout directly impacts the transmission quality of clock signals (such as latency and skew) and overall chip power consumption. As integrated circuits scale, clock sinks, such as registers, are often distributed in clusters, either regularly or irregularly. Traditional clock node layout methods struggle to efficiently handle this distribution, making timing optimization more challenging. Existing layout methods primarily include single-node long trees, H-trees, fishbone structures, and mesh structures. Single-node long trees directly drive all sinks from the root node, resulting in long paths and numerous bifurcations, leading to high latency and significant RC losses. H-trees and fishbone structures rely on a regular layout and are less adaptable to irregular cluster distributions. Mesh structures drive sinks through a global mesh network. While ensuring signal uniformity, they require a large number of clock buffers and metal routing, leading to high top-level driver pressure and increased power consumption. Furthermore, the early bifurcation points make it difficult to optimize timing using clock reconvergence pessimism elimination (CRPR) techniques. The core problem of these traditional methods is that they cannot perform targeted clustering based on the physical location of the sink, resulting in an unreasonable number of top-level clock nodes (too many or too few) and non-optimal path planning, which in turn causes problems such as excessive clock delay, uncontrolled power consumption, and difficulty in timing convergence. Summary of the Invention

[0003] In order to solve the problems existing in the prior art, the present invention provides a clock node calculation method, layout method and wiring method based on density clustering, which aims to perform top-level layout by obtaining the pin positions of the clock receiver, thereby optimizing the node settings, reducing power consumption and delay.

[0004] The technical solution adopted in the present invention is: In a first aspect, the present invention provides a clock node calculation method based on density clustering, which is used to determine the position of the top-level node of a clock receiver in a chip module. The specific steps are as follows: Step 100: First, obtain the plane point positions of all clock receiver pins in the chip module; Step 200: Then, a clustering algorithm is used to cluster the planar points of the clock receiver pins into a number of pin clusters and the geometric center of each pin cluster is determined; Step 300: Use the Delaunay Triangulation algorithm to triangulate the geometric centers of all pin clusters, connect them to form a relationship network diagram, and then use a geometric convergence algorithm based on graph theory to converge to a total number of points not greater than 10 under the condition of a set total wiring path length threshold D on the relationship network diagram to determine the top-level nodes.

[0005] In combination with the first aspect, the present invention provides a first implementation of the first aspect, wherein the clustering algorithm adopts a density clustering algorithm based on DBSCAN.

[0006] In combination with the first aspect or the first embodiment of the first aspect, the present invention provides a second embodiment of the first aspect. In step 200, when using the clustering algorithm, a distance threshold and a point quantity value are set, and a range is defined according to the distance threshold. When the number of planar points of the clock receiver pins within the range reaches the set point quantity value, it is determined as a pin cluster. Finally, all the points of the clock receiver pins are divided into several pin clusters, and the geometric center is determined based on the planar points of all the clock receiver pins in each pin cluster.

[0007] In combination with the first aspect or the first embodiment of the first aspect, the present invention provides a third embodiment of the first aspect. In step 300, a polygon algorithm is used to connect the geometric centers of the pin clusters to form a relationship network diagram composed of several polygons.

[0008] In combination with the third implementation of the first aspect, the present invention provides a fourth implementation of the first aspect, wherein the polygon is a triangle, and the polygon algorithm adopts a Delaunay triangulation algorithm.

[0009] In combination with the first aspect or the first embodiment of the first aspect, the present invention provides a fifth embodiment of the first aspect, wherein the convergence algorithm includes a minimum spanning tree algorithm and a cutting algorithm. The relationship network graph is first processed by the minimum spanning tree algorithm to obtain a tree graph, and then the tree graph is cut using a weighted cutting algorithm based on graph theory to separate the edges multiple times to form several subtree graphs. Finally, after the number of cuts meets the limited number of top-level nodes, the geometric center point of each subtree graph is used as the top-level node, and the corresponding pin cluster on each subtree graph is classified as the top-level node.

[0010] In combination with the fifth embodiment of the first aspect, the present invention provides a sixth embodiment of the first aspect, wherein the minimum spanning tree algorithm includes Prim algorithm, Kruskal algorithm and Boruvka algorithm. For the same relationship network diagram, corresponding tree diagrams are obtained by each of the three minimum spanning tree algorithms, and the tree diagram with the smallest Euclidean distance among the three tree diagrams is processed using the cutting algorithm.

[0011] In combination with the fifth implementation of the first aspect, the present invention provides a seventh implementation of the first aspect, wherein the cutting algorithm is one or more of the Luke bisection algorithm, the Kernighan-Lin bisection algorithm, the Louvain community discovery algorithm, and the K-path partitioning algorithm.

[0012] In a second aspect, the present invention also provides a layout method, which uses the top-level node, the geometric center of the pin cluster and the clock receiver pin obtained by the above-mentioned clock node calculation method as the layout point position of the clock node of the chip module.

[0013] In a third aspect, the present invention also provides a wiring method, which uses the top-level node, the geometric center of the pin cluster and the clock receiver pin obtained by the above-mentioned clock node calculation method as layout points to connect the wiring downward in sequence from the top-level node.

[0014] The beneficial effects of the present invention are: (1) The present invention can first determine the physical location distribution of the clock receiver through a clustering algorithm and then cluster it into several pin clusters. Then, the geometric center of the pin cluster is used as a hierarchical point for convergence. Finally, the top-level node is converged to within a set threshold by combining graph theory technology. Therefore, compared with the existing clock tree layout method, fewer nodes can be used at the top level. (2) The present invention can perform targeted density clustering based on the physical location of the clock receiver, identify cluster distributions of arbitrary shapes and filter noise through the preferred DBSCAN algorithm, and accurately capture the spatial distribution characteristics of the sink; compared with traditional single-point long tree, H-tree and other structures, it converges the scattered cluster nodes to a reasonable number that can be processed at the top level through the preferred geometric center calculation, Delaunay triangulation and minimum spanning tree construction, avoiding long-distance wiring across regions, shortening the clock signal transmission path from the source, and significantly reducing clock delay; (3) The clock tree bifurcation point constructed by the present invention is located at the back, which can form a longer common path, providing favorable conditions for clock re-convergence pessimism elimination technology. Compared with the problem of the sink bifurcation point being located at the front and the timing optimization space being limited in the Mesh structure, the hierarchical tree structure design enables more clock paths to share common routing in the front section, effectively reducing the pessimistic estimation in static timing analysis, greatly improving the timing convergence efficiency, and providing key support for the timing optimization of high-speed integrated circuits; (4) The present invention does not need to build a complex Mesh clock network and a large number of supporting clock buffers. It avoids the high drive load problem caused by global mesh wiring from the top-level design level. Through the collaboration of the minimum spanning tree and the graph partitioning algorithm, a small number of efficient top-level clock nodes are accurately determined, reducing the scale of the drive circuit and the loss of the metal network. While ensuring the quality of the clock signal, it significantly reduces the dynamic power consumption and static power consumption of the top-level clock network. It is particularly suitable for large-scale chip design that is sensitive to power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 Schematic diagram of several pin clusters obtained by clustering the planar points of all clock receiver pins in a chip module based on the DBSCAN algorithm in an embodiment of the present invention; Figure 2 In the embodiment of the present invention, Figure 1 A schematic diagram of calculating the geometric center of each pin cluster from the pin clusters obtained; Figure 3 In the embodiment of the present invention, Figure 2 Only the schematic diagram of the geometric center point of each pin cluster is retained; Figure 4 This is a relationship network diagram formed by applying the Delaunay triangulation algorithm to the geometric center points of the 113 pin clusters in an embodiment of the present invention; Figure 5 Schematic diagrams of tree diagrams obtained by using the PRIM minimum spanning tree algorithm under the condition of boundary weights for obtaining a relationship network diagram in an embodiment of the present invention; Figure 6 Schematic diagrams of tree diagrams obtained by using the Kruskal minimum spanning tree algorithm under the condition of boundary weights for obtaining a relationship network diagram in an embodiment of the present invention; Figure 7 Schematic diagrams of tree diagrams obtained by using the Boruvka minimum spanning tree algorithm under the condition of boundary weights for obtaining a relationship network diagram in an embodiment of the present invention; Figure 8 Schematic diagram of two subtrees obtained after the first binary division of the obtained tree diagram using the Luke binary division algorithm in an embodiment of the present invention; Figure 9 Schematic diagram of four subtree graphs obtained after the second binary partition using the Luke binary partition algorithm in an embodiment of the present invention; Figure 10 Schematic diagram of eight subtree graphs obtained after the third binary partition using the Luke binary partition algorithm in an embodiment of the present invention; Figure 11 In the embodiment of the present invention, Figure 1A schematic diagram of several top-level nodes finally obtained by the chip module and the pin clusters classified corresponding to each top-level node; Figure 12 is a tree diagram representing the top-level nodes obtained by performing bisection convergence using the Kernighan-Lin bisection algorithm in an embodiment of the present invention; Figure 13 is a dendrogram representing the top-level nodes finally obtained by convergence using the Louvain community discovery algorithm in an embodiment of the present invention; Figure 14 is a tree diagram representing the top-level nodes obtained by converging the K-way partitioning algorithm in the embodiment of the present invention; DETAILED DESCRIPTION

[0016] The present invention will be further explained below with reference to the accompanying drawings and specific embodiments.

[0017] To make the objectives, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Generally, the components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.

[0018] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments in the present application without making any creative efforts shall fall within the scope of protection of the present application.

[0019] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not require further definition or explanation in subsequent drawings.

[0020] In the description of this application, it should be noted that if the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the accompanying drawings, or the orientation or position relationship in which the product of the application is usually placed when in use. It is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it cannot be understood as a limitation on this application. In addition, if the terms "first", "second", etc. appear in the description of this application, they are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0021] Furthermore, the use of terms such as "horizontal" and "vertical" in the description of this application does not necessarily imply that a component must be absolutely horizontal or suspended, but rather that it can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal than "vertical" and does not mean that the structure must be completely horizontal, but rather that it can be slightly tilted.

[0022] It should also be noted that, unless otherwise expressly specified or limited, the terms "disposed," "installed," "connected," and "connected" should be understood broadly. For example, they may refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal connections between two components. A person of ordinary skill in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0023] Example 1: This embodiment discloses a node calculation method for clock receivers of chip modules based on density clustering, wherein the chip modules are not limited in type, and the location information of all clock receivers can be obtained through existing EDA or other types of software design, and a method for planning and convergence based on this information to obtain the top-level node layout.

[0024] Specifically, the steps of the method are as follows: First, the plane point information of all clock receiver pins of the corresponding chip module is obtained, that is, the pin point coordinate data of all clock receivers is obtained in an interface with a coordinate axis.

[0025] Then, by calling the clustering algorithm in the interface, the coordinate data of all pin points are clustered to form several pin clusters, and the coordinate data of all pin points in each pin cluster are determined to determine the geometric center of the pin cluster. The determination methods include calculating the geometric center by the determined pin cluster edge and calculating the average coordinates by the coordinate data of all pin points in the pin cluster.

[0026] Then, the geometric center points of each determined pin cluster are connected in the interface to form a relationship network diagram. Then, a geometric convergence algorithm based on graph theory is used to perform weighted segmentation in the relationship network diagram according to the correlation of each geometric center point to form several sub-graphs. Finally, the number of sub-graphs obtained is determined according to the set threshold of the number of top-level nodes, and the geometric center of each sub-graph is identified as the top-level node in the interface, and all pin clusters covered by each top-level node are associated.

[0027] It should be noted that the calculation method in this embodiment uses multiple steps to achieve multi-level convergence. The first step, the clustering algorithm, performs unified clustering and convergence on the numerous clock receiver pins discretely distributed across the chip module. However, this converged number does not meet the top-level node requirement. If there are too many top-level clock nodes, a large-scale mesh network must be built, relying on a large number of clock buffers. This leads to a surge in top-level power consumption, with a high proportion of buffer dynamic power consumption.

[0028] Therefore, for the pin clusters obtained in the first step of clustering, convergence is required again, but the convergence logic is different from that of the first step. The geometric algorithm of graph segmentation can meet the correlation of each pin cluster. Because the clustering algorithm is used again, the centroid calculation of each cluster will inevitably lose the precise position information of the original Sink, especially when the cluster shape is irregular or the density is uneven. The centroid of subsequent clusters may deviate from the true geometric optimal connection point, resulting in an increase in the physical distance between the top-level node and the Sink cluster to which it belongs, and the global optimal path length cannot be guaranteed, thereby increasing the clock signal transmission delay.

[0029] The image segmentation-based convergence method used in this method can ensure the minimum total distance of inter-cluster connections. However, the Euclidean distance or Manhattan distance metrics that rely on multiple clustering cannot capture the actual wiring constraints in complex layouts, which may lead to a deviation between the theoretical convergence effect and the actual chip implementation, reducing the reliability and universality of the technical solution.

[0030] This embodiment also discloses a layout method for the clock nodes of a chip module, which is optimized in a multi-layer layout manner. The top-level node and the geometric center of the pin cluster obtained by the above method are used as the first-level node and the second-level node respectively, and then the pin point of the clock receiver is used as the third node for layout.

[0031] This embodiment also discloses a clock wiring method for a chip module, which is optimized in a multi-layer layout manner. The top-level node, the geometric center of the pin cluster, and the pin point of the clock receiver obtained by the above-mentioned node calculation method are used as three-layer clock nodes, with the top-level node as the top layer, and then the geometric center point of the pin cluster as the second layer. The geometric center points of the corresponding pin clusters are connected from the top-level node as the first-level line layer, and then the geometric center point of the pin cluster is connected to all the pin points contained in each pin cluster to form a second-level line layer.

[0032] As an implementation method, for the above-mentioned node calculation method, when there are regularly distributed clock receiver pin points in the chip module, the clustering algorithm used is preferably the commonly used K-means clustering algorithm. According to the layout characteristics of the clock receiver pins of the chip module, the number of clusters K value to be obtained and parameters such as the number of iterations are set, and then the pin clusters are obtained as data for subsequent processing.

[0033] As an implementation method, for the above-mentioned node calculation method, the clustering algorithm adopted is preferably a density clustering algorithm based on DBSCAN, and clustering is performed by setting three parameters: eps (distance threshold), minsamples (minimum number of domain points required for core points), and metric (distance measurement method), where the metric adopts Euclidean distance or Manhattan distance.

[0034] Reference Figure 1-Figure 3 ,The figure shows the clustering process of calling the DBSCAN calculation tool in the wiring tool for a certain chip module, Figure 1 The pin locations of the clock receiver are marked with yellow dots in the CK pin density diagram of all areas. Figure 2 In the interface, different pin clusters are obtained by clustering using the DBSCAN density clustering algorithm, and five-pointed stars of different colors are used as the geometric center of each pin cluster. Figure 3 The yellow identification points of the pin cluster are removed, and the identification points with geometric centers are retained for the next stage of calculation.

[0035] In this embodiment, 113 pin clusters are obtained through the DBSCAN density clustering algorithm, and the coordinate information of the geometric center points of the 113 pin clusters are also calculated. For this number of pin clusters, they cannot be directly laid out as top-level nodes, and the convergence method based on geometric figure association in the above calculation method is required to converge.

[0036] As an implementation method, for the several pin clusters and the point information of their geometric centers obtained in the above content, this embodiment uses a polygon algorithm to associate the points of each geometric center, and specifically uses the Thiessen polygon algorithm to obtain a polygon-based relationship network diagram for subsequent processing.

[0037] The polygons are preferably regular quadrilateral meshes, which can be used to divide the plane into regular quadrilateral meshes, or to dynamically generate irregular quadrilaterals based on point distribution, such as by merging adjacent triangles into quadrilaterals using a greedy algorithm. Alternatively, using the Thiessen polygon algorithm, each polygon can be approximated as a quadrilateral, with the vertices or center points of the quadrilaterals serving as connecting nodes to construct a graph structure.

[0038] The polygon is preferably a triangle, and the calculation is performed using the Delaunay triangulation algorithm. Figure 4 , that is, through the Delaunay triangulation algorithm, the 113 pin clusters obtained above are connected to form a relationship network diagram.

[0039] Regarding this step, it's important to note that triangulation isn't an absolutely necessary step for mathematically solving point associations, but it is a key means of efficiently constructing geometric proximity graphs in engineering implementations. Its advantages in sparsity and fidelity are irreplaceable, especially when dealing with large, irregularly distributed points (such as 113 clusters). If the pin clusters are regularly distributed (e.g., in a grid pattern) and are relatively small (e.g., n < 50), methods such as center-of-gravity iteration and hierarchical clustering can be tried. However, for scenarios with arbitrary shapes, the presence of noise, and the need for precise timing optimization, triangulation is currently the optimal solution, as it achieves a balance between geometric accuracy, computational efficiency, and timing optimization through the synergy of multiple algorithms.

[0040] Specifically, it is to avoid directly using a fully connected graph. For example, if 113 points are directly connected to form a relationship network graph without using the polygon association algorithm, the calculation amount will eventually reach more than 6,000 edges. However, through triangulation, the number of edges can be reduced to about 300 edges. The triangulated edges can ensure that the subsequent minimum spanning tree scheme can capture the true geometric proximity, which is also the basis for subsequent processing.

[0041] For the obtained relationship network graph, it is necessary to perform weighted segmentation based on graph theory. As an implementation method, a minimum spanning tree is used to obtain a subtree of the minimum unit in multiple layers to determine the top-level node. In this embodiment, the Prim algorithm, Kruskal algorithm, and Boruvka algorithm are used. For the same relationship network graph, the corresponding dendrogram is obtained through three minimum spanning tree algorithms. The dendrogram with the smallest Euclidean distance among these three dendrograms is processed using the cutting algorithm.

[0042] Reference Figure 5 It is the tree diagram obtained by Prim's algorithm starting from a single point and gradually expanding the minimum edge. Figure 6 The Kruskal algorithm selects edges from small to large according to edge weight, avoiding loops until all points are connected. Figure 7 It is the tree diagram obtained by Boruvka algorithm by expanding multiple subtrees in parallel.

[0043] The solution with the smallest Euclidean distance, that is, the dendrogram obtained by the Kruskal algorithm, is selected for the next step. A dendrogram is a connected, acyclic graph; cutting any edge can split it into two subtrees. Therefore, the cutting problem essentially involves selecting the location and order of cut edges to meet convergence objectives (such as balanced node count, compact physical locations, and minimal path loss). Requirements include that the subtrees must be connected after the cut, and that the weights of the cut edges and the hierarchical convergence are important.

[0044] In this embodiment, the Luke binary algorithm is used to segment the tree diagram. Figure 8 、 Figure 9 and Figure 10 ,The figure shows the three-round segmentation process, the first of which is Figure 8 In the example, the tree diagram is divided into two subtree diagrams, one subtree diagram contains points of 56 pin clusters, and the other subtree diagram contains points of 57 pin clusters.

[0045] Figure 9 The middle is the second round of partitioning and cutting steps, which divides the two subtree graphs into four subtree graphs, which contain points of 29, 27, 29, and 28 pin clusters respectively.

[0046] Figure 10 The third round of partitioning and cutting steps is to divide the four subtree graphs into eight subtree graphs. The eight subtree graphs meet the number of top-level nodes that is initially set to no more than 10. Therefore, the geometric centers of the eight subtree graphs are determined as the top-level nodes. Figure 11 The chip module layout is marked with an X.

[0047] In some other implementations, the Kernighan-Lin bisection algorithm, the Louvain community discovery algorithm, and the K-path partitioning algorithm are used as substitutes for the Luke bisection algorithm to process the dendrogram obtained from the minimum spanning tree.

[0048] Reference Figure 12 The subtree segmentation diagram obtained by using the Kernighan-Lin bisection algorithm is shown in the figure. In this figure, the distribution of different subtrees is displayed on the same tree diagram through different colors. Compared with the Luke bisection algorithm, the points divided by this method are more physically discrete.

[0049] Reference Figure 13 The figure shows the subtree segmentation diagram obtained by the Louvain community discovery algorithm. The figure shows the distribution of different subtrees on the same tree diagram through different colors. The number of subtrees obtained by this method meets the requirements and the degree of discreteness is small.

[0050] Reference Figure 14The figure shows the subtree segmentation diagram obtained by the K-way partitioning algorithm. The figure shows the distribution of different subtrees on the same tree diagram through different colors. The subtree obtained by this method will produce fewer points and has certain deficiencies in equal division compared to the Luke binary algorithm.

[0051] In some other implementations, there are alternatives to the Luke bisection algorithm, such as a node-balanced cutting method. Greedy balanced cutting starts from the root node and recursively selects cutting edges to ensure that the number of nodes in the subtree after cutting is as close to half of the current total. This method is more efficient, but the distribution of the obtained subtrees is highly discrete. Another dynamic programming cutting method treats the tree as a rooted tree and records the "minimum total cutting cost when cutting into m subtrees" for each subtree. The cost is defined as the subtree diameter, delay, etc.

[0052] Other examples include geometrically constrained cutting based on physical locations, such as centroid cutting. This method uses the centroid of the tree as the cut point, removing the node whose number of subtree nodes does not exceed that of the original tree after deleting it. This method then splits the tree into several subtrees. Another example is minimum bounding box cutting, which calculates the minimum bounding box (MBB) for the current subtree and selects a cutting edge that passes through the center of the MBB (such as the midline of the x / y axis) to split the tree into two subtrees.

[0053] The present invention is not limited to the above optional embodiments. Anyone can derive various other forms of products based on the teachings of the present invention. The above specific embodiments should not be construed as limiting the scope of protection of the present invention. The scope of protection of the present invention shall be based on the scope defined in the claims, and the description can be used to interpret the claims.

Claims

1. A clock node calculation method based on density clustering, used to determine the location of the top-level node of a clock receiver in a chip module, characterized by: The specific steps are as follows: Step 100: First, obtain the plane point positions of all clock receiver pins in the chip module; Step 200: Then, a clustering algorithm is used to cluster the planar points of the clock receiver pins into a number of pin clusters and the geometric center of each pin cluster is determined; Step 300: Form a relationship network diagram for the geometric center lines of all pin clusters, and then use a geometric convergence algorithm based on graph theory to converge to a total number of no more than 10 points on the relationship network diagram under the condition of a set total wiring path length threshold D, and determine them as top-level nodes.

2. The clock node calculation method based on density clustering according to claim 1, characterized in that: The clustering algorithm adopts a density clustering algorithm based on DBSCAN.

3. The clock node calculation method based on density clustering according to claim 1 or 2, characterized in that: In step 200, when the clustering algorithm is used, a distance threshold and a point quantity value are set, and a range is defined according to the distance threshold. When the number of planar points of the clock receiver pins within the range reaches the set point quantity value, it is determined as a pin cluster. Finally, all the points of the clock receiver pins are divided into several pin clusters, and the geometric center is determined based on the planar points of all the clock receiver pins in each pin cluster.

4. The clock node calculation method based on density clustering according to claim 1 or 2, characterized in that: In step 300, a polygon algorithm is used to connect the geometric centers of the pin clusters to form a relationship network diagram consisting of several polygons.

5. The clock node calculation method based on density clustering according to claim 4, characterized in that: The polygon is a triangle, and the polygon algorithm adopts the Delaunay triangulation algorithm.

6. The clock node calculation method based on density clustering according to claim 1 or 2, characterized in that: The convergence algorithm includes a minimum spanning tree algorithm and a cutting algorithm. The relationship network graph is first processed by the minimum spanning tree algorithm to obtain a tree graph, and then the tree graph is cut multiple times using a weighted cutting algorithm based on graph theory to separate the edges to form several subtree graphs. Finally, after the number of cuts meets the limited number of top-level nodes, the geometric center point of each subtree graph is used as the top-level node, and the corresponding pin cluster on each subtree graph is classified as the top-level node.

7. The clock node calculation method based on density clustering according to claim 6, characterized in that: The minimum spanning tree algorithm includes Prim algorithm, Kruskal algorithm and Boruvka algorithm. For the same relationship network graph, the corresponding tree graph is obtained by each of the three minimum spanning tree algorithms, and the tree graph with the smallest Euclidean distance among the three tree graphs is processed using the cutting algorithm.

8. The clock node calculation method based on density clustering according to claim 6, characterized in that: The cutting algorithm is one or more of the Luke bisection algorithm, the Kernighan-Lin bisection algorithm, the Louvain community discovery algorithm and the K-path partitioning algorithm.

9. A layout method, characterized in that: The top-level node, the geometric center of the pin cluster, and the clock receiver pin obtained by the clock node calculation method of claim 1 or 2 are used as the layout points of the clock node of the chip module.

10. A wiring method, characterized in that: The top-level node, the geometric center of the pin cluster and the clock receiver pin obtained by the clock node calculation method in claim 1 or 2 are used as layout points to connect downward wiring in sequence from the top-level node.

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