Word line driver layout and memory

Abstract

The embodiment of the invention relates to the technical field of semiconductor layout design, in particular to a word line driver layout and a memory, the word line driver layout comprises a plurality of layout units arranged in a first direction, the first direction is the arrangement direction of word lines, each layout unit is used for layout of a driving transistor, and the first direction is the arrangement direction of the word lines. Each layout unit comprises a device layer which is configured to be provided with a driving transistor corresponding to each word line; the metal wiring layer at least comprises a first wiring layer and a second wiring layer; the first wiring layer is configured to arrange i1 word lines; the second wiring layer is configured to arrange i2 word lines; word lines arranged in the first wiring layer are electrically connected with the corresponding driving transistors; word lines arranged in the second wiring layer are electrically connected with the corresponding driving transistors through conductive structures arranged in the first wiring layer. The word line driver layout provided by the embodiment of the invention is used for increasing the distance between the word lines under the condition that the size of the memory is reduced.

Description

Technical Field

[0001] The disclosed embodiments relate to the technical field of semiconductor layout design, and in particular to a word line driver layout and a memory. Background Art

[0002] Dynamic Random Access Memory (DRAM) is an important type of volatile memory in computer storage systems, and plays the main function of caching data when the computer is working.

[0003] In the advanced complementary metal oxide semiconductor (CMOS) process, DRAM with a single transistor-one capacitor (1T1C) structure has been developing in line with Moore's Law, continuously reducing size and improving performance.

[0004] However, as the size of memory continues to decrease, the spacing between adjacent word lines in the memory continues to shrink, and the parasitic capacitance between word lines increases. In addition, as the spacing between word lines decreases, the size and layout of the transistors driving the word lines are also subject to corresponding restrictions. Summary of the Invention

[0005] The present disclosure provides a word line driver layout and a memory, which lay out word lines based on multiple metal routing layers to increase the spacing between word lines when the memory size is reduced.

[0006] According to a first aspect of an embodiment of the present disclosure, a wordline driver layout is provided, comprising a plurality of layout units arranged in a first direction, where the first direction is the direction in which wordlines are arranged, wherein each layout unit is used to layout a driver transistor and x wordlines, where x is an arbitrary positive integer, and each layout unit comprises: a device layer, configured to arrange the driver transistor corresponding to each wordline; a metal routing layer, located on one side of the device layer in a direction perpendicular to the plane of the device layer, configured to layout the x wordlines; the metal routing layer comprises at least a first routing layer and a second routing layer; the first routing layer is located on one side of the device layer and configured to layout i1 wordlines, where i1 is an arbitrary positive integer less than x; the second routing layer is located on a side of the first routing layer away from the device layer and configured to layout i2 wordlines, where i2 is an arbitrary positive integer less than x; the wordlines arranged in the first routing layer are electrically connected to the corresponding driver transistors; and the wordlines arranged in the second routing layer are electrically connected to the corresponding driver transistors via conductive structures arranged in the first routing layer.

[0007] In some embodiments, the first routing layer and the second routing layer are based on the same material to route the word lines.

[0008] In some embodiments, the material used to lay out the word lines in the first routing layer and the second routing layer includes tungsten.

[0009] In some embodiments, i1>i2.

[0010] In some embodiments, each of the layout units further includes: a first contact through-hole, located between the first routing layer and the device layer; a second contact through-hole, located between the first routing layer and the second routing layer; the conductive structure in the first routing layer includes at least: i2 first conductive structures; the word lines arranged in the first routing layer are electrically connected to the corresponding driving transistors in the device layer through the corresponding first contact through-holes; the word lines arranged in the second routing layer are electrically connected to the corresponding first conductive structures through the corresponding second contact through-holes, and each of the first conductive structures is electrically connected to the corresponding driving transistors in the device layer through the corresponding first contact through-holes.

[0011] In some embodiments, the metal routing layer also includes: a third routing layer, the third routing layer is located on the side of the second routing layer away from the first routing layer, and is configured to lay out i3 word lines, where i3 is any positive integer less than x; each of the layout units also includes: a third contact via, located between the second routing layer and the third routing layer; the conductive structure in the first routing layer also includes: i3 second conductive structures; the second routing layer also includes: i3 third conductive structures; the word lines laid out in the third routing layer are electrically connected to the corresponding third conductive structures through the corresponding third contact vias, each of the third conductive structures is electrically connected to the corresponding second conductive structure through the corresponding second contact via, and each of the second conductive structures is electrically connected to the corresponding driving transistor in the device layer through the corresponding first contact via.

[0012] In some embodiments, the driving transistor includes a first N-type transistor, a P-type transistor, and a second N-type transistor; wherein the first N-type transistor and the P-type transistor are controlled based on a common driving signal, and the second N-type transistor is controlled based on an independent driving signal; in the plane where the device layer is located and in the second direction, the device layer includes a first N region and a P region, and the second direction is the extension direction of the word line; in the plane where the device layer is located and in the first direction, the first N region includes a first gate and a second gate; the first gate serves as the gate of the first N-type transistor, and the second gate serves as the gate of the second N-type transistor, the first gate extends in the second direction, and forms a third gate in the P region, and the third gate serves as the gate of the P-type transistor.

[0013] In some embodiments, in the plane where the device layer is located and in the second direction, the device layer further includes a second N region, and the second N region is located on a side of the P region away from the first N region; in the plane where the device layer is located and in the first direction, the second N region includes a fourth gate and a fifth gate, the fourth gate serves as the gate of the first N-type transistor, and the fifth gate serves as the gate of the second N-type transistor; the third gate extends in the second direction and forms the fourth gate in the second N region.

[0014] In some embodiments, the third gate includes: a first sub-gate extending in the second direction, a second sub-gate extending in the first direction, and a third sub-gate extending in the second direction; the first gate extends in the second direction and forms the first sub-gate in the P region; the third sub-gate extends in the second direction and forms the fourth gate in the second N region; in the second direction, the first sub-gate and the third sub-gate are located on opposite sides of the second sub-gate, and the second sub-gate is configured to electrically connect the first sub-gate and the third sub-gate; the extension line of the first sub-gate is parallel to the extension line of the third sub-gate, and in the first direction, the second gate and the fifth gate are located on opposite sides of the third gate.

[0015] In some embodiments, the plurality of layout units include: first layout units and second layout units that are alternately arranged; in the first direction, the second layout units are mirror-symmetrical units of the first layout units.

[0016] In some embodiments, in the first direction, adjacent first layout units and second layout units constitute a layout group, and in the layout group, the first gate in the first layout unit and the first gate in the second layout unit are adjacently arranged.

[0017] In some embodiments, for the first layout unit in the same layout group, in the first direction, the side close to the second layout unit is defined as the first side, and the side away from the second layout unit is defined as the second side; in the first N region, the first side active area corresponding to the first gate is used to receive a first control signal, and the second side active area corresponding to the first gate and the first side active area corresponding to the second gate are shared to connect to the corresponding word line; in the P region, the first side active area corresponding to the first sub-gate is used to receive a second control signal, and the second side active area corresponding to the first sub-gate is connected to the corresponding word line; the first side active area corresponding to the third sub-gate is connected to the corresponding word line, and the second side active area corresponding to the third sub-gate is used to receive a third control signal; in the second N region, the second side active area corresponding to the fourth gate is used to receive a fourth control signal, and the first side active area corresponding to the fourth gate and the second side active area corresponding to the fifth gate are shared to connect to the corresponding word line.

[0018] In some embodiments, the first side active region corresponding to the first gate in the first layout unit and the second layout unit is shared; the first side active region corresponding to the first sub-gate in the first layout unit and the second layout unit is shared.

[0019] In some embodiments, the second gate in the first layout unit is electrically connected to the second gate in the second layout unit in the adjacent layout group through a first connecting gate, and the second side active area of ​​the second gate in the first layout unit and the second side active area of ​​the second gate in the second layout unit in the adjacent layout group are shared to receive a fifth control signal; the fifth gate in the first layout unit in the same layout group is electrically connected to the fifth gate in the second layout unit through a second connecting gate, and the second side active area of ​​the fifth gate in the first layout unit and the second side active area of ​​the fifth gate in the second layout unit are shared to receive a sixth control signal.

[0020] In some embodiments, the second gate in the first layout unit and the second gate in the second layout unit in the adjacent layout group are a first common gate structure; the fifth gate in the first layout unit in the same layout group and the fifth gate in the second layout unit are a second common gate structure.

[0021] In some embodiments, x=4, i1=3, i2=1.

[0022] In some embodiments, the x word lines include a first word line, a second word line, a third word line, and a fourth word line, wherein the first word line, the second word line, and the third word line are arranged in a first wiring layer, and the fourth word line is arranged in a second wiring layer; in the second direction, the first N region includes adjacent first and second regions, the first P region includes adjacent third, fourth, fifth, and sixth regions, the third region is adjacent to the second region, the second region includes adjacent seventh and eighth regions, the seventh region is adjacent to the sixth region; in the first region, the second side active region of the first gate is connected to the first side active region of the second gate the first word line; in the second region, the second side active region of the first gate and the first side active region of the second gate are connected to the second word line; in the third region, the second side active region of the first sub-gate is connected to the first word line; in the fourth region, the second side active region of the first sub-gate is connected to the fourth word line; in the fifth region, the first side active region of the third sub-gate is connected to the second word line; in the sixth region, the first side active region of the third sub-gate is connected to the third word line; in the seventh region, the first side active region of the fourth gate is connected to the fourth word line; and in the eighth region, the first side active region of the fourth gate is connected to the third word line.

[0023] A second aspect of the embodiments of the present disclosure further provides a memory, the layout of the memory including the word line driver layout provided by the first aspect.

[0024] The technical solution provided by the embodiments of the present disclosure has at least the following advantages: by arranging word lines on different layers, the spacing between word lines is increased compared to arranging all word lines on the same layer, thereby avoiding the reduction in word line spacing that introduces larger parasitic capacitance affecting the performance of the memory; in addition, after increasing the word line spacing, the size of the transistors used in the word line driver is also increased, thereby improving the reliability of the device, reducing the process difficulty and improving the product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0026] Figure 1 A schematic diagram of the structure of the device layer and metal wiring layer in a memory provided in one embodiment of the present disclosure;

[0027] Figure 2 A schematic diagram of the structure of each layout unit in the device layer and metal routing layer provided in an embodiment of the present disclosure;

[0028] Figure 3 A schematic diagram of the layout structure of multiple layout units in a word line driver layout provided by an embodiment of the present disclosure;

[0029] Figure 4 A schematic diagram of a circuit structure of a word line driver corresponding to a layout unit provided in one embodiment of the present disclosure;

[0030] Figure 5 A schematic diagram of the layout structure of a first device layer and a schematic diagram of the layout structure of a corresponding metal routing layer provided in an embodiment of the present disclosure;

[0031] Figure 6 A schematic diagram of the layout structure of gate structures in two device layers provided in one embodiment of the present disclosure;

[0032] Figure 7 A schematic diagram of the layout structure of a second device layer provided in an embodiment of the present disclosure;

[0033] Figure 8 A schematic diagram of the layout structure of a third device layer provided in an embodiment of the present disclosure;

[0034] Figure 9 A schematic diagram of the layout structure of multiple layout groups in a word line driver layout provided in an embodiment of the present disclosure;

[0035] Figure 10 A schematic diagram of a circuit structure of two word line drivers corresponding to a layout group based on a 2D5T design according to an embodiment of the present disclosure;

[0036] Figure 11 An embodiment of the present disclosure provides Figure 10 A schematic diagram of the layout structure of the device layer of a layout group in the example;

[0037] Figure 12 A schematic diagram of a circuit structure of two word line drivers corresponding to a layout group based on a 3T design according to an embodiment of the present disclosure;

[0038] Figure 13 An embodiment of the present disclosure provides Figure 12 Schematic diagram of the device layer layout structure of a layout group in the example. DETAILED DESCRIPTION

[0039] In the description of the embodiments of the present disclosure, technical terms such as "first" and "second" are used solely to distinguish between different objects and should not be understood to indicate or imply relative importance or to implicitly specify the quantity, specific order, or primary and secondary relationship of the technical features indicated. In the description of the embodiments of the present disclosure, "plurality" means more than two, unless otherwise specifically defined.

[0040] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present disclosure. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0041] In the description of the embodiments of the present disclosure, the term "and / or" is merely a description of an association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B can represent the following three situations: A exists, A and B exist at the same time, and B exists. In addition, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0042] In the description of the embodiments of the present disclosure, the term "multiple" refers to more than two (including two). Similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple pieces" refers to more than two pieces (including two pieces).

[0043] In the description of the embodiments of the present disclosure, the technical terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore should not be understood as limiting the embodiments of the present disclosure.

[0044] In the description of the embodiments of the present disclosure, unless otherwise expressly specified or limited, technical terms such as "installed," "connected," "connected," and "fixed" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integration; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and they can refer to internal connectivity between two components or interaction between two components. Those skilled in the art can understand the specific meanings of the above terms in the embodiments of the present disclosure based on specific circumstances.

[0045] In the accompanying drawings corresponding to the embodiments of the present disclosure, the thickness and area of ​​the layers are exaggerated for better understanding and ease of description. When describing a component (such as a layer, film, region or substrate) on another component or on the surface of another component, the component can be "directly" located on the surface of the other component, or a third component can be present between the two components. Conversely, when describing a component on the surface of another component or when another component is formed or provided on the surface of a component, it means that there is no third component between the two components. In addition, when describing a component as being "substantially" formed on another component, it means that the component is not formed on the entire surface (or front surface) of the other component, nor is it formed on a partial edge of the entire surface.

[0046] In the description of the embodiments of the present disclosure, when a component is referred to as "including" another component, unless otherwise specified, other components are not excluded, and other components may be further included. In addition, when a component such as a layer, film, region, or plate is referred to as being "on / located on" another component, it can be "directly on" the other component (i.e., located on the surface of the other component with no other components between them), or another component can be present between them. In addition, when a component such as a layer, film, region, or plate is "directly on" another component, or when a component such as a layer, film, region, or plate is located on the surface of another component, it means that no other components are located between them.

[0047] The terms used herein in the description of the various embodiments are intended only to describe the specific embodiments and are not intended to be limiting. As used in the description of the various embodiments and the appended claims, "the component" is intended to include the plural form unless the context clearly indicates otherwise. A component includes a layer, film, region, or plate.

[0048] As can be seen from the background technology, as the size of memory continues to decrease, the spacing between adjacent word lines in the memory continues to shrink, and the parasitic capacitance between word lines increases; in addition, as the spacing between word lines decreases, the size and layout of the transistors driving the word lines are also subject to corresponding restrictions.

[0049] An embodiment of the present disclosure provides a word line driver layout, comprising a plurality of layout units arranged in a first direction, where the first direction is the direction in which the word lines are arranged, wherein each layout unit is used to layout a driver transistor and x word lines, where x is an arbitrary positive integer, and each layout unit comprises: a device layer, configured to arrange a driver transistor corresponding to each word line; a metal routing layer, located on one side of the device layer in a direction perpendicular to the plane where the device layer is located, and configured to layout x word lines; the metal routing layer comprises at least a first routing layer and a second routing layer; the first routing layer is located on one side of the device layer and configured to layout i1 word lines, where i1 is an arbitrary positive integer less than x; the second routing layer is located on a side of the first routing layer away from the device layer and configured to layout i2 word lines, where i2 is an arbitrary positive integer less than x; the word lines arranged in the first routing layer are electrically connected to the corresponding driver transistors; and the word lines arranged in the second routing layer are electrically connected to the corresponding driver transistors via conductive structures arranged in the first routing layer.

[0050] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0051] refer to Figures 1 to 3 ,in, Figure 1 A schematic diagram of the structure of the device layer and metal wiring layer in the memory provided in some embodiments, Figure 2 A schematic diagram of the structure of each layout unit in the device layer and the metal routing layer provided in some embodiments, Figure 3 A schematic diagram of the layout structure of multiple layout units in a word line driver layout provided in some embodiments.

[0052] The wordline driver layout provided in the embodiment of the present disclosure is used to form a wordline driver (Wordline Driver), which includes multiple sub-wordline drivers (Sub-Wordline Driver, SWD), each of which includes multiple wordlines (Wordline, WL) and multiple driver transistors driving the corresponding wordlines.

[0053] refer to Figure 2 and Figure 3 The word line driver layout 100 provided by the embodiment of the present disclosure includes a plurality of layout units 200 , wherein each layout unit 200 is used to form a corresponding sub-word line driver.

[0054] The plurality of layout units 200 are arranged in a first direction x, i.e., the plurality of layout units 200 are spaced apart in the first direction x, where the first direction x is the direction in which the word lines are arranged. It should be noted that the subsequent description of the embodiments of this disclosure also involves a second direction y, which is the direction in which the word lines extend. The second direction y can also be considered the direction in which the word line driver layout 100 or the layout units 200 extend.

[0055] refer to Figure 1 The word line driver layout 100 includes a device layer 101 and a metal wiring layer 102 , wherein the device layer 101 is used to form a driver transistor, and the metal wiring layer 102 is used to lay out word lines.

[0056] refer to Figure 2 , for each layout unit 200, each layout unit 200 is used to layout a driving transistor and x word lines, where x is any positive integer. Figure 2 In the example, each layout unit 200 is used to lay out four word lines (ie, x=4), which is only used to exemplify the word line driver layout 100 provided in the embodiment of the present disclosure and does not constitute a limitation to the embodiment of the present disclosure.

[0057] refer to Figure 1 and Figure 2 The device layer 101 is configured to set a driving transistor corresponding to each word line; the metal wiring layer 102 is located on one side of the device layer 101 in the direction z perpendicular to the plane where the device layer 101 is located, and the metal wiring layer 102 is configured to lay out x word lines.

[0058] In some embodiments, the metal routing layer 102 includes a first routing layer 110 and a second routing layer 120. The first routing layer 110 is located on one side of the device layer 101, and the second routing layer 120 is located on a side of the first routing layer 110 away from the device layer 101. The first routing layer 110 is configured to route i1 word lines, where i1 is any positive integer less than x, and the second routing layer 120 is configured to route i2 word lines, where i2 is any positive integer less than x.

[0059] The word lines arranged in the first wiring layer 110 are electrically connected to corresponding driving transistors, and the word lines arranged in the second wiring layer 120 are electrically connected to corresponding driving transistors through conductive structures provided in the first wiring layer 110 .

[0060] It should be noted that in Figure 2 In the example, x=4, i1=3, i2=1, that is, the word line driver formed by each layout unit 200 is used to layout 4 word lines, wherein 3 word lines are laid out in the first wiring layer 110 and 1 word line is laid out in the second wiring layer 120.

[0061] Based on the above description, it can be seen that for the word line driver layout 100 provided in the embodiment of the present disclosure, by laying out the word lines on different layers, the spacing between the word lines is increased compared to laying out all the word lines on the same layer, thereby avoiding the introduction of larger parasitic capacitance due to the reduction in the word line spacing, thereby optimizing the performance of the memory; in addition, after increasing the word line spacing, the size of the transistors used in the word line driver is also increased, thereby improving the reliability of the device, reducing the process difficulty and improving the product yield.

[0062] Regarding the conductive structures in the memory, in some embodiments, each layout unit 200 further includes: a first contact via located between the first routing layer 110 and the device layer 101; and a second contact via located between the first routing layer 110 and the second routing layer 120. The conductive structures in the first routing layer 110 include at least i2 first conductive structures. The word lines arranged in the first routing layer 110 are electrically connected to the corresponding driver transistors in the device layer 101 through corresponding first contact vias. The word lines arranged in the second routing layer 120 are electrically connected to the corresponding first conductive structures through corresponding second contact vias. Each first conductive structure is electrically connected to the corresponding driver transistor in the device layer 101 through the corresponding first contact via.

[0063] It should be noted that Figure 1 In the example, the inclusion of the first routing layer 110 and the second routing layer 120 in the metal routing layer 102 does not constitute a limitation of the embodiments of the present disclosure. In other embodiments, the metal routing layer 102 may further include a third routing layer, a fourth routing layer, etc. that continue to be stacked on the second routing layer 120, so as to lay out x word lines through more layers of routing layers to further increase the spacing between word lines. In some embodiments, the metal routing layer 102 further includes: a third routing layer (not shown), the third routing layer being located on a side of the second routing layer 120 away from the first routing layer 110, the third routing layer being configured to lay out i3 word lines, where i3 is any positive integer less than x.

[0064] Correspondingly, each layout unit 200 also includes: a third contact through-hole, located between the second routing layer 120 and the third routing layer; the conductive structure in the first routing layer 110 also includes i3 second conductive structures, and the second routing layer 120 also includes i3 third conductive structures; the word lines arranged in the third routing layer are electrically connected to the corresponding third conductive structures through the corresponding third contact through-holes, each third conductive structure is electrically connected to the corresponding second conductive structure through the corresponding second contact through-hole, and each second conductive structure is electrically connected to the corresponding driving transistor in the device layer 101 through the corresponding first contact through-hole.

[0065] It should be noted that Figure 2The relationship i1>i2 in the example does not constitute a limitation on the embodiment of the present disclosure. The core of the embodiment of the present disclosure is to lay out the x word lines required for the word line driver in different layers. As for the number of word lines laid out in each layer, the embodiment of the present disclosure does not limit it. In an example, if the word line driver corresponding to each layout unit 200 needs to lay out 4 word lines, it can be set as follows Figure 2 While i1 = 3 and i2 = 1, i1 = 2 and i2 = 2, or i1 = 1 and i2 = 3, can also be set. In some embodiments, i1 > i2. That is, the first routing layer 110, which is closer to the device layer 101, is used to route more word lines, while the second routing layer 120, which is farther away from the device layer 101, is used to route fewer word lines. This reduces the number of conductive structures in the first routing layer 110, thereby simplifying the memory layout.

[0066] In some embodiments, the first routing layer 110 and the second routing layer 120 are based on the same material to route word lines.

[0067] In some embodiments, the material of the first wiring layer 110 and the second wiring layer 120 for routing word lines includes tungsten.

[0068] Specifically, although the first routing layer 110 and the second routing layer 120 are different routing layers for laying out word lines, the first routing layer 110 and the second routing layer 120 are based on the same material for laying out word lines, that is, the first routing layer 110 and the second routing layer 120 both belong to the zeroth metal layer M0 (Metal 0) used for laying out word lines in the memory.

[0069] It should be noted that, in addition to laying out word lines, the zeroth metal layer M0 (Metal 0) is also used to lay out the wiring required for the normal operation of other memories. In addition, in addition to the bottom metal layer M0, the metal layers in the memory also include other metal layers, such as the first metal layer M1 (Metal 1), the second metal layer M2 (Metal 2), etc., wherein the material used to lay out the metal lines of the first metal layer M1 (Metal 1) and the second metal layer M2 (Metal2) includes copper. The second routing layer 120 is set based on the zeroth metal layer M0 to avoid the second routing layer 120 having to cross more layers to be electrically connected to the driving transistor set in the device layer 101, thereby simplifying the layout of the memory. In addition, the first routing layer and the second routing layer are both set using the zeroth metal layer M0, that is, two routing layers are set for the metal layer of the same material to lay out the word lines, which facilitates connection, simplifies the process difficulty, and increases reliability.

[0070] The following embodiments of the present disclosure are described by taking each sub-word line driver driving four word lines as an example, that is, x=4 (the four word lines are WL <0> 、WL <1> 、WL <2> and WL <3> ). refer to Figure 4 , Figure 4 A schematic diagram of a circuit structure of a word line driver corresponding to a layout unit is provided for some embodiments. In some embodiments, the driver transistor includes a first N-type transistor, a P-type transistor, and a second N-type transistor; wherein the first N-type transistor and the P-type transistor are controlled based on a common drive signal K1, and the first N-type transistors and the P-type transistors corresponding to different word lines are controlled based on the same common drive signal K1; the second N-type transistor is controlled based on an independent drive signal, and the second N-type transistors corresponding to different word lines are controlled based on different independent drive signals (WL <0> The corresponding independent driving signal is K <0> , WL <1> The corresponding independent driving signal is K <1> , WL <2> The corresponding independent driving signal is K <2> , WL <3> The corresponding independent driving signal is K <3> ).

[0071] Combine Figure 4 And refer to Figures 5 to 8 In the plane where the device layer 101 is located and in the second direction y, the device layer includes a first N region 301 and a P region 303; in the plane where the device layer 101 is located and in the first direction x, the first N region includes a first gate and a second gate, the first gate serves as the gate of the first N-type transistor, the second gate serves as the gate of the second N-type transistor, the first gate extends in the second direction y, and forms a third gate in the P region, the third gate serves as the gate of the P-type transistor.

[0072] For the first N-type transistor, the first terminal of the first N-type transistor is used to receive the first signal, and the second terminal is connected to the corresponding word line; in some embodiments, the first terminal of the first N-type transistor is connected to a negative voltage power supply to provide the first signal based on the negative voltage power supply.

[0073] For the second N-type transistor, the first terminal of the second N-type transistor is used to receive the second signal, and the second terminal is connected to the corresponding word line; in some embodiments, the second terminal of the second N-type transistor is connected to a negative voltage power supply to provide the second signal based on the negative voltage power supply.

[0074] For a P-type transistor, the first terminal of the P-type transistor is used to receive the third signal, and the second terminal is connected to the corresponding word line; in some embodiments, the second terminal of the P-type transistor is connected to a positive voltage power supply to provide a third signal based on the positive voltage power supply (the third signal corresponding to different word lines is FXT <0> 、FXT <1> 、FXT <2> and FXT <3> ).

[0075] It should be noted that the negative voltage power supply providing the first signal and the negative voltage power supply providing the second signal may be the same negative voltage power supply Vkk, or may be different negative voltage power supplies.

[0076] In some embodiments, in the plane where the device layer 101 is located and in the second direction, the device layer 101 also includes a second N region 302, and the second N region 302 is located on the side of the P region 303 away from the first N region 301; in the plane where the device layer 101 is located and in the first direction, the second N region 303 includes a fourth gate and a fifth gate, the fourth gate serves as the gate of the first N-type transistor, the fifth gate serves as the gate of the second N-type transistor, and the third gate extends in the second direction y, and forms a fourth gate in the second N region.

[0077] It should be noted that the P region 303 can also be configured as two different regions similar to the first N region 301 and the second N region 302. In this case, the first terminals of the corresponding P-type transistors are used to receive the third signal and the sixth signal, respectively. The positive voltage power supply providing the third signal and the positive voltage power supply providing the sixth signal can be the same positive voltage power supply or different positive voltage power supplies.

[0078] In some embodiments, reference Figure 5 , Figure 5 The following is a schematic diagram of the layout structure of the first device layer and the corresponding metal wiring layer provided in an embodiment of the present disclosure. Figure 5 It includes a schematic diagram of the layout structure of the device layer 101, and a schematic diagram of the layout structure of the first routing layer 110 and the second routing layer 120 corresponding to the layout structure of the device layer 101. It should be noted that, Figure 5 In the example, the dot-filled boxes are used to represent the positions of the first contact holes between the first wiring layer 110 and the device layer 101 , and the black dots are used to represent the positions of the second contact holes between the first wiring layer 110 and the second wiring layer 120 .

[0079] WL <0> Arranged on the first wiring layer 110, WL <0> The corresponding first N-type transistor is set in the first N region 301. The first terminal is interconnected to the first wiring layer 110 based on the first contact through hole, and then interconnected to the second wiring layer 120 based on the second contact through hole, and then connected to other metal layers of the memory to obtain the first signal. The second terminal is connected to the WL in the first wiring layer 110 based on the first contact through hole. <0> ;WL <0> The corresponding second N-type transistor is set in the first N region 301. The first terminal is interconnected to the first wiring layer 110 based on the first contact through hole, and then interconnected to the second wiring layer 120 based on the second contact through hole, and then connected to other metal layers of the memory to obtain the second signal. The second terminal is shared with the second terminal of the first N-type transistor; WL <0> The corresponding P-type transistor is set in the P area 303. The first terminal is interconnected to the first wiring layer 110 based on the first contact through hole, and then interconnected to the second wiring layer 120 based on the second contact through hole, and then connected to other metal layers of the memory to obtain the third signal FXT <0> The second terminal is connected to the WL in the first wiring layer 110 based on the first contact hole. <0> Since the P-type transistor and the first N-type transistor are controlled based on the same common driving signal K1, that is, the gates of the P-type transistor and the first N-type transistor are shared, that is, the first gate corresponding to the first N-type transistor is extended in the second direction y to form a third gate corresponding to the P-type transistor in the P region 303.

[0080] WL <1> Arranged on the first wiring layer 110, WL <1> The corresponding first N-type transistor is set in the first N region 301. The first terminal is interconnected to the first wiring layer 110 based on the first contact through hole, and then interconnected to the second wiring layer 120 based on the second contact through hole, and then connected to other metal layers of the memory to obtain the first signal. The second terminal is connected to the WL in the first wiring layer 110 based on the first contact through hole. <1> ;WL <1> The corresponding second N-type transistor is set in the first N region 301. The first terminal is interconnected to the first wiring layer 110 based on the first contact through hole, and then interconnected to the second wiring layer 120 based on the second contact through hole, and then connected to other metal layers of the memory to obtain the second signal. The second terminal is shared with the second terminal of the first N-type transistor; WL <1> The corresponding P-type transistor is set in the P area 303. The first terminal is interconnected to the first wiring layer 110 based on the first contact through hole, and then interconnected to the second wiring layer 120 based on the second contact through hole, and then connected to other metal layers of the memory to obtain the third signal FXT <1> The second terminal is connected to the WL in the first wiring layer 110 based on the first contact hole. <1> Since the P-type transistor and the first N-type transistor are controlled based on the same common driving signal K1, that is, the gates of the P-type transistor and the first N-type transistor are shared, that is, the first gate corresponding to the first N-type transistor is extended in the second direction y to form a third gate corresponding to the P-type transistor in the P region 303.

[0081] WL <2> Arranged on the first wiring layer 110, WL <2> The corresponding first N-type transistor is set in the second N region 302. The first terminal is interconnected to the first wiring layer 110 based on the first contact through hole, and then interconnected to the second wiring layer 120 based on the second contact through hole, and then connected to other metal layers of the memory to obtain the first signal. The second terminal is connected to the WL in the first wiring layer 110 based on the first contact through hole. <2> ;WL <2> The corresponding second N-type transistor is set in the second N region 302. The first terminal is interconnected to the first wiring layer 110 based on the first contact through hole, and then interconnected to the second wiring layer 120 based on the second contact through hole, and then connected to other metal layers of the memory to obtain the second signal. The second terminal is shared with the second terminal of the first N-type transistor; WL <2> The corresponding P-type transistor is set in the P area 303. The first terminal is interconnected to the first wiring layer 110 based on the first contact through hole, and then interconnected to the second wiring layer 120 based on the second contact through hole, and then connected to other metal layers of the memory to obtain the third signal FXT <2> The second terminal is connected to the WL in the first wiring layer 110 based on the first contact hole. <2> Since the P-type transistor and the first N-type transistor are controlled based on the same common driving signal K1, that is, the gates of the P-type transistor and the first N-type transistor are shared, the third gate corresponding to the P-type transistor is extended in the second direction y to form the fourth gate corresponding to the first N-type transistor in the second N region 302.

[0082] WL <3> Arranged on the second wiring layer 120, WL <3> The corresponding first N-type transistor is set in the second N region 302. The first terminal is interconnected to the first wiring layer 110 based on the first contact through hole, and then interconnected to the second wiring layer 120 based on the second contact through hole, and then connected to other metal layers of the memory to obtain the first signal. The second terminal is interconnected to the first wiring layer 110 based on the first contact through hole, and then connected to the WL in the second wiring layer 120 through the second contact through hole. <3> ;WL <3> The corresponding second N-type transistor is set in the second N region 302. The first terminal is interconnected to the first wiring layer 110 based on the first contact through hole, and then interconnected to the second wiring layer 120 based on the second contact through hole, and then connected to other metal layers of the memory to obtain the second signal. The second terminal is shared with the second terminal of the first N-type transistor; WL <3> The corresponding P-type transistor is set in the P area 303. The first terminal is interconnected to the first wiring layer 110 based on the first contact through hole, and then interconnected to the second wiring layer 120 based on the second contact through hole, and then connected to other metal layers of the memory to obtain the third signal FXT <3> The second terminal is interconnected to the first wiring layer 110 based on the first contact via, and then connected to the WL in the second wiring layer 120 through the second contact via. <3> Since the P-type transistor and the first N-type transistor are controlled based on the same common driving signal K1, that is, the gates of the P-type transistor and the first N-type transistor are shared, the third gate corresponding to the P-type transistor is extended in the second direction y to form the fourth gate corresponding to the first N-type transistor in the second N region 302.

[0083] Figure 6 Schematic diagram of the layout structure of the gate structure in two device layers provided in some embodiments. Figure 6 (a) is a schematic diagram of the layout structure of the gate structure in the first device layer. Figure 6 (b) is a schematic diagram of the layout structure of the gate structure in the second device layer. In some embodiments, the third gate 203 includes a first sub-gate 210 extending in the second direction y, a second sub-gate 220 extending in the first direction x, and a third sub-gate 230 extending in the second direction y. The first gate 201 extends in the second direction y and forms the first sub-gate 210 in the P region 303. The third sub-gate 230 extends in the second direction and forms the fourth gate 204 in the second N region 302. In the second direction y, the first sub-gate 210 and the third sub-gate 230 are located on opposite sides of the second sub-gate 220. The second sub-gate 220 is configured to electrically connect the first sub-gate 210 and the third sub-gate 230.

[0084] refer to Figure 6(a) In some embodiments, in the second direction y, there is a gap between the extension line of the first sub-gate 210 and the extension line of the third sub-gate 230, so that the position of the word line in the first direction x can be changed during wiring, so as to facilitate the connection of the word line with the terminal of the corresponding driving transistor. Figure 6 (b) In some embodiments, in the second direction y, the extension line of the first sub-gate 210 and the extension line of the third sub-gate 230 overlap.

[0085] refer to Figure 7 and Figure 8 , Figure 7 A schematic diagram of the layout structure of the second device layer provided in some embodiments, Figure 8 This is a schematic diagram of the layout structure of the third device layer provided in some embodiments. It should be noted that: Figure 7 and Figure 8 In the layout example, the gate structure is laid out based on Figure 6 As shown in (b), those skilled in the art can Figure 7 and Figure 8 The layout example is for Figure 6 (a) Deformation.

[0086] refer to Figure 7 (a) and Figure 7 (b) In some embodiments, in the plane where the device layer 101 is located and in the second direction, the second N region 302 is located on a side of the P region 303 away from the first N region 301 .

[0087] refer to Figure 8 (a) and Figure 8 (b) In some embodiments, in the plane of the device layer 101 and in the second direction, the second N region 302 is disposed adjacent to the first N region 301. In one example, the second N region 302 is located between the first N region 301 and the P region 303; in another example, the first N region 301 is located between the second N region 302 and the P region 303. Figure 8 Examples not shown).

[0088] refer to Figure 7 (a) and Figure 8 (a) In a first direction x, two opposite sides of a common gate shared by the first and fourth gates (to receive a common drive signal K1) are defined as a first side and a second side. In some embodiments, the second gate 202 and the fifth gate 205 are located on opposite sides of the common gate. For example, if the second gate 202 is located on the first side of the first gate, the fifth gate 205 is located on the second side of the fourth gate; if the second gate 202 is located on the second side of the first gate, the fifth gate 205 is located on the first side of the fourth gate.

[0089] refer to Figure 7 (b) and Figure 8 (b) In a first direction x, two opposite sides of a common gate of the first and fourth gates (to receive a common drive signal K1) are defined as a first side and a second side. In some embodiments, the second gate 202 and the fifth gate 205 are located on the same side of the common gate. For example, if the second gate 202 is located on the first side of the first gate, the fifth gate 205 is located on the first side of the fourth gate; if the second gate 202 is located on the second side of the first gate, the fifth gate 205 is located on the second side of the fourth gate.

[0090] refer to Figure 3 and Figure 9 , Figure 9 Schematic diagram of the layout structure of multiple layout groups in a wordline driver layout provided in some embodiments. In some embodiments, the multiple layout units 200 include alternating first layout units 401 and second layout units 402, where the second layout units 402 are mirror images of the first layout units 401 in a first direction x.

[0091] In some embodiments, adjacent first layout cells 401 and second layout cells 402 in a first direction x form a layout group 410, and within layout group 401, the first gate of first layout cell 401 and the first gate of second layout cell 402 are adjacently arranged. By arranging layout cells 200 to be mirror-symmetrical and forming first layout cells 401 and second layout cells 402 of layout group 410, terminals of driver transistors in different layout cells 200 are shared, thereby reducing the layout area of ​​word line driver layout 100.

[0092] refer to Figure 10 and Figure 11 , Figure 10 A schematic diagram of a circuit structure of two word line drivers corresponding to a layout group based on a 2D5T design provided in some embodiments, Figure 11 Some embodiments provide Figure 10 Schematic diagram of the device layer layout structure of a layout group in the example. Among them, 2D5T means that two word lines are connected to five driver transistors. It should be noted that Figure 11 For Figure 5 The layout structure diagram of the layout group 410 is constructed based on the layout structure diagram of the device layer 101 of the example. Figures 6 to 8 relatively Figure 5 The idea of ​​transformation Figure 11 Make corresponding adjustments.

[0093] In addition, Figure 10 and Figure 11In the description of the example, 4 word lines are laid out in each layout unit, and 3 word lines are laid out in the first routing layer and 1 word line is laid out in the second routing layer (i.e. x=4, i1=3, i2=1). Among them, the sub-word line driver corresponding to a layout unit in the layout group 410 is used to lay out the first word line WL <0> , the second word line WL <1> , the third word line WL <2> and the fourth word line WL <3> , the sub-word line driver corresponding to another layout unit is used to lay out the fifth word line WL <4> , sixth word line WL <5> , seventh word line WL <6> and the eighth word line WL <7> . The first word line WL <0> , the second word line WL <1> , the third word line WL <2> , fifth word line WL <4> , sixth word line WL <5> and the seventh word line WL <6> Arranged in the first wiring layer, the fourth word line WL <3> and the eighth word line WL <7> It is laid out in the second routing layer. Figure 11 In this example, the first sub-gate 210 and the third sub-gate 230 located in the P region 303 further include an extended gate in the first direction x, and the extended gate is used to isolate adjacent active regions located in the P region 303. In addition, in some embodiments, the first gate 201 and the second gate 202 located in the first N region 301, or the fourth gate 204 and the fifth gate 205 located in the second N region 302 may also include an extended gate in the first direction x.

[0094] In the second direction, the first N region 301 includes the adjacent first and second regions, the first P region 303 includes the adjacent third, fourth, fifth, and sixth regions, and the third and second regions are adjacent. The second N region 302 includes the adjacent seventh and eighth regions, and the seventh and sixth regions are adjacent. For the first layout unit 401 in the same layout group 410, in the first region, the second side active region of the first gate 201 and the first side active region of the second gate 202 are connected to the first word line WL <0> In the second region, the second side active region of the first gate 201 and the first side active region of the second gate 202 are connected to the second word line WL <1> In the third region, the second side active region of the first sub-gate 210 is connected to the first word line WL <0> In the fourth region, the second side active region of the first sub-gate 210 is connected to the fourth word line WL <3> In the fifth region, the first side active region of the third sub-gate 230 is connected to the second word line WL <1> In the sixth region, the first side active region of the third sub-gate 230 is connected to the third word line WL <2> In the seventh region, the first side active region of the fourth gate 204 is connected to the fourth word line WL <3> In the eighth region, the first side active region of the fourth gate 204 is connected to the third word line WL <2> For the first layout unit 402 in the same layout group 410, in the first region, the second side active region of the first gate 201 and the first side active region of the second gate 202 are connected to the fifth word line WL <4> In the second region, the second side active region of the first gate 201 and the first side active region of the second gate 202 are connected to the sixth word line WL <5> In the third region, the second side active region of the first sub-gate 210 is connected to the fifth word line WL <4> In the fourth region, the second side active region of the first sub-gate 210 is connected to the eighth word line WL <7> In the fifth region, the first side active region of the third sub-gate 230 is connected to the sixth word line WL <5> In the sixth region, the first side active region of the third sub-gate 230 is connected to the seventh word line WL <6> In the seventh region, the first side active region of the fourth gate 204 is connected to the eighth word line WL <7> In the eighth region, the first side active region of the fourth gate 204 is connected to the seventh word line WL <6> .

[0095] In some embodiments, for a first layout unit in the same layout group 410, the side closer to the second layout unit in the first direction x is defined as the first side, and the side farther from the second layout unit is defined as the second side. In the first N region 301, the first side active region corresponding to the first gate 201 is used to receive a first control signal, and the second side active region corresponding to the first gate 201 and the first side active region corresponding to the second gate 202 are shared to connect to the corresponding word line. In the P region 303, the first side active region corresponding to the first sub-gate 210 is used to receive a second control signal, and the second side active region corresponding to the first sub-gate 210 is connected to the corresponding word line. The first side active region corresponding to the third sub-gate 230 is connected to the corresponding word line, and the second side active region corresponding to the third sub-gate 230 is used to receive a third control signal. In the second N region 302, the second side active region corresponding to the fourth gate 204 is used to receive a fourth control signal, and the first side active region corresponding to the fourth gate 204 and the second side active region corresponding to the fifth gate 205 are shared to connect to the corresponding word line.

[0096] Similarly, for the second layout unit in the same layout group 410, the side closer to the first layout unit in the first direction x is defined as the first side, and the side farther from the first layout unit is defined as the second side. In the first N region 301, the first-side active area corresponding to the first gate 201 is used to receive the first control signal, and the second-side active area corresponding to the first gate 201 and the first-side active area corresponding to the second gate 202 are shared to connect to the corresponding word line. In the P region 303, the first-side active area corresponding to the first sub-gate 210 is used to receive the second control signal, and the second-side active area corresponding to the first sub-gate 210 is connected to the corresponding word line. The first-side active area corresponding to the third sub-gate 230 is connected to the corresponding word line, and the second-side active area corresponding to the third sub-gate 230 is used to receive the third control signal. In the second N region 302, the second-side active area corresponding to the fourth gate 204 is used to receive the fourth control signal, and the first-side active area corresponding to the fourth gate 204 and the second-side active area corresponding to the fifth gate 205 are shared to connect to the corresponding word line.

[0097] In some embodiments, the second gate 202 in the first layout unit and the second gate 202 in the second layout unit in the adjacent layout group are a first shared gate structure; the fifth gate 205 in the first layout unit in the same layout group and the fifth gate 205 in the second layout unit are a second shared gate structure.

[0098] Assume that the common driving signal corresponding to the first N-type transistor and the first P-type transistor in the first layout unit is MWLa, and the common driving signal corresponding to the first N-type transistor and the first P-type transistor in the second layout unit is MWLb.

[0099] For the first word line WL <0> In the corresponding first layout unit, in the first N region 301, the first gate 201 is used to receive the common drive signal MWLa, the first side active area of ​​the first gate 201 is used to receive the first control signal Vkk, and the second side active area of ​​the first gate 201 is used to connect to the first word line WL <0> , to form a first N-type transistor N0. The second gate 202 is used to receive the corresponding independent driving signal FXB <0> The first side active region of the second gate 202 is shared with the second side active region of the first gate 201. The second side active region of the second gate 202 is used to receive the first signal neta. Since the second gate 202 in the first layout unit and the second gate 202 in the second layout unit in the adjacent layout group 410 are a first shared gate structure, the second side active region serves as the first side active region of the second gate 202 in the adjacent layout group 410 to connect to the corresponding word line (e.g., WL <6> ) to form the second N-type transistor N00. In the P region 303, the first sub-gate 210 is shared with the first gate 201 in the first N region 301 to receive the common drive signal MWLa, and the first side active area of ​​the first sub-gate 210 is used to receive the second control signal FXT <0> The second side active region of the first sub-gate 210 is used to connect the first word line WL <0> , to form a P-type transistor P0.

[0100] For the second word line WL <1> In the corresponding first layout unit, in the first N region 301, the first gate 201 is used to receive the common drive signal MWLa, the first side active area of ​​the first gate 201 is used to receive the first control signal Vkk, and the second side active area of ​​the first gate 201 is used to connect the second word line WL <1> , to form a first N-type transistor N1. The second gate 202 is used to receive the corresponding independent driving signal FXB <1> The first side active region of the second gate 202 is shared with the second side active region of the first gate 201. The second side active region of the second gate 202 is used to receive the second signal netb. Since the second gate 202 in the first layout unit and the second gate 202 in the second layout unit in the adjacent layout group 410 are a first shared gate structure, the second side active region serves as the first side active region of the second gate 202 in the adjacent layout group 410 to connect to the corresponding word line (e.g., WL <7> ) to form the second N-type transistor N10. In the P region 303, the third sub-gate 230 is shared with the fourth gate 204 in the second N region 302 to receive the common drive signal MWLa, and the second side active area of ​​the third sub-gate 230 is used to receive the third control signal FXT <1> The first side active region of the third sub-gate 230 is used to connect the second word line WL <1> , to form a P-type transistor P1.

[0101] For the third word line WL <2> In the corresponding first layout unit, in the second N region 302, the fourth gate 204 is used to receive the common drive signal MWLa, and the first side active area of ​​the fourth gate 204 is connected to the third word line WL <2> The second side active area of ​​the fourth gate 204 is used to receive the fourth control signal Vkk to form the first transistor N2. Since the fifth gate 205 in the first layout unit and the fifth gate 205 in the second layout unit are a second common gate structure, the fifth gate 205 is used to receive the corresponding independent driving signal FXB <2> The active area of ​​the fifth gate 205 near the first layout unit is shared with the first side active area of ​​the fourth gate 204 in the first layout unit, and the active area near the second layout unit is shared with the first side active area of ​​the fourth gate 204 in the second layout unit, thereby forming the second N-type transistor N20. In the P region 303, the third sub-gate 230 is shared with the fourth gate 204 in the second N region 302 to receive the common drive signal MWLa. The first side active area of ​​the third sub-gate 230 is used to connect to the third word line WL <2> The second side active region of the third sub-gate 230 is used to receive the third control signal FXT <2> , to form a P-type transistor P2.

[0102] For the fourth word line WL <3> In the corresponding first layout unit, in the second N region 302, the fourth gate 204 is used to receive the common drive signal MWLa, and the first side active area of ​​the fourth gate 204 is connected to the fourth word line WL <3> The second side active region of the fourth gate 204 is used to receive the fourth control signal Vkk to form the first transistor N3. Since the fifth gate 205 in the first layout unit and the fifth gate 205 in the second layout unit are a second common gate structure, the fifth gate 205 is used to receive the corresponding independent driving signal FXB <3> The active area of ​​the fifth gate 205 near the first layout unit is shared with the first side active area of ​​the fourth gate 204 in the first layout unit, and the active area near the second layout unit is shared with the first side active area of ​​the fourth gate 204 in the second layout unit, thereby forming the second N-type transistor N30. In the P region 303, the first sub-gate 210 is shared with the first gate 201 in the first N region 301 to receive the common drive signal MWLa. The second side active area of ​​the first sub-gate 210 is used to connect to the fourth word line WL <3> The first side active region of the first sub-gate 210 is used to receive the second control signal FXT <3> , to form a P-type transistor P3.

[0103] For the fifth word line WL <4> In the corresponding second layout unit, in the second N region 302, the fourth gate 204 is used to receive the common drive signal MWLb, and the first side active area of ​​the fourth gate 204 is connected to the fifth word line WL <4> The second side active region of the fourth gate 204 is used to receive the fourth control signal Vkk to form the first transistor N4. Since the fifth gate 205 in the first layout unit and the fifth gate 205 in the second layout unit are a second common gate structure, the fifth gate 205 is used to receive the corresponding independent drive signal FXB <2> The active area of ​​the fifth gate 205 near the first layout unit is shared with the first side active area of ​​the fourth gate 204 in the first layout unit, and the active area near the second layout unit is shared with the first side active area of ​​the fourth gate 204 in the second layout unit, to form the second N-type transistor N40. In the P region 303, the third sub-gate 230 is shared with the fourth gate 204 in the second N region 302 to receive the common drive signal MWLb. The first side active area of ​​the third sub-gate 230 is used to connect to the fifth word line WL <4> The second side active region of the third sub-gate 230 is used to receive the third control signal FXT <2> , to form a P-type transistor P4.

[0104] For the sixth word line WL <5> In the corresponding second layout unit, in the second N region 302, the fourth gate 204 is used to receive the common drive signal MWLb, and the first side active area of ​​the fourth gate 204 is connected to the sixth word line WL <5> The second side active area of ​​the fourth gate 204 is used to receive the fourth control signal Vkk to form the first transistor N5. Since the fifth gate 205 in the first layout unit and the fifth gate 205 in the second layout unit are a second common gate structure, the fifth gate 205 is used to receive the corresponding independent driving signal FXB <3> The active area of ​​the fifth gate 205 near the first layout unit is shared with the first side active area of ​​the fourth gate 204 in the first layout unit, and the active area near the second layout unit is shared with the first side active area of ​​the fourth gate 204 in the second layout unit, thereby forming the second N-type transistor N50. In the P region 303, the first sub-gate 210 is shared with the first gate 201 in the first N region 301 to receive the common drive signal MWLb. The second side active area of ​​the first sub-gate 210 is used to connect to the sixth word line WL <5> The first side active region of the first sub-gate 210 is used to receive the second control signal FXT <3> , to form a P-type transistor P5.

[0105] For the seventh word line WL <6> In the corresponding second layout unit, in the first N region 301, the first gate 201 is used to receive the common drive signal MWLb, the first side active area of ​​the first gate 201 is used to receive the first control signal Vkk, and the second side active area of ​​the first gate 201 is used to connect the seventh word line WL <6> , to form a first N-type transistor N6. The second gate 202 is used to receive the corresponding independent driving signal FXB <0> The first side active region of the second gate 202 is shared with the second side active region of the first gate 201. The second side active region of the second gate 202 is used to receive the third signal netc. Since the second gate 202 in the first layout unit and the second gate 202 in the second layout unit in the adjacent layout group 410 are a first shared gate structure, the second side active region serves as the first side active region of the second gate 202 in the adjacent layout group 410 to connect to the corresponding word line (e.g., WL <0> ) to form the second N-type transistor N60. In the P region 303, the first sub-gate 210 is shared with the first gate 201 in the first N region 301 to receive the common drive signal MWLb, and the first side active area of ​​the first sub-gate 210 is used to receive the second control signal FXT <0> The second side active region of the first sub-gate 210 is used to connect the seventh word line WL <6> , to form a P-type transistor P6.

[0106] For the eighth word line WL <7> In the corresponding second layout unit, in the first N region 301, the first gate 201 is used to receive the common drive signal MWLb, the first side active area of ​​the first gate 201 is used to receive the first control signal Vkk, and the second side active area of ​​the first gate 201 is used to connect to the eighth word line WL <7> , to form a first N-type transistor N7. The second gate 202 is used to receive the corresponding independent driving signal FXB <1> The first side active region of the second gate 202 is shared with the second side active region of the first gate 201. The second side active region of the second gate 202 is used to receive the fourth signal netd. Since the second gate 202 in the first layout unit and the second gate 202 in the second layout unit in the adjacent layout group 410 are a first shared gate structure, the second side active region serves as the first side active region of the second gate 202 in the adjacent layout group 410 to connect to the corresponding word line (e.g., WL <1> ) to form the second N-type transistor N70. In the P region 303, the third sub-gate 230 is shared with the first gate 201 in the second N region 302 to receive the common drive signal MWLb, and the second side active area of ​​the third sub-gate 230 is used to receive the third control signal FXT <3> The first side active region of the third sub-gate 230 is used to connect the eighth word line WL <7> , to form a P-type transistor P7.

[0107] In the above example, the signal corresponding to Vkk is used to provide a low level or a negative level, and FXT <0> 、FXT <1> 、FXT <2> and FXT <3> The corresponding signal is used to provide a high level. In addition, for the first word line WL <0> Corresponding FXB <0> and FXT <0> are mutually inverted signals; for the second word line WL <1> Corresponding FXB <1> and FXT <1> are mutually inverted signals; for the third word line WL <2> Corresponding FXB <2> and FXT <2> are mutually inverted signals; for the fourth word line WL <3> Corresponding FXB <3> and FXT <3> are mutually inverted signals; for the fifth word line WL <4> Corresponding FXB <2> and FXT <2> are mutually inverted signals; for the sixth word line WL <5> Corresponding FXB <3> and FXT <3> are mutually inverted signals; for the seventh word line WL <6> Corresponding FXB <0> and FXT <0> are mutually inverted signals; for the eighth word line WL <7> Corresponding FXB <1> and FXT <1> They are mutually inverted signals.

[0108] It should be noted that in Figure 11 In this example, the first side active area corresponding to the first gate 201 in the first layout unit and the second layout unit are shared, and the first side active area corresponding to the first sub-gate 210 in the first layout unit and the second layout unit are shared, thereby further reducing the area of ​​the layout group. In some embodiments, the first side active area corresponding to the first gate 201 in the first layout unit and the second layout unit are not shared, and the first side active area corresponding to the first sub-gate 210 in the first layout unit and the second layout unit are not shared.

[0109] refer to Figure 12 and Figure 13 , Figure 12 A schematic diagram of a circuit structure of two word line drivers corresponding to a layout group based on a 3T design provided in some embodiments, Figure 13 Some embodiments provide Figure 12 Schematic diagram of the device layer layout structure of a layout group in the example. Among them, 3T means that each word line is connected to 3 driver transistors. It should be noted that Figure 13 For Figure 5 The layout structure diagram of the layout group 410 is constructed based on the layout structure diagram of the device layer 101 of the example. Figures 6 to 8 relatively Figure 5 The idea of ​​transformation Figure 13 Make corresponding adjustments.

[0110] In addition, Figure 12 and Figure 13In the description of the embodiment corresponding to the example, 4 word lines are laid out in each layout unit, and 3 word lines are laid out in the first routing layer and 1 word line is laid out in the second routing layer (i.e. x=4, i1=3, i2=1). Among them, the sub-word line driver corresponding to a layout unit in the layout group 410 is used to lay out the first word line WL <0> , the second word line WL <1> , the third word line WL <2> and the fourth word line WL <3> , the sub-word line driver corresponding to another layout unit is used to lay out the fifth word line WL <4> , sixth word line WL <5> , seventh word line WL <6> and the eighth word line WL <7> Among them, the first word line WL <0> , the second word line WL <1> , the third word line WL <2> , fifth word line WL <4> , sixth word line WL <5> and the seventh word line WL <6> Arranged in the first wiring layer, the fourth word line WL <3> and the eighth word line WL <7> It is laid out in the second routing layer. Figure 13 In this example, the first sub-gate 210 and the third sub-gate 230 located in the P region 303 further include an extended gate in the first direction x, and the extended gate is used to isolate adjacent active regions located in the P region 303. In addition, in some embodiments, the first gate 201 and the second gate 202 located in the first N region 301, or the fourth gate 204 and the fifth gate 205 located in the second N region 302 may also include an extended gate in the first direction x.

[0111] In the second direction, the first N region 301 includes the adjacent first and second regions, the first P region 303 includes the adjacent third, fourth, fifth, and sixth regions, and the third and second regions are adjacent. The second N region 302 includes the adjacent seventh and eighth regions, and the seventh and sixth regions are adjacent. For the first layout unit 401 in the same layout group 410, in the first region, the second side active region of the first gate 201 and the first side active region of the second gate 202 are connected to the first word line WL <0> In the second region, the second side active region of the first gate 201 and the first side active region of the second gate 202 are connected to the second word line WL <1> In the third region, the second side active region of the first sub-gate 210 is connected to the first word line WL <0> In the fourth region, the second side active region of the first sub-gate 210 is connected to the fourth word line WL <3> In the fifth region, the first side active region of the third sub-gate 230 is connected to the second word line WL <1> In the sixth region, the first side active region of the third sub-gate 230 is connected to the third word line WL <2> In the seventh region, the first side active region of the fourth gate 204 is connected to the fourth word line WL <3> In the eighth region, the first side active region of the fourth gate 204 is connected to the third word line WL <2> For the first layout unit 402 in the same layout group 410, in the first region, the second side active region of the first gate 201 and the first side active region of the second gate 202 are connected to the fifth word line WL <4> In the second region, the second side active region of the first gate 201 and the first side active region of the second gate 202 are connected to the sixth word line WL <5> In the third region, the second side active region of the first sub-gate 210 is connected to the fifth word line WL <4> In the fourth region, the second side active region of the first sub-gate 210 is connected to the eighth word line WL <7> In the fifth region, the first side active region of the third sub-gate 230 is connected to the sixth word line WL <5> In the sixth region, the first side active region of the third sub-gate 230 is connected to the seventh word line WL <6> In the seventh region, the first side active region of the fourth gate 204 is connected to the eighth word line WL <7> In the eighth region, the first side active region of the fourth gate 204 is connected to the seventh word line WL <6> .

[0112] In some embodiments, for a first layout unit in the same layout group 410, the side closer to the second layout unit in the first direction x is defined as the first side, and the side farther from the second layout unit is defined as the second side. In the first N region 301, the first side active region corresponding to the first gate 201 is used to receive a first control signal, and the second side active region corresponding to the first gate 201 and the first side active region corresponding to the second gate 202 are shared to connect to the corresponding word line. In the P region 303, the first side active region corresponding to the first sub-gate 210 is used to receive a second control signal, and the second side active region corresponding to the first sub-gate 210 is connected to the corresponding word line. The first side active region corresponding to the third sub-gate 230 is connected to the corresponding word line, and the second side active region corresponding to the third sub-gate 230 is used to receive a third control signal. In the second N region 302, the second side active region corresponding to the fourth gate 204 is used to receive a fourth control signal, and the first side active region corresponding to the fourth gate 204 and the second side active region corresponding to the fifth gate 205 are shared to connect to the corresponding word line.

[0113] Similarly, for the second layout unit in the same layout group 410, the side closer to the first layout unit in the first direction x is defined as the first side, and the side farther from the first layout unit is defined as the second side. In the first N region 301, the first-side active area corresponding to the first gate 201 is used to receive the first control signal, and the second-side active area corresponding to the first gate 201 and the first-side active area corresponding to the second gate 202 are shared to connect to the corresponding word line. In the P region 303, the first-side active area corresponding to the first sub-gate 210 is used to receive the second control signal, and the second-side active area corresponding to the first sub-gate 210 is connected to the corresponding word line. The first-side active area corresponding to the third sub-gate 230 is connected to the corresponding word line, and the second-side active area corresponding to the third sub-gate 230 is used to receive the third control signal. In the second N region 302, the second-side active area corresponding to the fourth gate 204 is used to receive the fourth control signal, and the first-side active area corresponding to the fourth gate 204 and the second-side active area corresponding to the fifth gate 205 are shared to connect to the corresponding word line.

[0114] In some embodiments, the second gate 202 in the first layout unit is electrically connected to the second gate 202 in the second layout unit in the adjacent layout group through a first connecting gate 403, and the second side active area of ​​the second gate 202 in the first layout unit and the second side active area of ​​the second gate 202 in the second layout unit in the adjacent layout group are shared to receive a fifth control signal; the fifth gate 205 in the first layout unit in the same layout group is electrically connected to the fifth gate 205 in the second layout unit through a second connecting gate 404, and the second side active area of ​​the fifth gate 205 in the first layout unit and the second side active area of ​​the fifth gate 205 in the second layout unit are shared to receive a sixth control signal.

[0115] Assume that the common driving signal corresponding to the first N-type transistor and the first P-type transistor in the first layout unit is MWLa, and the common driving signal corresponding to the first N-type transistor and the first P-type transistor in the second layout unit is MWLb.

[0116] For the first word line WL <0> In the corresponding first layout unit, in the first N region 301, the first gate 201 is used to receive the common drive signal MWLa, the first side active area of ​​the first gate 201 is used to receive the first control signal Vkk, and the second side active area of ​​the first gate 201 is used to connect to the first word line WL <0> , to form a first N-type transistor N0. The second gate 202 is used to receive the corresponding independent driving signal FXB <0> The first side active region of the second gate 202 is shared with the second side active region of the first gate 201. The second side active region of the second gate 202 is used to receive the fifth control signal Vkk to form the second N-type transistor N00. In addition, the second gate 202 is also connected to the second gate 202 in the adjacent layout group through the first connecting gate 403, and the second gates 202 in the adjacent layout group share the second side active region. In the P region 303, the first sub-gate 210 is shared with the first gate 201 in the first N region 301 to receive the common drive signal MWLa. The first side active region of the first sub-gate 210 is used to receive the second control signal FXT <0> The second side active region of the first sub-gate 210 is used to connect the first word line WL <0> , to form a P-type transistor P0.

[0117] For the second word line WL <1> In the corresponding first layout unit, in the first N region 301, the first gate 201 is used to receive the common drive signal MWLa, the first side active area of ​​the first gate 201 is used to receive the first control signal Vkk, and the second side active area of ​​the first gate 201 is used to connect the second word line WL <1> , to form a first N-type transistor N1. The second gate 202 is used to receive the corresponding independent driving signal FXB <1> The first side active region of the second gate 202 is shared with the second side active region of the first gate 201. The second side active region of the second gate 202 is used to receive the fifth control signal Vkk to form the second N-type transistor N10. In addition, the second gate 202 is also connected to the second gate 202 in the adjacent layout group through the first connecting gate 403, and the second gates 202 in the adjacent layout group share the second side active region. In the P region 303, the third sub-gate 230 is shared with the fourth gate 204 in the second N region 302 to receive the common drive signal MWLa. The second side active region of the third sub-gate 230 is used to receive the third control signal FXT. <1> The first side active region of the third sub-gate 230 is used to connect the second word line WL <1> , to form a P-type transistor P1.

[0118] For the third word line WL <2> In the corresponding first layout unit, in the second N region 302, the fourth gate 204 is used to receive the common drive signal MWLa, and the first side active area of ​​the fourth gate 204 is connected to the third word line WL <2> The second side active area of ​​the fourth gate 204 is used to receive the fourth control signal Vkk to form the first transistor N2. The fifth gate 205 is used to receive the corresponding independent control signal FXB <2> The first side active region of the fifth gate 205 is used to receive the sixth control signal Vkk to form the second N-type transistor N20. In addition, the fifth gate 205 in the same layout group is also connected to the fifth gate 205 of another layout unit through the second connecting gate 404, and the fifth gates 205 corresponding to the two layout units in the same layout group share the first side active region. In the P region 303, the third sub-gate 230 is shared with the fourth gate 204 in the second N region 302 to receive the common drive signal MWLa. The first side active region of the third sub-gate 230 is used to connect to the third word line WL. <2> The second side active region of the third sub-gate 230 is used to receive the third control signal FXT <2> , to form a P-type transistor P2.

[0119] For the fourth word line WL <3> In the corresponding first layout unit, in the second N region 302, the fourth gate 204 is used to receive the common drive signal MWLa, and the first side active area of ​​the fourth gate 204 is connected to the fourth word line WL <3> The second side active area of ​​the fourth gate 204 is used to receive the fourth control signal Vkk to form the first transistor N3. The fifth gate 205 is used to receive the corresponding independent control signal FXB <3> The first side active region of the fifth gate 205 is used to receive the sixth control signal Vkk to form the second N-type transistor N30. In addition, the fifth gate 205 in the same layout group is also connected to the fifth gate 205 of another layout unit through the second connecting gate 404, and the fifth gates 205 corresponding to the two layout units in the same layout group share the first side active region. In the P region 303, the first sub-gate 210 is shared with the first gate 201 in the first N region 301 to receive the common drive signal MWLa. The second side active region of the first sub-gate 210 is used to connect to the fourth word line WL. <3> The first side active region of the first sub-gate 210 is used to receive the second control signal FXT <3> , to form a P-type transistor P3.

[0120] For the fifth word line WL <4> In the corresponding second layout unit, in the second N region 302, the fourth gate 204 is used to receive the common drive signal MWLb, and the first side active area of ​​the fourth gate 204 is connected to the fifth word line WL <4> The second side active area of ​​the fourth gate 204 is used to receive the fourth control signal Vkk to form the first transistor N4. The fifth gate 205 is used to receive the corresponding independent control signal FXB <2> The first side active region of the fifth gate 205 is used to receive the sixth control signal Vkk to form the second N-type transistor N40. In addition, the fifth gate 205 in the same layout group is also connected to the fifth gate 205 of another layout unit through the second connecting gate 404, and the fifth gates 205 corresponding to the two layout units in the same layout group share the first side active region. In the P region 303, the third sub-gate 230 is shared with the fourth gate 204 in the second N region 302 to receive the common drive signal MWLb. The first side active region of the third sub-gate 230 is used to connect to the fifth word line WL <4> The second side active region of the third sub-gate 230 is used to receive the third control signal FXT <2> , to form a P-type transistor P4.

[0121] For the sixth word line WL <5> In the corresponding second layout unit, in the second N region 302, the fourth gate 204 is used to receive the common drive signal MWLb, and the first side active area of ​​the fourth gate 204 is connected to the sixth word line WL <5> The active area on the second side of the fourth gate 204 is used to receive the fourth control signal Vkk to form the first transistor N5. The fifth gate 205 is used to receive the corresponding independent control signal FXB <3> The first side active region of the fifth gate 205 is used to receive the sixth control signal Vkk to form the second N-type transistor N50. In addition, the fifth gate 205 in the same layout group is also connected to the fifth gate 205 of another layout unit through the second connecting gate 404, and the fifth gates 205 corresponding to the two layout units in the same layout group share the first side active region. In the P region 303, the first sub-gate 210 is shared with the first gate 201 in the first N region 301 to receive the common drive signal MWLb. The second side active region of the first sub-gate 210 is used to connect to the sixth word line WL <5> The first side active region of the first sub-gate 210 is used to receive the second control signal FXT <3> , to form a P-type transistor P5.

[0122] For the seventh word line WL <6> In the corresponding second layout unit, in the first N region 301, the first gate 201 is used to receive the common drive signal MWLb, the first side active area of ​​the first gate 201 is used to receive the first control signal Vkk, and the second side active area of ​​the first gate 201 is used to connect the seventh word line WL <6> , to form a first N-type transistor N6. The second gate 202 is used to receive the corresponding independent driving signal FXB <0> The first side active region of the second gate 202 is shared with the second side active region of the first gate 201. The second side active region of the second gate 202 is used to receive the fifth control signal Vkk to form the second N-type transistor N60. In addition, the second gate 202 is also connected to the second gate 202 in the adjacent layout group through the first connecting gate 403, and the second gates 202 in the adjacent layout group share the second side active region. In the P region 303, the first sub-gate 210 is shared with the first gate 201 in the first N region 301 to receive the common drive signal MWLb. The first side active region of the first sub-gate 210 is used to receive the second control signal FXT. <0> The second side active region of the first sub-gate 210 is used to connect the seventh word line WL <6> , to form a P-type transistor P6.

[0123] For the eighth word line WL <7> In the corresponding second layout unit, in the first N region 301, the first gate 201 is used to receive the common drive signal MWLb, the first side active area of ​​the first gate 201 is used to receive the first control signal Vkk, and the second side active area of ​​the first gate 201 is used to connect to the eighth word line WL <7> , to form a first N-type transistor N7. The second gate 202 is used to receive the corresponding independent driving signal FXB <1> The first side active region of the second gate 202 is shared with the second side active region of the first gate 201. The second side active region of the second gate 202 is used to receive the fifth control signal Vkk to form the second N-type transistor N70. In addition, the second gate 202 is also connected to the second gate 202 in the adjacent layout group through the first connecting gate 403, and the second gates 202 in the adjacent layout group share the second side active region. In the P region 303, the third sub-gate 230 is shared with the fourth gate 204 in the second N region 302 to receive the common drive signal MWLb. The second side active region of the third sub-gate 230 is used to receive the third control signal FXT. <3> The first side active region of the third sub-gate 230 is used to connect the eighth word line WL <7> , to form a P-type transistor P7.

[0124] In the above example, the signal corresponding to Vkk is used to provide a low level or a negative level, and FXT <0> 、FXT <1> 、FXT <2> and FXT <3> The corresponding signal is used to provide a high level. In addition, for the first word line WL <0> Corresponding FXB <0> and FXT <0> are mutually inverted signals; for the second word line WL <1> Corresponding FXB <1> and FXT <1> are mutually inverted signals; for the third word line WL <2> Corresponding FXB <2> and FXT <2> are mutually inverted signals; for the fourth word line WL <3> Corresponding FXB <3> and FXT <3> are mutually inverted signals; for the fifth word line WL <4> Corresponding FXB <2> and FXT <2> are mutually inverted signals; for the sixth word line WL <5> Corresponding FXB <3> and FXT <3> are mutually inverted signals; for the seventh word line WL <6> Corresponding FXB <0> and FXT <0> are mutually inverted signals; for the eighth word line WL <7> Corresponding FXB <1> and FXT <1> They are mutually inverted signals.

[0125] It should be noted that in Figure 13 In this example, the first side active area corresponding to the first gate 201 in the first layout unit and the second layout unit are shared, and the first side active area corresponding to the first sub-gate 210 in the first layout unit and the second layout unit are shared, thereby further reducing the area of ​​the layout group. In some embodiments, the first side active area corresponding to the first gate 201 in the first layout unit and the second layout unit are not shared, and the first side active area corresponding to the first sub-gate 210 in the first layout unit and the second layout unit are not shared.

[0126] In summary, for the word line driver layout 100 provided in the embodiment of the present disclosure, by laying out the word lines on different layers, the spacing between the word lines is increased compared to laying out all the word lines on the same layer, thereby avoiding the reduction in word line spacing that introduces a larger parasitic capacitance affecting the performance of the memory; in addition, after increasing the word line spacing, the size of the transistors used in the word line driver is also increased, thereby improving the reliability of the device, reducing the process difficulty and improving the product yield.

[0127] It should be noted that, in the absence of conflicts, the features disclosed in the word line driver layouts provided in the above embodiments can be randomly combined to obtain new word line driver layout embodiments.

[0128] Another embodiment of the present disclosure further provides a memory, the layout of the memory including the word line driver layout provided by the above embodiment.

[0129] In some embodiments, the memory may be a storage unit or device based on a semiconductor device or component. For example, the memory device may be a volatile memory, such as a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate synchronous dynamic random access memory (LPDDR SDRAM), a graphics double data rate synchronous dynamic random access memory (GDDR SDRAM), a double data rate type dual synchronous dynamic random access memory (DDR2 SDRAM), a double data rate type triple synchronous dynamic random access memory (DDR3 SDRAM), a double data rate fourth generation synchronous dynamic random access memory (25DDR4 SDRAM), a thyristor random access memory (TRAM), or the like; or may be a non-volatile memory, such as a phase change random access memory (PRAM), a magnetic random access memory (MRAM), a resistive random access memory (RRAM), or the like.

[0130] In some embodiments, the memory provided in this application can be applied to a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply.

[0131] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, please refer to the detailed description of other embodiments above and will not be repeated here.

[0132] The basic concepts have been described above. It will be apparent to those skilled in the art that the detailed disclosure above is merely illustrative and does not limit the present application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements, and amendments to the present application. Such modifications, improvements, and amendments are suggested in the present application and remain within the spirit and scope of the exemplary embodiments of the present application.

[0133] The above is a detailed introduction to a word line driver layout and memory provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. At the same time, for those skilled in the art, based on the ideas of the present application, there may be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present application.

Claims

1. A word line driver layout, comprising a plurality of layout units arranged in a first direction, wherein the first direction is the arrangement direction of the word lines, wherein: Each of the layout units is used to lay out a driving transistor and x word lines, where x is any positive integer, and is characterized in that each of the layout units includes: The device layer is configured to set the driving transistor corresponding to each word line; a metal routing layer, located on one side of the device layer in a direction perpendicular to the plane where the device layer is located, and configured to lay out the x word lines; The metal routing layer includes at least a first routing layer and a second routing layer; The first routing layer is located on one side of the device layer and is configured to lay out i1 word lines, where i1 is any positive integer less than x; The second routing layer is located on a side of the first routing layer away from the device layer, and is configured to lay out i2 word lines, where i2 is any positive integer less than x; The word lines arranged in the first wiring layer are electrically connected to the corresponding driving transistors; The word lines arranged in the second wiring layer are electrically connected to the corresponding driving transistors through the conductive structure arranged in the first wiring layer.

2. The word line driver layout according to claim 1, wherein: The first routing layer and the second routing layer are based on the same material to lay out the word lines.

3. The word line driver layout according to claim 2, wherein: The material used to lay out the word lines in the first routing layer and the second routing layer includes tungsten.

4. The word line driver layout according to claim 1, wherein: i1>i2.

5. The word line driver layout according to claim 1, wherein: Each of the layout units further includes: a first contact via, located between the first wiring layer and the device layer; a second contact via, located between the first wiring layer and the second wiring layer; The conductive structure in the first wiring layer includes at least: i2 first conductive structures; The word lines arranged in the first wiring layer are electrically connected to the corresponding driving transistors in the device layer through the corresponding first contact holes; The word lines arranged in the second wiring layer are electrically connected to the corresponding first conductive structures through the corresponding second contact vias, and each of the first conductive structures is electrically connected to the corresponding driving transistor in the device layer through the corresponding first contact vias.

6. The word line driver layout according to claim 5, wherein: The metal routing layer further includes: a third routing layer, the third routing layer being located on a side of the second routing layer away from the first routing layer, and being configured to lay i3 word lines, where i3 is any positive integer less than x; Each of the layout units further includes: a third contact via located between the second routing layer and the third routing layer; The conductive structure in the first wiring layer further includes: i3 second conductive structures; The second wiring layer further includes: i3 third conductive structures; The word lines arranged in the third routing layer are electrically connected to the corresponding third conductive structures through the corresponding third contact vias, each of the third conductive structures is electrically connected to the corresponding second conductive structures through the corresponding second contact vias, and each of the second conductive structures is electrically connected to the corresponding driving transistors in the device layer through the corresponding first contact vias.

7. The word line driver layout according to claim 1, wherein: The driving transistor includes a first N-type transistor, a P-type transistor, and a second N-type transistor; wherein the first N-type transistor and the P-type transistor are controlled based on a common driving signal, and the second N-type transistor is controlled based on an independent driving signal; In the plane where the device layer is located and in the second direction, the device layer includes a first N region and a P region, and the second direction is the extension direction of the word line; In the plane where the device layer is located and in the first direction, the first N region includes a first gate and a second gate; The first gate serves as the gate of the first N-type transistor, the second gate serves as the gate of the second N-type transistor, the first gate extends in the second direction, and a third gate is formed in the P region, and the third gate serves as the gate of the P-type transistor.

8. The word line driver layout according to claim 7, wherein: In the plane where the device layer is located and in the second direction, the device layer further includes a second N region, and the second N region is located on a side of the P region away from the first N region; In the plane where the device layer is located and in the first direction, the second N region includes a fourth gate and a fifth gate, the fourth gate serves as the gate of the first N-type transistor, and the fifth gate serves as the gate of the second N-type transistor; The third gate extends in the second direction, and the fourth gate is formed in the second N region.

9. The word line driver layout according to claim 8, wherein: The third gate includes: a first sub-gate extending in the second direction, a second sub-gate extending in the first direction, and a third sub-gate extending in the second direction; The first gate extends in the second direction and forms the first sub-gate in the P region; The third sub-gate extends in the second direction and forms the fourth gate in the second N region; in the second direction, the first sub-gate and the third sub-gate are located on opposite sides of the second sub-gate, and the second sub-gate is configured to electrically connect the first sub-gate and the third sub-gate; An extension line of the first sub-gate is parallel to an extension line of the third sub-gate, and in the first direction, the second gate and the fifth gate are located on opposite sides of the third gate.

10. The word line driver layout according to claim 9, wherein: The plurality of layout units include: first layout units and second layout units that are alternately arranged; in the first direction, the second layout units are mirror-symmetrical units of the first layout units.

11. The word line driver layout according to claim 10, wherein: In the first direction, the adjacent first layout unit and the second layout unit constitute a layout group, and in the layout group, the first gate in the first layout unit and the first gate in the second layout unit are adjacently arranged.

12. The word line driver layout according to claim 11, wherein: include: For the first layout unit in the same layout group, in the first direction, a side close to the second layout unit is defined as a first side, and a side away from the second layout unit is defined as a second side; In the first N region, a first side active region corresponding to the first gate is used to receive a first control signal, and a second side active region corresponding to the first gate and a first side active region corresponding to the second gate are shared to connect to corresponding word lines; In the P region, the first side active region corresponding to the first sub-gate is used to receive the second control signal, and the second side active region corresponding to the first sub-gate is connected to the corresponding word line; the first side active region corresponding to the third sub-gate is connected to the corresponding word line, and the second side active region corresponding to the third sub-gate is used to receive the third control signal; In the second N region, the second side active region corresponding to the fourth gate is used to receive a fourth control signal, and the first side active region corresponding to the fourth gate and the second side active region corresponding to the fifth gate are shared to connect corresponding word lines.

13. The word line driver layout according to claim 12, wherein: include: The first side active area corresponding to the first gate in the first layout unit and the second layout unit is shared; The first side active region corresponding to the first sub-gate in the first layout unit and the second layout unit is shared.

14. The word line driver layout according to claim 12 or 13, wherein: include: The second gate in the first layout unit is electrically connected to the second gate in the second layout unit in the adjacent layout group through a first connecting gate, and a second side active region of the second gate in the first layout unit and a second side active region of the second gate in the second layout unit in the adjacent layout group are shared to receive a fifth control signal; The fifth gate in the first layout unit and the fifth gate in the second layout unit in the same layout group are electrically connected through a second connecting gate, and the second side active area of ​​the fifth gate in the first layout unit and the second side active area of ​​the fifth gate in the second layout unit are shared to receive a sixth control signal.

15. The word line driver layout according to claim 12 or 13, wherein: include: The second gate in the first layout unit and the second gate in the second layout unit in the adjacent layout group form a first common gate structure; The fifth gate in the first layout unit and the fifth gate in the second layout unit in the same layout group are a second common gate structure.

16. The word line driver layout according to claim 12, wherein: x=4, i1=3, i2=1.

17. The word line driver layout according to claim 16, wherein: include: The x word lines include a first word line, a second word line, a third word line, and a fourth word line, wherein the first word line, the second word line, and the third word line are arranged in a first routing layer, and the fourth word line is arranged in a second routing layer; In the second direction, the first N region includes a first region and a second region that are adjacent to each other, the first P region includes a third region, a fourth region, a fifth region, and a sixth region that are adjacent to each other, the third region and the second region are adjacent to each other, the second region includes a seventh region and an eighth region that are adjacent to each other, and the seventh region and the sixth region are adjacent to each other; In the first region, the second side active region of the first gate and the first side active region of the second gate are connected to the first word line; In the second region, the second side active region of the first gate and the first side active region of the second gate are connected to the second word line; In the third region, the active region on the second side of the first sub-gate is connected to the first word line; In the fourth region, the active region on the second side of the first sub-gate is connected to the fourth word line; In the fifth region, the active region on the first side of the third sub-gate is connected to the second word line; In the sixth region, the first side active region of the third sub-gate is connected to the third word line; In the seventh region, the first side active region of the fourth gate is connected to the fourth word line; In the eighth region, the first side active region of the fourth gate is connected to the third word line.

18. A memory, characterized in that: The memory layout includes the word line driver layout according to any one of claims 1 to 17.

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