Pulsed pre-charge circuit and electronic device using the same

Abstract

The application provides a pulsating pre-charging circuit and an electronic device using the same, and relates to the technical field of power management. The pulsating pre-charging circuit comprises a field effect transistor arranged between an input end and an energy storage capacitor, and the field effect transistor is configured to work in a linear region and continuously and alternately output a first current and a second current to the energy storage capacitor according to an input power source when the pulsating pre-charging circuit pre-charges the energy storage capacitor, and the current value of the first current is greater than that of the second current. The pulsating pre-charging control circuit comprises a first reference power source and a second reference power source, and the pulsating pre-charging control circuit is configured to continuously and alternately output a first driving voltage and a second driving voltage to the gate of the field effect transistor according to the first reference power source and the second reference power source when the pulsating pre-charging circuit pre-charges the energy storage capacitor, and the first driving voltage is used for making the field effect transistor output the first current, and the second driving voltage is used for making the field effect transistor output the second current.

Description

TECHNICAL FIELD

[0001] The present application mainly relates to the technical field of power management, and particularly relates to a pulsating pre-charging circuit and electronic equipment suitable for the same. BACKGROUND

[0002] Electronic equipment needs power supply to work normally. The power supply can come from a direct current power supply system or an alternating current power grid. In order to stabilize the input power supply voltage and the input power supply outage holding time, an energy storage capacitor is often added to the rear circuit of the input side of the electronic equipment.

[0003] However, when the electronic equipment is powered on, the energy storage capacitor is instantaneously charged, which causes a huge start-up inrush current, that is, an inrush current or a surge current. The huge start-up inrush current is related to the input voltage, the capacitance of the energy storage capacitor and the start-up time. Specifically, the greater the capacitance of the energy storage capacitor, the greater the start-up inrush current; the higher the input voltage, the greater the start-up inrush current; and the shorter the start-up time, the greater the start-up inrush current. The excessive start-up inrush current can trigger the overcurrent protection mechanism of the electronic equipment to cause the electronic equipment to shut down. In addition, the excessive start-up inrush current can also cause the input fuse in the electronic equipment to melt. At the same time, the excessive start-up inrush current can also cause the power supply voltage to drop, which affects the power supply quality of other loads. SUMMARY

[0004] The technical problem to be solved by the present application is to provide a pulsating pre-charging circuit and electronic equipment suitable for the same, so as to suppress the start-up inrush current.

[0005] To solve the above technical problem, the present application provides a pulsating pre-charging circuit arranged between a power supply input end and a rear circuit, the rear circuit comprising an energy storage capacitor, the power supply input end being used for connecting an input power supply, the pulsating pre-charging circuit being adapted to pre-charge the energy storage capacitor by the input power supply, the pulsating pre-charging circuit comprising: a field effect transistor arranged between the input end and the energy storage capacitor, the field effect transistor being configured to work in a linear region when the pulsating pre-charging circuit pre-charges the energy storage capacitor, and to continuously and alternately output a first current and a second current to the energy storage capacitor according to the input power supply, the current value of the first current being greater than that of the second current; and a pulsating pre-charging control circuit comprising a first reference power supply and a second reference power supply, the pulsating pre-charging control circuit being configured to continuously and alternately output a first driving voltage and a second driving voltage to the gate of the field effect transistor according to the first reference power supply and the second reference power supply when the pulsating pre-charging circuit pre-charges the energy storage capacitor, the first driving voltage being used for the field effect transistor to output the first current, and the second driving voltage being used for the field effect transistor to output the second current.

[0006] Optionally, the pulsed pre-charge circuit further comprises a voltage sampling circuit configured to convert the first current or the second current output by the field effect tube into a corresponding sampling voltage; and the pulsed pre-charge control circuit is further configured to adjust the first driving voltage or the second driving voltage according to the sampling voltage.

[0007] Optionally, the pulsed pre-charge control circuit further comprises an operational amplifier, a negative input terminal of the operational amplifier being used to access the sampling voltage; a switch, one end of the switch being connected to a positive input terminal of the operational amplifier, the other end of the switch being connected to the first reference power supply or the second reference power supply; a PWM control sub-circuit configured to control the switch to be connected to the first reference power supply and the second reference power supply alternately and continuously, so that the operational amplifier outputs a first output voltage corresponding to the first reference power supply and a second output voltage corresponding to the second reference power supply alternately and continuously; and a driving sub-circuit, the driving sub-circuit being connected to an output terminal of the operational amplifier and a gate of the field effect tube respectively, the driving sub-circuit being adapted to convert the first output voltage into the first driving voltage and convert the second output voltage into the second driving voltage.

[0008] Optionally, the pulsed pre-charge control circuit further comprises a feedback compensation sub-circuit connected between the negative input terminal of the operational amplifier and the output terminal of the operational amplifier.

[0009] Optionally, the voltage sampling circuit comprises a sampling resistor, and the field effect tube comprises an NMOS tube, wherein the NMOS tube is close to a positive electrode of the power supply input terminal, a drain of the NMOS tube is connected to the positive electrode of the power supply input terminal, a source of the NMOS tube is connected to one end of the sampling resistor and the negative input terminal of the operational amplifier respectively, the other end of the sampling resistor is connected to one end of the energy storage capacitor, the positive input terminal of the operational amplifier is connected to the positive electrode of the first reference power supply when the switch is connected to the first reference power supply, and the positive input terminal of the operational amplifier is connected to the positive electrode of the second reference power supply when the switch is connected to the second reference power supply.

[0010] Optionally, the voltage sampling circuit comprises a sampling resistor, and the field effect tube comprises an NMOS tube, wherein the NMOS tube is close to a negative electrode of the power supply input terminal, one end of the sampling resistor is connected to the negative electrode of the power supply input terminal, the other end of the sampling resistor is connected to a source of the NMOS tube and the negative input terminal of the operational amplifier respectively, a drain of the NMOS tube is connected to one end of the energy storage capacitor, the positive input terminal of the operational amplifier is connected to the positive electrode of the first reference power supply when the switch is connected to the first reference power supply, and the positive input terminal of the operational amplifier is connected to the positive electrode of the second reference power supply when the switch is connected to the second reference power supply.

[0011] Optionally, the voltage sampling circuit comprises a sampling resistor, and the field effect tube comprises a PMOS tube, wherein the PMOS tube is close to the positive pole of the power input end, one end of the sampling resistor is connected to the positive pole of the power input end, the other end of the sampling resistor is connected to the source of the PMOS tube and the negative input end of the operational amplifier respectively, the drain of the PMOS tube is connected to one end of the energy storage capacitor, the positive input end of the operational amplifier is connected to the negative pole of the first reference power supply when the switch is connected to the first reference power supply, and the positive input end of the operational amplifier is connected to the negative pole of the second reference power supply when the switch is connected to the second reference power supply.

[0012] Optionally, the voltage sampling circuit comprises a sampling resistor, and the field effect tube comprises a PMOS tube, wherein the PMOS tube is close to the positive pole of the power input end, one end of the sampling resistor is connected to the positive pole of the power input end, the other end of the sampling resistor is connected to the source of the PMOS tube and the negative input end of the operational amplifier respectively, the drain of the PMOS tube is connected to one end of the energy storage capacitor, the positive input end of the operational amplifier is connected to the negative pole of the first reference power supply when the switch is connected to the first reference power supply, and the positive input end of the operational amplifier is connected to the negative pole of the second reference power supply when the switch is connected to the second reference power supply.

[0013] Optionally, the minimum current value of the second current is 0.000001A.

[0014] To solve the above technical problems, the application provides an electronic device, comprising: a power input end adapted to access an input power supply; a later-stage circuit comprising an energy storage capacitor; and the above-mentioned pulse pre-charging circuit connected between the power input end and the later-stage circuit, the pulse pre-charging circuit being adapted to pre-charge the energy storage capacitor by the input power supply.

[0015] Compared with the prior art, the application has the following advantages: by making the field effect tube work in the linear region and alternately outputting the first current and the second current to the energy storage capacitor according to the input power supply, the start-up inrush current can be effectively suppressed and the energy storage capacitor can be pre-charged. In addition, due to the alternately outputting of the first current and the second current, the power consumption of the field effect tube can be effectively reduced, and the junction temperature of the field effect tube is further reduced, thereby getting rid of the limitation of the safe working area. BRIEF DESCRIPTION OF DRAWINGS

[0016] The accompanying drawings are included to provide a further understanding of the application, and are incorporated in and constitute apart of this application, illustrate embodiments of the application, and together with the description serve to explain the principles of the application. In the drawings:

[0017] Figure 1 is a structural block diagram of an electronic device according to an embodiment of the application;

[0018] Figure 2 is Figure 1Circuit schematic of the pulse pre-charge circuit, power input terminal and the post-stage circuit;

[0019] Figure 3 is Figure 2 Schematic diagram of the voltage across the power input terminal, the voltage across the energy storage capacitor and the pre-charge current with time;

[0020] Figure 4 is Figure 2 Schematic diagram of the safe working area of the NMOS transistor;

[0021] Figure 5 Circuit schematic of the pulse pre-charge circuit, power input terminal and the post-stage circuit according to an embodiment of the present application;

[0022] Figure 6 Circuit schematic of the pulse pre-charge circuit, power input terminal and the post-stage circuit according to an embodiment of the present application; and

[0023] Figure 7 Circuit schematic of the pulse pre-charge circuit, power input terminal and the post-stage circuit according to an embodiment of the present application. DETAILED DESCRIPTION

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments description. Obviously, the drawings in the following description are only some examples or embodiments of the present application, and for those skilled in the art, the present application can also be applied to other similar scenarios without creative labor on the basis of these drawings. Unless it is clear from the language context or otherwise indicated, the same reference numbers in the drawings represent the same structure or operation.

[0025] As shown in the present application and claims, unless the context clearly indicates otherwise, the words "one", "a", "an", and / or "the" do not mean to specify a single number, but also can include a plurality. Generally speaking, the terms "comprise" and "include" only indicate the inclusion of the steps and elements explicitly identified, and these steps and elements do not constitute an exclusive list, and the method or device can also include other steps or elements.

[0026] The foregoing is a summary and thus contains only the most basic embodiment. The application can be practiced with the specific embodiments and options described herein, and it can also be practiced without such specific embodiments and options. Furthermore, the preceding description and drawings should not be construed as limiting the application. Numerous and various embodiments can be derived from this description without departing from the application. The description and drawings are illustrative only, and the scope of the application is defined only by the appended claims. The embodiments described herein are intended to be merely illustrative of the principles of the application. Numerous modifications may

[0027] In the description of the present application, it should be understood that the orientation words such as "front, back, upper, lower, left, right", "transverse, vertical, perpendicular, horizontal" and "top, bottom" and the like indicated orientation or position relationship are generally based on the orientation or position relationship shown in the drawings, only for the convenience of describing the present application and simplifying the description, without the opposite description, these orientation words do not indicate and imply that the indicated device or element must have a particular orientation or be constructed and operated in a particular orientation, therefore, it cannot be understood as a limitation on the scope of protection of the present application; the orientation words "inner, outer" refer to the inner and outer relative to the contour of each component.

[0028] For the convenience of description, spatial relative terms such as "over", "above", "upper surface", "upper" and the like can be used herein to describe the spatial position relationship of one device or feature with other devices or features as shown in the drawings. It should be understood that the spatial relative terms are intended to include different orientations in use or operation in addition to the orientation of the device described in the drawings. For example, if the device in the drawing is inverted, the device described as "above" or "over" other devices or structures will be positioned "below" or "under" other devices or structures. Thus, the example term "above" can include both "above" and "below" orientations. The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein are interpreted accordingly.

[0029] Furthermore, it should be noted that the use of "first", "second", etc. words to define parts is merely for the convenience of distinguishing between the respective parts, and the above words do not have special meanings unless otherwise stated. Therefore, the above words should not be interpreted as limiting the scope of protection of the present application. In addition, although the terms used in the present application are selected from the commonly used terms, some of the terms mentioned in the present application may be selected by the applicant according to his or her judgment, and the detailed meanings thereof are described in the relevant parts of the description. In addition, the present application is required to be understood not only by the actual terms used, but also by the meanings implied by each term.

[0030] It will be understood that when a part is referred to as being "on", "connected to", "coupled to" or "contacting" another part, it can be directly on, connected to, coupled to, or contacting the other part, or intervening parts can be present. In contrast, when a part is referred to as being "directly on", "directly connected to", "directly coupled to", or "directly contacting" another part, there are no intervening parts present. By the same token, when a first part is referred to as being "electrically contacting" or "electrically coupled to" a second part, there is an electrical path between the first part and the second part that allows current to flow. The electrical path can include capacitors, coupled inductors, and / or other components that allow current to flow, even if there is no direct contact between conductive parts. Embodiment One

[0031] Figure 1 is a structural block diagram of an electronic device according to an embodiment of the present application. As shown in Figure 1 , the electronic device 10 includes a pulsed pre-charge circuit 100, a power input 200, and a post-stage circuit 300. The pulsed pre-charge circuit 100 is disposed between the power input 200 and the post-stage circuit 300. The power input 200 is used to access an input power. The post-stage circuit 300 includes an energy storage capacitor. The pulsed pre-charge circuit 100 is adapted to pre-charge the energy storage capacitor by the input power.

[0032] Continuing to refer to Figure 2The pulse pre-charge circuit 100 in the embodiment includes a field effect tube 11, a pulse pre-charge control circuit 12 and a voltage sampling circuit 13. The field effect tube 11 includes an NMOS tube Q1. The pulse pre-charge control circuit 12 includes an operational amplifier OP1, a switch K1, a first reference power supply V2, a second reference power supply V1, a PWM control sub-circuit 121, a driving sub-circuit 122 and a feedback compensation sub-circuit 123. The voltage sampling circuit 13 includes a sampling resistor RS1. Specifically, the drain of the NMOS tube Q1 is connected to the positive pole of the power input end 200, i.e., the NMOS tube Q1 is close to the positive pole of the power input end 200. The source of the NMOS tube Q1 is connected to one end of the sampling resistor RS1 and the negative input end of the operational amplifier OP1, respectively. The other end of the sampling resistor RS1 is connected to one end of an energy storage capacitor C1. The other end of the energy storage capacitor C1 is connected to the negative pole of the power input end 200. One end of the switch K1 is connected to the positive input end of the operational amplifier OP1, and the other end of the switch K1 is connected to the positive pole of the first reference power supply V2 or the positive pole of the second reference power supply V1. In the embodiment, the negative pole of the first reference power supply V2 and the negative pole of the second reference power supply V1 are grounded, and the first reference power supply V2 is used to provide a first reference voltage, and the second reference power supply V1 is used to provide a second reference voltage. It can be understood that when the switch K1 is connected to the first reference power supply V2, the positive input end of the operational amplifier OP1 is connected to the positive pole of the first reference power supply V2, so that the first reference voltage is input to the positive input end of the operational amplifier OP1. Correspondingly, when the switch K1 is connected to the second reference power supply V1, the positive input end of the operational amplifier OP1 is connected to the positive pole of the second reference power supply V1, so that the second reference voltage is input to the positive input end of the operational amplifier OP1. In addition, in the embodiment, one end of the two power supply ends of the operational amplifier OP1 is connected to a voltage Vcc, and the other end is grounded, so that the operational amplifier OP1 can work normally. It should be noted that the application does not limit the implementation manner of the voltage sampling circuit, and in some embodiments, the voltage sampling circuit includes a current transformer.

[0033] With reference to the foregoing Figure 2, PWM control sub-circuit 121 is configured to control switch K1 to be connected to first reference power supply V2 and second reference power supply V1 alternately, so that operational amplifier OP1 outputs first output voltage corresponding to first reference power supply and second output voltage corresponding to second reference power supply alternately. Driving sub-circuit 122 is connected to output terminal of operational amplifier OP1 and gate of NMOS tube Q1 respectively, and driving sub-circuit 122 is adapted to convert first output voltage into first driving voltage and convert second output voltage into second driving voltage. It should be noted that first output voltage and second output voltage output by operational amplifier OP1 cannot directly drive NMOS tube Q1 to work in linear region, so first output voltage and second output voltage are amplified by driving sub-circuit 122, so that NMOS tube Q1 can be driven smoothly. Therefore, the present application does not limit the setting of driving sub-circuit, and in some embodiments, the driving sub-circuit can be any circuit or component which can generate corresponding driving voltage capable of driving field effect tube to work in linear region according to input voltage.

[0034] With reference to Figure 2 , feedback compensation sub-circuit 123 is connected between negative input terminal of operational amplifier OP1 and output terminal of operational amplifier OP1. In the embodiment, feedback compensation sub-circuit 123 is used to adjust first output voltage and second output voltage output by operational amplifier OP1. It can be understood that, in the embodiment, feedback compensation sub-circuit 123 includes resistance and capacitance to realize signal feedback. With reference to Figure 2 , in the embodiment, the other end of sampling resistance RS1 which is not connected to NMOS tube Q1 is taken as zero potential reference point, i.e. the other end of sampling resistance RS1 is grounded. It should be noted that, in the embodiment, zero potential reference point is provided by pulsed pre-charge control circuit 12, but the present application does not limit the setting mode of zero potential reference point, and in other embodiments, zero potential reference point can be provided by other circuit except pulsed pre-charge control circuit.

[0035] The specific circuit of pulsed pre-charge circuit 100 and the circuit connection relationship among pulsed pre-charge circuit 100, power input terminal 200 and subsequent circuit 300 have been described above. Next, the process that pulsed pre-charge circuit 100 of the embodiment pre-charges energy storage capacitor C1 by input power is described. With reference to Figure 2When the power input end 200 is connected to the input power and the pulsed pre-charge circuit 100 pre-charges the energy storage capacitor C1, the PWM control sub-circuit 121 controls the switch K1 to be connected to the first reference power V2 and the second reference power V1 alternately, so that the gate of the NMOS tube Q1 receives the first driving voltage and the second driving voltage alternately. When the NMOS tube Q1 receives the first driving voltage, the NMOS tube Q1 works in the linear region and generates a pre-charge current I1 flowing through the sampling resistor RS1 and the circuit where the energy storage capacitor C1 is located, which is called the first current. When the NMOS tube Q1 receives the second driving voltage, the NMOS tube Q1 works in the linear region and generates a pre-charge current I2 flowing through the sampling resistor RS1 and the circuit where the energy storage capacitor C1 is located, which is called the second current. In this embodiment, the current value of the first current is greater than the current value of the second current.

[0036] Further referring to Figure 3 , Figure 3 From top to bottom, they are the voltage Vin across the power input end 200 over time, the voltage across the energy storage capacitor C1 over time, and the pre-charge current over time, and the unit of each abscissa is millisecond (ms). As shown in Figure 3 , since the time t1, the power input end 200 is connected to the input power, so that the voltage Vin across the power input end 200 is not 0, thereby the pulsed pre-charge circuit 100 alternately generates the first current and the second current, and the current value of the first current is I1, and the current value of the second current is I2. Exemplarily, Figure 3 , the pulsed pre-charge circuit 100 generates the first current in the period from t1 to t2, and generates the second current in the period from t2 to t3. The first current and the second current are alternately used to pre-charge the energy storage capacitor C1 until the voltage across the energy storage capacitor reaches the preset voltage value Vo at the time tn, and then the pre-charge process is ended.

[0037] Further referring to Figure 2 and Figure 3 , in this embodiment, the minimum current value of the second current is 0.000001A, so when the NMOS tube Q1 works to generate the second current, the NMOS tube Q1 works in the near equivalent off mode, that is, the voltage between the source and the drain of the NMOS tube Q1 is close to zero. At this time, the power consumption of the NMOS tube Q1 is close to 0, so that the junction temperature of the NMOS tube Q1 can be greatly reduced, and then the NMOS tube Q1 can be out of the limitation of the safe operating area (SOA) corresponding to the linear region. Exemplarily, referring to Figure 4When the switching frequency of switch K1 controlled by PWM control subcircuit 121 is 10Hz or higher, the NMOS transistor Q1 operates within a safe operating range equivalent to a 100µs high-frequency switching mode. Conversely, when PWM control subcircuit 121 is not operating, the ordinary NMOS transistor Q1 can only operate within a certain frequency range. Figure 4 The safe working area range in DC mode. It should be noted that... Figure 4 "China" DS(on) In the "Limited work area" R DS(on) This represents the drain-source resistance of the field-effect transistor (FET) in the on-state. It can be seen that the PWM control sub-circuit 121 can significantly improve the safe operating range of the NMOS transistor Q1, thereby improving the overall circuit performance. Furthermore, in this embodiment, the NMOS transistor Q1 does not enter a fully off mode. In a fully off mode, the gate voltage of the NMOS transistor Q1 is low, and the corresponding drain and source voltages will experience voltage spikes, leading to electromagnetic interference. Conversely, since the NMOS transistor Q1 in this embodiment does not enter a fully off mode, its gate voltage remains above the gate voltage threshold, thus preventing voltage spikes and avoiding electromagnetic interference.

[0038] It should be noted that in this embodiment, the value of the first current is adjusted by the first reference power supply V2, the sampling resistor RS1, and the feedback compensation sub-circuit 123. Since the other end of the sampling resistor RS1 is a zero-potential reference point, the end of RS1 connected to the feedback compensation sub-circuit 123 can obtain the sampling voltage formed by the first current flowing through RS1. Subsequently, the feedback compensation sub-circuit 123 uses the sampling voltage to form voltage feedback, thereby adjusting the first driving voltage and stabilizing the value of the first current at a preset value. Correspondingly, the value of the second current is adjusted by the second reference power supply V1, the sampling resistor RS1, and the feedback compensation sub-circuit 123, and the principle is the same as that of the first current adjustment, which will not be repeated here.

[0039] In addition, in the embodiment, the PWM control sub-circuit 121 controls the switching frequency of the switch K1, so that the first current and the second current have different duty cycles, thereby meeting the requirements of the start-up delay time and the peak limit of the charging current. For example, when the power-on impact current needs to be less than 5 times the rated current, and the start-up delay needs to be less than 100 ms, for some energy storage applications, for large input capacitors (usually 10000uF and 20000uF, or even larger), and for pre-charging the output energy storage capacitor with power factor correction (PFC) in the AC input circuit, the prior art solution must increase the power of the charging resistor, which in turn increases the volume of the resistor, or significantly increases the rated current and rated voltage capacity of the transistor, and the heat sink also needs to be increased accordingly, thereby increasing the volume of the system, which cannot meet the requirements of the volume and weight of the system. The pulse pre-charging circuit 100 of the embodiment can change the size of the pre-charging current by controlling the switching frequency of the switch K1 by the PWM control sub-circuit 121, thereby meeting the requirements of the start-up delay time and the peak limit of the charging current.

[0040] It should be noted that the application does not limit the field effect transistor to be an NMOS transistor or to be arranged at the positive side of the power input terminal. The circuit structure of the pulse pre-charging circuit under different field effect transistor arrangements will be described below. It can be understood that the working principle of the pulse pre-charging circuit in the following embodiments is the same as that of the pulse pre-charging circuit in the first embodiment, and will not be repeated hereinafter. In addition, in order to facilitate description, the components or circuits corresponding to the first embodiment in the following embodiments use the same marks, and the same function of the same components or the same circuit will not be repeated. Embodiment two

[0041] Reference Figure 5The pulse pre-charge circuit 100 in the embodiment comprises a field effect tube 11, a pulse pre-charge control circuit 12 and a voltage sampling circuit 13. The field effect tube 11 comprises an NMOS tube Q1. The pulse pre-charge control circuit 12 comprises an operational amplifier OP1, a switch K1, a first reference power supply V2, a second reference power supply V1, a PWM control sub-circuit 121, a driving sub-circuit 122 and a feedback compensation sub-circuit 123. The voltage sampling circuit 13 comprises a sampling resistor RS1. Specifically, one end of the sampling resistor RS1 is connected to the negative pole of the power input end 200, and the other end of the sampling resistor RS1 is connected to the source of the NMOS tube Q1 and the negative input end of the operational amplifier OP1 respectively. Obviously, the NMOS tube Q1 is close to the negative pole of the power input end 200. The drain of the NMOS tube Q1 is connected to one end of an energy storage capacitor C1. The other end of the energy storage capacitor C1 is connected to the positive pole of the power input end 200. One end of the switch K1 is connected to the positive input end of the operational amplifier OP1, and the other end of the switch K1 is connected to the positive pole of the first reference power supply V2 or the positive pole of the second reference power supply V1. In the embodiment, the negative pole of the first reference power supply V2 and the negative pole of the second reference power supply V1 are connected to the ground respectively, and the first reference power supply V2 is used to provide a first reference voltage, and the second reference power supply V1 is used to provide a second reference voltage. In addition, in the embodiment, one end of the two power supply ends of the operational amplifier OP1 is connected to a voltage Vcc, and the other end is connected to the ground, so that the operational amplifier OP1 can work normally.

[0042] With reference to Figure 5 The PWM control sub-circuit 121 is configured to control the switch K1 to be connected to the first reference power supply V2 and the second reference power supply V1 alternately and continuously, so that the operational amplifier OP1 outputs a first output voltage corresponding to the first reference power supply and a second output voltage corresponding to the second reference power supply alternately and continuously. The driving sub-circuit 122 is connected to the output end of the operational amplifier OP1 and the gate of the NMOS tube Q1 respectively, and is adapted to convert the first output voltage into a first driving voltage and convert the second output voltage into a second driving voltage. The feedback compensation sub-circuit 123 is connected between the negative input end of the operational amplifier OP1 and the output end of the operational amplifier OP1. In the embodiment, the end of the sampling resistor RS1 which is not connected to the NMOS tube Q1 is taken as a zero potential reference point, i.e. the end of the sampling resistor RS1 is connected to the ground. Embodiment three

[0043] With reference to Figure 6The pulse pre-charge circuit 100 in the embodiment comprises a field effect tube 11, a pulse pre-charge control circuit 12 and a voltage sampling circuit 13. The field effect tube 11 comprises a PMOS tube Q2. The pulse pre-charge control circuit 12 comprises an operational amplifier OP1, a switch K1, a first reference power supply V2, a second reference power supply V1, a PWM control sub-circuit 121, a driving sub-circuit 122 and a feedback compensation sub-circuit 123. The voltage sampling circuit 13 comprises a sampling resistor RS1. Specifically, one end of the sampling resistor RS1 is connected to the positive pole of the power input end 200, and the other end of the sampling resistor RS1 is connected to the source of the PMOS tube Q2 and the negative input end of the operational amplifier OP1 respectively. Obviously, the PMOS tube Q2 is close to the positive pole of the power input end 200. The drain of the PMOS tube Q2 is connected to one end of an energy storage capacitor C1. The other end of the energy storage capacitor C1 is connected to the negative pole of the power input end 200. One end of the switch K1 is connected to the positive input end of the operational amplifier OP1, and the other end of the switch K1 is connected to the negative pole of the first reference power supply V2 or the negative pole of the second reference power supply V1. In the embodiment, the positive pole of the first reference power supply V2 and the positive pole of the second reference power supply V1 are connected to the supply voltage +Vcc respectively, and the first reference power supply V2 is used to provide a first reference voltage, and the second reference power supply V1 is used to provide a second reference voltage. In addition, in the embodiment, one end of the two supply ends of the operational amplifier OP1 is connected to the voltage Vcc, and the other end is connected to the ground, so that the operational amplifier OP1 can work normally.

[0044] With reference to the foregoing Figure 6 , the PWM control sub-circuit 121 is configured to control the switch K1 to be connected to the first reference power supply V2 and the second reference power supply V1 alternately and continuously, so that the operational amplifier OP1 outputs the first output voltage corresponding to the first reference power supply and the second output voltage corresponding to the second reference power supply alternately and continuously. The driving sub-circuit 122 is connected to the output end of the operational amplifier OP1 and the gate of the PMOS tube Q2 respectively, and is adapted to convert the first output voltage into a first driving voltage and convert the second output voltage into a second driving voltage. The feedback compensation sub-circuit 123 is connected between the negative input end of the operational amplifier OP1 and the output end of the operational amplifier OP1. In the embodiment, the end of the sampling resistor RS1 which is not connected to the PMOS tube Q2 is taken as a zero potential reference point, i.e. the end of the sampling resistor RS1 is connected to the ground. Embodiment four

[0045] With reference to the foregoing Figure 7In the embodiment, the pulsating pre-charge circuit 100 comprises a field effect tube 11, a pulsating pre-charge control circuit 12 and a voltage sampling circuit 13. The field effect tube 11 comprises a PMOS tube Q2. The pulsating pre-charge control circuit 12 comprises an operational amplifier OP1, a switch K1, a first reference power supply V2, a second reference power supply V1, a PWM control sub-circuit 121, a driving sub-circuit 122 and a feedback compensation sub-circuit 123. The voltage sampling circuit 13 comprises a sampling resistor RS1. Specifically, the drain of the PMOS tube Q2 is connected to the negative pole of the power input end 200, i.e. the PMOS tube Q2 is close to the negative pole of the power input end 200. The source of the PMOS tube Q2 is connected to one end of the sampling resistor RS1 and the negative input end of the operational amplifier OP1 respectively. The other end of the sampling resistor RS1 is connected to one end of an energy storage capacitor C1. The other end of the energy storage capacitor C1 is connected to the negative pole of the power input end 200. One end of the switch K1 is connected to the positive input end of the operational amplifier OP1, and the other end of the switch K1 is connected to the negative pole of the first reference power supply V2 or the negative pole of the second reference power supply V1. In the embodiment, the positive pole of the first reference power supply V2 and the positive pole of the second reference power supply V1 are connected to the power supply voltage +Vcc respectively, and the first reference power supply V2 is used to provide a first reference voltage, and the second reference power supply V1 is used to provide a second reference voltage. In addition, in the embodiment, one end of the two power supply ends of the operational amplifier OP1 is connected to the voltage Vcc, and the other end is connected to the ground, so that the operational amplifier OP1 can work normally.

[0046] With reference to the foregoing description, it is obvious that the above-mentioned application disclosure is only used as an example, and does not constitute a limitation on the application. Although the application is not explicitly described, those skilled in the art can make various modifications, improvements and corrections to the application. Such modifications, improvements and corrections are suggested in the application, so such modifications, improvements and corrections still belong to the spirit and scope of the exemplary embodiments of the application. Figure 7 , the PWM control sub-circuit 121 is configured to control the switch K1 to be connected to the first reference power supply V2 and the second reference power supply V1 alternately and continuously, so that the operational amplifier OP1 outputs the first output voltage corresponding to the first reference power supply and the second output voltage corresponding to the second reference power supply alternately and continuously. The driving sub-circuit 122 is connected to the output end of the operational amplifier OP1 and the gate of the PMOS tube Q2 respectively, and the driving sub-circuit 122 is adapted to convert the first output voltage into a first driving voltage and convert the second output voltage into a second driving voltage. The feedback compensation sub-circuit 123 is connected between the negative input end of the operational amplifier OP1 and the output end of the operational amplifier OP1. In the embodiment, the other end of the sampling resistor RS1 which is not connected to the PMOS tube Q2 is used as a zero potential reference point, i.e. the other end of the sampling resistor RS1 is connected to the ground.

[0047] The above has described the basic concept, and it is obvious that the above-mentioned application disclosure is only used as an example, and does not constitute a limitation on the application. Although the application is not explicitly described, those skilled in the art can make various modifications, improvements and corrections to the application. Such modifications, improvements and corrections are suggested in the application, so such modifications, improvements and corrections still belong to the spirit and scope of the exemplary embodiments of the application.

[0048] Furthermore, this application uses specific terms to describe embodiments of the application. For example, "an embodiment," "one embodiment," and / or "some embodiments" refer to a particular feature, structure, or characteristic related to at least one embodiment of the application. Therefore, it should be emphasized and noted that "an embodiment," "one embodiment," or "an alternative embodiment" mentioned twice or more in different locations in this specification do not necessarily refer to the same embodiment. In addition, certain features, structures, or characteristics in one or more embodiments of the application can be appropriately combined.

[0049] Some aspects of this application can be executed entirely by hardware, entirely by software (including firmware, resident software, microcode, etc.), or by a combination of hardware and software. The aforementioned hardware or software may be referred to as a "data block," "module," "engine," "unit," "component," or "system." The processor may be one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DAPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, or combinations thereof. Furthermore, aspects of this application may manifest as computer products residing in one or more computer-readable media, including computer-readable program code. For example, computer-readable media may include, but are not limited to, magnetic storage devices (e.g., hard disks, floppy disks, magnetic tapes, etc.), optical discs (e.g., compressed CDs, digital multifunction DVDs, etc.), smart cards, and flash memory devices (e.g., cards, sticks, key drives, etc.).

[0050] A computer-readable medium may contain a propagated data signal containing computer program code, for example, on baseband or as part of a carrier wave. This propagated signal may take various forms, including electromagnetic, optical, and so on, or suitable combinations thereof. A computer-readable medium can be any computer-readable medium other than a computer-readable storage medium, which can be connected to an instruction execution system, apparatus, or device to enable communication, propagation, or transmission of a program for use. The program code located on the computer-readable medium can be propagated through any suitable medium, including radio, cable, fiber optic cable, radio frequency signals, or similar media, or any combination of the above media.

[0051] Similarly, it should be noted that, in order to simplify the description of the present application and thus aid in the understanding of one or more embodiments, the foregoing description of the embodiments of the present application sometimes combines multiple features into a single embodiment, drawing, or description thereof. However, this disclosure method does not imply that the subject matter of the present application requires more features than those mentioned in the claims. In fact, the embodiments contain fewer features than all the features of the single embodiments disclosed above.

[0052] Some embodiments use numerical descriptors of ingredients, amounts of attributes, and the like. It should be understood that such numerical descriptors used in the description of embodiments are, in some examples, modified by the terms "about," "approximately," or "generally." Unless otherwise stated, "about," "approximately," or "generally" indicates that a deviation of ±20% is allowed on the stated number. Accordingly, numerical values used in the description and claims of some embodiments are approximations that vary depending upon the desired properties sought to be obtained by the individual embodiment. In some embodiments, the numerical values are approximations that vary from the stated values by a reasonable amount, considering the nature of the property and the desired properties sought to be obtained by the individual embodiment. In some embodiments, the numerical parameters are determined by the use of standard techniques.

[0053] While the application has been described with reference to the currently preferred embodiments, those skilled in the art will recognize that changes can be made within the scope of the application, as described in the appended claims, and equivalents thereof.

Claims

1. A pulsed pre-charge circuit, characterized in that, A pulsed pre-charge circuit is positioned between the power input terminal and the subsequent stage circuit, the latter stage circuit including an energy storage capacitor. The power input terminal is used to connect to an input power supply. The pulsed pre-charge circuit is adapted to pre-charge the energy storage capacitor through the input power supply. The pulsed pre-charge circuit includes: A field-effect transistor is disposed between the input terminal and the energy storage capacitor. The field-effect transistor is configured to operate in the linear region when the pulsed pre-charging circuit pre-charges the energy storage capacitor, and to continuously and alternately output a first current and a second current to the energy storage capacitor according to the input power supply, wherein the value of the first current is greater than the value of the second current. A voltage sampling circuit is configured to convert the first current or the second current output by the field-effect transistor into a corresponding sampling voltage; and A pulsed precharge control circuit includes a first reference power supply and a second reference power supply. The pulsed precharge control circuit is configured to, when precharging the energy storage capacitor, continuously and alternately output a first driving voltage and a second driving voltage to the gate of the field-effect transistor (FET) based on the first reference power supply and the second reference power supply. The first driving voltage causes the FET to output a first current, and the second driving voltage causes the FET to output a second current. The pulsed pre-charge control circuit also includes: An operational amplifier, wherein the negative input terminal of the operational amplifier is used to connect the sampling voltage; A switch, one end of which is connected to the positive input terminal of the operational amplifier, and the other end of which is connected to the first reference power supply or the second reference power supply; A PWM control sub-circuit is configured to control the switch to be continuously and alternately connected to the first reference power supply and the second reference power supply, so that the operational amplifier continuously and alternately outputs a first output voltage corresponding to the first reference power supply and a second output voltage corresponding to the second reference power supply; and A driver sub-circuit is connected to the output terminal of the operational amplifier and the gate of the field-effect transistor, respectively. The driver sub-circuit is adapted to convert the first output voltage into the first driving voltage and the second output voltage into the second driving voltage.

2. The pulsed pre-charge circuit as described in claim 1, characterized in that, The pulsed pre-charge control circuit also includes: A feedback compensation circuit is connected between the negative input terminal and the output terminal of the operational amplifier.

3. The pulsed pre-charge circuit as described in claim 2, characterized in that, The voltage sampling circuit includes a sampling resistor, and the field-effect transistor includes an NMOS transistor. The NMOS transistor is located near the positive terminal of the power input terminal, and its drain is connected to the positive terminal of the power input terminal. The source of the NMOS transistor is connected to one end of the sampling resistor and the negative input terminal of the operational amplifier. The other end of the sampling resistor is connected to one end of the energy storage capacitor. When the switch is connected to the first reference power supply, the positive input terminal of the operational amplifier is connected to the positive terminal of the first reference power supply. When the switch is connected to the second reference power supply, the positive input terminal of the operational amplifier is connected to the positive terminal of the second reference power supply.

4. The pulsed pre-charge circuit as described in claim 2, characterized in that, The voltage sampling circuit includes a sampling resistor. The field-effect transistor is an NMOS transistor, wherein the NMOS transistor is located near the negative terminal of the power supply input. One end of the sampling resistor is connected to the negative terminal of the power supply input, and the other end of the sampling resistor is connected to the source of the NMOS transistor and the negative input terminal of the operational amplifier. The drain of the NMOS transistor is connected to one end of the energy storage capacitor. When the switch is connected to the first reference power supply, the positive input terminal of the operational amplifier is connected to the positive terminal of the first reference power supply. When the switch is connected to the second reference power supply, the positive input terminal of the operational amplifier is connected to the positive terminal of the second reference power supply.

5. The pulsed pre-charge circuit as described in claim 2, characterized in that, The voltage sampling circuit includes a sampling resistor, and the field-effect transistor includes a PMOS transistor. The PMOS transistor is located near the positive terminal of the power input terminal. One end of the sampling resistor is connected to the positive terminal of the power input terminal, and the other end of the sampling resistor is connected to the source of the PMOS transistor and the negative input terminal of the operational amplifier. The drain of the PMOS transistor is connected to one end of the energy storage capacitor. When the switch is connected to the first reference power supply, the positive input terminal of the operational amplifier is connected to the negative terminal of the first reference power supply. When the switch is connected to the second reference power supply, the positive input terminal of the operational amplifier is connected to the negative terminal of the second reference power supply.

6. The pulsed pre-charge circuit as described in claim 2, characterized in that, The voltage sampling circuit includes a sampling resistor, and the field-effect transistor includes a PMOS transistor. The PMOS transistor is located near the negative terminal of the power input terminal, and its drain is connected to the negative terminal of the power input terminal. The source of the PMOS transistor is connected to one end of the sampling resistor and the negative input terminal of the operational amplifier. The other end of the sampling resistor is connected to one end of the energy storage capacitor. When the switch is connected to the first reference power supply, the positive input terminal of the operational amplifier is connected to the negative terminal of the first reference power supply. When the switch is connected to the second reference power supply, the positive input terminal of the operational amplifier is connected to the negative terminal of the second reference power supply.

7. The pulsed pre-charge circuit as described in any one of claims 1-6, characterized in that, The minimum current value of the second current is 0.000001A.

8. An electronic device, characterized in that, include: Power input terminal, suitable for connecting to an input power source; The subsequent circuitry includes an energy storage capacitor; as well as The pulsed pre-charge circuit as described in any one of claims 1-7 is connected between the power input terminal and the subsequent circuit, and the pulsed pre-charge circuit is adapted to pre-charge the energy storage capacitor through the input power supply.

Images