Manufacturing method of high-reliability half-hole slot AI computing power card PCB

Abstract

The invention relates to a manufacturing method of a high-reliability half-hole groove AI computing power card PCB, and the method comprises the steps: carrying out the pre-process treatment, including substrate cutting and the like; then laser drilling is carried out, the aperture tolerance is controlled to be + / -12.5 microns, hole filling electroplating is carried out after plasma cleaning, a 18-micron copper layer is formed, and then copper reduction is carried out; then outer layer drilling is conducted, the hole position precision is controlled to be + / -0.075 mm, multiple procedures such as plate copper electroplating and outer layer hole pattern plating are conducted, pattern electroplating, film stripping, resin hole plugging and cap electroplating are conducted, and the copper layer thickness, the hole plugging thickness and the like are strictly controlled in all the steps; and performing outer-layer pattern manufacturing, secondary electroplating, forming processing and surface treatment, and finally completing the subsequent processes. The invention provides a manufacturing method of a high-reliability half-hole groove AI computing power card PCB, and aims to solve the problems of substrate warping, non-uniform high-density interconnection structure, residual copper, microdefects, heterostructure integration bottleneck and the like in the prior art.

Description

Technical Field

[0001] The present invention relates to a high-density interconnected PCB manufacturing technology, and in particular to a high-reliability half-hole slot structure PCB manufacturing method suitable for AI computing power cards. Background Art

[0002] With the rapid development of artificial intelligence (AI) technology, AI computing power cards are placing increasingly stringent demands on PCB performance. In high-computing power modules, PCBs must possess high reliability, complex interconnect structures, and ultra-fine circuitry. However, existing PCB manufacturing processes present numerous challenges, limiting their further application in the AI ​​computing power card market.

[0003] In traditional processes, the overly thick copper layer can easily cause the substrate to warp, affecting the flatness of the PCB and the subsequent processing accuracy. At the same time, in high-density interconnect structures, the thickness gradient problem caused by the composite electroplating process makes it possible to design micro-pitch circuits with a risk of impedance mutation due to differences in copper thickness, affecting the stability of signal transmission. In addition, the problem of residual copper in multiple electroplating processes is difficult to solve, which reduces the selectivity of the etching process and affects the interface clarity of complex stacked structures. Moreover, the traditional single etching process cannot effectively remove the submicron-level structural defects generated during the processing process, affecting the electrical performance and reliability of the PCB. In addition, the compatibility problem between high aspect ratio hole and slot structures and ultra-fine circuits has also been plaguing the development of the industry. Existing processes are difficult to meet complex design requirements.

[0004] Therefore, a new manufacturing method is urgently needed to solve the above problems in order to meet the high reliability and high performance requirements of AI computing power cards for PCBs. Summary of the Invention

[0005] In view of this, the present invention provides a method for manufacturing a high-reliability half-hole slot AI computing power card PCB to solve the problems existing in the prior art, such as substrate warping, uneven high-density interconnection structure, residual copper, microscopic defects, and bottlenecks in heterogeneous structure integration.

[0006] The purpose of the present invention is achieved through the following technical solutions: A method for manufacturing a high-reliability half-hole slot AI computing power card PCB, comprising: (1) Pre-processing: completing substrate cutting, inner layer pattern production and lamination processes; (2) Laser drilling: Use laser to drill blind holes at designated locations, with a hole diameter control tolerance of ±12.5um; (3) Plasma cleaning: Plasma treatment is performed on blind holes to remove residual glue on the hole wall and improve the bonding strength of subsequent electroplating layers; (4) Hole filling electroplating: Use the hole filling process for copper plating to achieve full filling of the blind hole and form an 18μm copper layer; (5) Copper reduction treatment: reduce the copper layer thickness to 11±0.5μm by chemical etching; (6) Outer layer drilling: Use mechanical drilling to drill through holes, and the hole position accuracy is controlled to ±0.075mm; (7) Copper electroplating: Electroplating the entire board to form a base copper layer with a hole copper thickness of 5 μm and a surface copper thickness of 19 ± 3 μm; (8) Outer layer plating hole pattern: Use dry film to cover the non-copper plated area, open the window where the hole needs to be plated, and cover the rest with dry film to ensure that the part where the circuit needs to be made will not be thickened due to electroplating, and at the same time cover the non-copper hole to reduce the cost; (9) Graphic electroplating: Pulse electroplating technology is used to plate copper 20μm to ensure that the hole copper meets the customer's hole copper requirements. Only copper is plated without tin. While meeting the customer's hole copper requirements, it ensures that the subsequent etching bottom copper will not be thickened; (10) Film removal: remove the protective dry film to facilitate resin plugging and prevent the dry film from remaining during the plugging process and causing problems such as open circuit gaps in the circuit production; (11) Resin plugging: Fill the through hole with epoxy resin and control the plugging thickness to 16±3μm after grinding; (12) Cap plating: Use DP+ plate to electroplate thin copper 10um to ensure that the etching bottom copper does not exceed the circuit etching capacity and meet the needs of fine circuits; (13) Outer layer pattern production: Use LDI to produce fine lines to meet the requirements of 3 / 3mil and below lines; (14) Graphic secondary electroplating: by thickening the copper to meet the customer's hole surface copper requirements, and by tin plating, it protects the circuit during the etching process and improves the cloak problem caused by the half-hole in the later process; (15) Molding: CNC cutting to form a semi-hole groove structure, with a dimensional tolerance of ±0.1mm; (16) SES etching: The required circuits are etched out by stripping the film and etching, and the cloak problem caused by the half-hole is etched away at the same time, improving product quality, and stripping the tin to expose the required circuit layer; (17) Post-processing: complete solder mask, surface treatment, shape processing and electrical testing, etc.

[0007] Through innovative step-by-step electroplating processes for through- and blind-vias, precise control of multi-layer copper thickness is achieved. Separate control of the timing of blind-via filling and through-hole plating, combined with a dynamic balanced copper reduction process, effectively addresses the substrate warpage problem caused by excessive copper layer buildup in traditional processes. This technology, through a dynamic balanced copper reduction process, establishes a copper layer stress compensation mechanism, reducing substrate warpage while ensuring conductivity and meeting high flatness requirements, laying the foundation for subsequent ultra-fine circuit fabrication.

[0008] An innovative step-by-step plating system has been developed. This system achieves differentiated copper thickness control in different areas through staged electroplating and selective masking, addressing the challenge of uniformity in high-density interconnect structures. By decoupling the via-fill and pattern plating processes, a zoned masking technique is employed to achieve targeted thickening in critical areas. This solution significantly improves the thickness gradient issues associated with traditional composite electroplating processes, particularly for fine-pitch circuit designs, effectively eliminating the risk of impedance fluctuations caused by copper thickness variations.

[0009] Selective electrodeposition technology is introduced to build an intelligent etching protection system. High-precision dry film patterning technology is used to establish a three-dimensional shielding network, and automatic passivation of non-essential areas is achieved through electrochemical potential difference control. This innovative process completely solves the problem of residual copper in multiple electroplating processes, significantly improves the selectivity of the etching process, and ensures interface clarity in complex stacked structures.

[0010] A composite surface finishing process has been developed to achieve the coordinated elimination of microscopic defects. Combining chemical activation with physical manipulation, an innovative multi-phase collaborative etching mechanism is employed to establish a graded removal strategy for different metal residue forms. This technology overcomes the limitations of traditional single-stage etching processes, completely removing submicron-level structural defects generated during processing while maintaining the integrity of the underlying circuitry.

[0011] Establishing a full-process process compatibility system breaks through the bottleneck of heterogeneous structure integration. By deeply integrating through- and blind-via collaborative design methods with plating stress matching technology, we creatively address the compatibility challenge of high-aspect-ratio slot structures with ultra-fine circuits. This solution achieves process synergy among key technologies such as warp control, resin sealing, and semi-hole molding, significantly improving the product's adaptability to complex design requirements and providing a reliable interconnect solution for high-computing-power modules.

[0012] Preferably, in step (4), the hole filling flatness is optimized by the hole filling process, and the hole mouth depression is controlled to be ≤5 μm.

[0013] The microstructure of the copper layer filling blind vias is optimized through a via-filling process. This process dynamically adjusts the plating solution flow field distribution and current density gradient to preferentially deposit copper ions at the bottom of the blind vias, effectively compensating for the "crater" effect produced by traditional via-filling processes. Precise control of the recessed depth avoids sudden changes in copper layer thickness during subsequent copper reduction steps, ensuring consistent circuit impedance and providing an ideal substrate surface for ultra-fine circuit fabrication. This technology significantly improves the electrical conductivity and thermomechanical reliability of the blind via structure.

[0014] Preferably, a double-sided grinding process is used in step (11) to ensure that the height difference between the surface of the resin plug hole and the plane of the substrate is ≤3 μm.

[0015] The double-sided grinding process achieves highly flat surfaces in the resin-filled vias through a symmetrical pressure control system. Composite polishing techniques simultaneously eliminate surface deformation caused by resin curing shrinkage and substrate stress distortion, ensuring a molecular-level bond between the resin and copper layer. This process effectively ensures uniform electric field distribution during subsequent cap plating, fundamentally preventing plating defects caused by interface unevenness and significantly enhancing the product's structural stability in extreme environments.

[0016] Preferably, the pattern electroplating in steps (9) and (14) adopts pulse reverse current technology, the current density is controlled at 2-3ASD, and the plating uniformity is ≥85%.

[0017] The pulsed reverse current technology optimizes copper ion deposition uniformity within high-aspect-ratio micropores by alternating between a forward pulse duration of 20ms (current density 3 ASD) and a reverse pulse duration of 5ms (current density 1 ASD). This technology overcomes the concentration polarization limitations of traditional DC electroplating by periodically switching the direction of the electric field. The forward pulse phase enables rapid, directional deposition of copper ions, while the reverse pulse phase effectively removes byproducts adsorbed on the electrode surface. This technology significantly improves coating coverage uniformity within high-aspect-ratio micropores, making it particularly suitable for ultra-fine circuit fabrication. It significantly reduces geometric distortion at the circuit edges and ensures waveform integrity during high-frequency signal transmission.

[0018] Preferably, after the forming process in step (15), an alkaline etching solution is used for treatment, with the solution concentration controlled at 50-70 g / L and the temperature at 40-50° C. to remove burrs on the hole wall and copper wire residues.

[0019] The optimized alkaline etching solution achieves selective removal of machining residues. By establishing a dynamic equilibrium between the complexing agent and metal ions, the solution preferentially etches loose metal structures while maintaining a protective effect on the dense copper layer. This process effectively eliminates microscopic defects caused by the molding process, significantly reduces conductor surface roughness, and creates an ideal electromagnetic environment for high-speed signal transmission.

[0020] Preferably, the window opening accuracy of the dry film in step (8) is controlled to be ±15 μm, and the window opening size in the half-hole groove area is 0.05 mm larger than the design value.

[0021] Dry film windowing precision control technology utilizes a real-time thermal deformation compensation algorithm to dynamically correct for deviations in the exposed pattern position. An innovative windowing margin design mechanism ensures safe processing distances while efficiently utilizing the coating material. This technology significantly improves the spatial matching accuracy between the circuit and the semi-hole slot structure, effectively preventing impedance mismatch issues caused by alignment deviations.

[0022] Preferably, the secondary electroplating of the pattern in step (14) adopts a positive film process, combining direct electroplating with whole-board electroplating, and the thickness of the tin layer is controlled to be 8±0.5μm.

[0023] The synergistic application of positive film processing and composite electroplating technology has created a multi-layer precision coating system. Direct electroplating forms a dense underlying structure, and full-board electroplating achieves precise thickness compensation. This technology overcomes the performance limitations of a single-layer coating process, significantly improving the coating's crystal quality and resistance to environmental corrosion, meeting the long-term reliability requirements of high-power density scenarios.

[0024] Preferably, the plasma cleaning parameters in step (3) are: gas flow rate 200-300 sccm, RF power 800-1000 W, and processing time 3-5 min.

[0025] Optimizing plasma cleaning parameters achieves deep cleaning of the three-dimensional structure of blind vias. Precisely controlling plasma energy density and exposure time effectively removes contaminants from the via walls while maintaining the structural integrity of the substrate. This process significantly enhances the chemical activity of the via wall surface, creating an ideal interface for subsequent metal deposition and ensuring a strong metallurgical bond between the via-filling coating and the substrate.

[0026] Preferably, in step (13), the fine circuit is produced using an 8 μm thick dry film, the exposure energy is controlled to be 80-100 mJ / cm², and the development parameters are controlled to be 0.8-1.2% Na2CO3 solution.

[0027] The combination of ultra-thin dry film and precision development technology overcomes the resolution bottleneck in ultra-fine circuit fabrication. By controlling the kinetics of photochemical reactions, an ultra-high selectivity ratio is achieved in the development process. This technology effectively suppresses abnormal etching of circuit sidewalls, ensuring the geometric accuracy and electrical performance consistency of micron-level linewidth structures.

[0028] Preferably, it is suitable for AI computing power card module PCB with line width and line spacing ≤3 / 3mil, containing half-hole slot and resin plug hole structure, and the finished product warpage is ≤0.7%.

[0029] Collaborative innovation throughout the entire process breaks through the limitations of traditional manufacturing, achieving the unification of ultra-fine structure and high reliability through multi-stage stress-balance design and material interface optimization. This technological system significantly enhances the product's adaptability to complex application environments and meets the stringent requirements of the next-generation AI computing modules for high-density interconnection and long-term stable operation.

[0030] The beneficial effects of the present invention compared to the prior art are: Through innovative step-by-step electroplating processes for through- and blind-vias, precise control of multi-layer copper thickness is achieved. Separate control of the timing of blind-via filling and through-hole plating, combined with a dynamic balanced copper reduction process, effectively addresses the substrate warpage problem caused by excessive copper layer buildup in traditional processes. This technology, through a dynamic balanced copper reduction process, establishes a copper layer stress compensation mechanism, reducing substrate warpage while ensuring conductivity and meeting high flatness requirements, laying the foundation for subsequent ultra-fine circuit fabrication.

[0031] An innovative step-by-step plating system has been developed. This system achieves differentiated copper thickness control in different areas through staged electroplating and selective masking, addressing the challenge of uniformity in high-density interconnect structures. By decoupling the via-fill and pattern plating processes, a zoned masking technique is employed to achieve targeted thickening in critical areas. This solution significantly improves the thickness gradient issues associated with traditional composite electroplating processes, particularly for fine-pitch circuit designs, effectively eliminating the risk of impedance fluctuations caused by copper thickness variations.

[0032] Selective electrodeposition technology is introduced to build an intelligent etching protection system. High-precision dry film patterning technology is used to establish a three-dimensional shielding network, and automatic passivation of non-essential areas is achieved through electrochemical potential difference control. This innovative process completely solves the problem of residual copper in multiple electroplating processes, significantly improves the selectivity of the etching process, and ensures interface clarity in complex stacked structures.

[0033] A composite surface finishing process has been developed to achieve the coordinated elimination of microscopic defects. Combining chemical activation with physical manipulation, an innovative multi-phase collaborative etching mechanism is employed to establish a graded removal strategy for different metal residue forms. This technology overcomes the limitations of traditional single-stage etching processes, completely removing submicron-level structural defects generated during processing while maintaining the integrity of the underlying circuitry.

[0034] Establishing a full-process process compatibility system breaks through the bottleneck of heterogeneous structure integration. By deeply integrating through- and blind-via collaborative design methods with plating stress matching technology, we creatively address the compatibility challenge of high-aspect-ratio slot structures with ultra-fine circuits. This solution achieves process synergy among key technologies such as warp control, resin sealing, and semi-hole molding, significantly improving the product's adaptability to complex design requirements and providing a reliable interconnect solution for high-computing-power modules. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments.

[0036] Therefore, the following detailed description of the embodiments of the present application is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0037] It should be noted that, unless there is any conflict, the embodiments and features in the embodiments of this application can be combined with each other.

[0038] The technical solution in this application will be described below.

[0039] Example 1: A method for manufacturing a high-reliability half-hole AI computing power card PCB 1. Core process steps Step 1. Pre-processing: perform substrate cutting, inner layer pattern production and lamination processes.

[0040] Step 2. Laser drilling: Laser drill blind holes with a hole diameter tolerance of ±12.5um.

[0041] Step 3. Plasma cleaning: 200-300 sccm gas flow, 800-1000 W RF power, processing for 3-5 minutes.

[0042] Step 4. Filling hole electroplating: The blind hole is fully filled to form an 18μm copper layer, and the hole mouth is recessed ≤5μm.

[0043] Step 5. Copper reduction treatment: chemical etching to a copper thickness of 11±0.5μm.

[0044] Step 6. Outer layer drilling: Mechanically drill through holes with a hole accuracy of ±0.075mm.

[0045] Step 7. Electroplating copper on the board: hole copper 5μm, surface copper 19±3μm.

[0046] Step 8. Outer layer plating hole pattern: dry film window accuracy ±15μm, half hole slot window maximum 0.05mm.

[0047] Step 9. Pattern electroplating: pulse reverse electroplating (20ms forward 3ASD / 5ms reverse 1ASD), copper plating 20μm.

[0048] Step 10. Demolding: Remove the protective layer to prevent resin residue.

[0049] Step 11. Resin plugging: Double-sided grinding plate to control the height difference ≤ 3μm, plugging thickness 16±3μm.

[0050] Step 12. Cap plating: DP+ board is plated with 10μm thin copper.

[0051] Step 13. Outer layer graphics: LDI production 3 / 3mil line, 8μm dry film, 80-100mJ / cm² exposure.

[0052] Step 14. Secondary electroplating: positive process tin plating 8±0.5μm.

[0053] Step 15. Forming process: CNC gong cutting half hole groove, tolerance ± 0.1mm.

[0054] Step 16. SES etching: alkaline etching solution (50-70g / L, 40-50℃) to remove burrs.

[0055] Step 17. Post-processing: solder mask, surface treatment, shape processing and electrical testing.

[0056] II. Key Technology Innovation 1. Copper layer stress control technology: A dynamic balanced copper reduction process is used to establish a stress compensation mechanism, and the blind hole filling and through-hole electroplating timing are separated and controlled; the substrate warpage is achieved to ≤0.7%, meeting the 3 / 3mil line width requirement.

[0057] 2. Step-by-step coating construction system: Phased electroplating combined with selective masking technology and pulse reverse electroplating make the coating uniformity ≥85%, eliminating the thickness gradient difference of more than 0.5μm in traditional processes.

[0058] 3. Intelligent etching protection system: The three-dimensional shielding network realizes automatic passivation of non-essential areas, improves the selective removal rate of alkaline etching solution by 40%, and reduces the roughness of the circuit sidewall to Rz≤1.2μm.

[0059] 4. Composite surface finishing process: Multi-phase collaborative etching removes submicron defects, the residual copper wire on the hole wall is <0.5μm / m², and the surface roughness of the conductor is Ra≤0.3μm.

[0060] 3. Optimizing process parameters 1. Pulse plating: forward 20ms@3ASD / reverse 5ms@1ASD.

[0061] 2. Resin plugging: Double-sided symmetrical grinding pressure 8-12MPa.

[0062] 3. Graphic transfer: Developed with 0.8-1.2% sodium carbonate solution.

[0063] 4. Circuit protection: Tin layer thickness is controlled within a tolerance of ±0.5μm.

[0064] 5. Interface treatment: Plasma cleaning activation energy ≥ 45mN / m.

[0065] 4. Technical Effect 1. Achieve 5μm level blind hole filling flatness control.

[0066] 2. High-frequency signal loss is reduced by 18% @10GHz.

[0067] 3. The hole copper bonding strength is increased to above 1.5N / mm.

[0068] 4. Impedance control accuracy ±5% @100Ω differential line.

[0069] 5. Thermal cycle test passed 1000 times (-55℃~125℃).

[0070] Through system optimization of 17 processes and 5 core technological innovations, this solution solves key technical problems such as warpage control, plating uniformity, and fine circuit forming in high-density interconnected PCB manufacturing, providing a reliable circuit carrier platform for AI computing power cards.

[0071] Example 2: Optimizing the Thickness of the Via-Filling Electroplated Copper Layer and the Dynamic Copper Reduction Process Adjustment of core process steps: Step 4: Hole filling electroplating: Adjust the thickness of the blind hole filling copper layer to 20μm (originally 18μm), and control the hole mouth depression to ≤4μm.

[0072] Step 5: Copper reduction treatment: Reduce the copper layer thickness to 12±0.3μm (originally 11±0.5μm) by chemical etching.

[0073] Verification of key technological innovations: Dynamically balanced copper reduction: By increasing the initial copper layer thickness and optimizing copper reduction parameters, the stress issues caused by high copper thickness are compensated. Substrate warpage is still controlled to ≤ 0.7%, and impedance consistency is improved to ±4% (previously ±5%).

[0074] Optimization of hole filling flatness: Gradient current density control technology is used to increase the copper layer deposition rate at the bottom of the hole by 15%, and reduce the hole mouth depression to less than 4μm.

[0075] Technical effect: The conductivity of blind vias is improved, and the copper resistance of the vias is reduced by 10%.

[0076] High-frequency signal loss is further reduced to 20%@10GHz (originally 18%).

[0077] The thermal cycle test passed 1500 times (originally 1000 times), verifying the reliability advantage of high copper thickness.

[0078] Example 3: Plasma Cleaning Gas Combination Optimization Adjustment of core process steps: Step 3: Plasma cleaning: using Ar / O2 mixed gas (ratio 7:3), gas flow rate 250 sccm, RF power 900 W, and processing time 4 min.

[0079] Verification of key technological innovations: Three-dimensional purification effect: The chemical activity of O2 in the mixed gas is enhanced, effectively removing organic residues on the pore wall, and the surface energy of the pore wall is increased to 50mN / m (originally 45mN / m).

[0080] Substrate protection: Ar gas physical bombardment is reduced, and the incidence of substrate microcracks is reduced by 30%.

[0081] Technical effect: The bonding strength of the hole-filling electroplating layer is increased to 1.8N / mm (originally 1.5N / mm).

[0082] The hole wall roughness Ra≤0.2μm (originally 0.3μm), improving high-frequency signal transmission performance.

[0083] Example 4: Ultra-fine line (2 / 2mil) fabrication Adjustment of core process steps: Step 13: Outer layer pattern production: Use 6μm thick dry film (originally 8μm), adjust the exposure energy to 100-120mJ / cm², and control the development parameters to 1.0-1.5% Na2CO3 solution.

[0084] Step 14: Graphic secondary electroplating: The thickness of the tin layer is adjusted to 7±0.3μm (originally 8±0.5μm).

[0085] Verification of key technological innovations: Ultra-thin dry film technology: 6μm dry film combined with high-precision LDI exposure achieves 2 / 2mil line width and line spacing, and sidewall verticality ≥88° (originally 85°).

[0086] Tin layer thinning optimization: Reduce the thickness of the tin layer to adapt to finer circuits, and the burrs on the edge of the circuit after etching are ≤0.5μm.

[0087] Technical effect: Impedance control accuracy is improved to ±3%@100Ω differential line.

[0088] The signal transmission rate is increased by 15%, suitable for 5G millimeter wave frequency band.

[0089] Example 5: Full-process automated quality monitoring Adjustment of core process steps: Introducing automated testing equipment: After laser drilling, AOI (automatic optical inspection) is used to monitor the aperture tolerance in real time, and an automatic alarm will be issued if the tolerance is exceeded.

[0090] An online thickness detector is integrated in the graphic electroplating stage, and the copper thickness fluctuation is controlled within ±0.2μm.

[0091] After forming, a 3D scanner is used to detect the size of the half-hole slot, and the pass rate is increased to 99.8%.

[0092] Verification of key technological innovations: Intelligent process closed-loop control: Adjust process parameters through real-time data feedback to reduce human errors.

[0093] Defect Early Warning System: Identifies potential problems (such as uneven resin plugging) in advance, reducing the defective product rate by 40%.

[0094] Technical effect: Production cycle is shortened by 20% and consistency is significantly improved.

[0095] The electrical test pass rate increased from 95% to 98.5%.

[0096] Example 6: Optimization of high aspect ratio half-hole groove structure Adjustment of core process steps: Step (15) Forming processing: Using super-hard tungsten steel tools, the CNC cutting speed is reduced to 8000 rpm (originally 12000 rpm), and the dimensional tolerance is controlled to ±0.08 mm (originally ±0.1 mm).

[0097] Step (16) SES etching: the etching solution concentration was adjusted to 60 g / L, the temperature was 45°C, and the etching time was extended by 10%.

[0098] Verification of key technological innovations: Low-stress processing: Low-speed cutting reduces thermal deformation of the substrate, and the roughness of the side wall of the half-hole groove Rz ≤ 1.0μm (originally 1.2μm).

[0099] Precision etching: Optimize etching solution parameters to completely remove copper wire residue in deep grooves (residue < 0.3μm / m²).

[0100] Technical effect: The semi-hole groove structure has improved strength and its bending resistance has increased by 25%.

[0101] High-frequency signal return loss is reduced to -30dB@20GHz.

[0102] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. A method for manufacturing a high-reliability half-hole AI computing power card PCB, characterized in that: include (1) Pre-processing: completing substrate cutting, inner layer pattern production and lamination processes; (2) Laser drilling: Use laser to drill blind holes at designated locations, with a hole diameter control tolerance of ±12.5um; (3) Plasma cleaning: Plasma treatment is performed on blind holes to remove residual glue on the hole wall and improve the bonding strength of subsequent electroplating layers; (4) Hole filling electroplating: Use the hole filling process for copper plating to achieve full filling of the blind hole and form an 18μm copper layer; (5) Copper reduction treatment: reduce the copper layer thickness to 11±0.5μm by chemical etching; (6) Outer layer drilling: Use mechanical drilling to drill through holes, and the hole position accuracy is controlled to ±0.075mm; (7) Copper electroplating: Electroplating the entire board to form a base copper layer with a hole copper thickness of 5 μm and a surface copper thickness of 19 ± 3 μm; (8) Outer layer plating hole pattern: Use dry film to cover the non-copper plated area, open the window where the hole needs to be plated, and cover the rest with dry film to ensure that the part where the circuit needs to be made will not be thickened due to electroplating, and at the same time cover the non-copper hole to reduce the cost; (9) Graphic electroplating: Pulse electroplating technology is used to plate copper 20μm to ensure that the hole copper meets the customer's hole copper requirements. Only copper is plated without tin. While meeting the customer's hole copper requirements, it ensures that the subsequent etching bottom copper will not be thickened; (10) Film removal: remove the protective dry film to facilitate resin plugging and prevent the dry film from remaining during the plugging process and causing problems such as open circuit gaps in the circuit production; (11) Resin plugging: Fill the through hole with epoxy resin and control the plugging thickness to 16±3μm after grinding; (12) Cap plating: Use DP+ plate to electroplate thin copper 10um to ensure that the etching bottom copper does not exceed the circuit etching capacity and meet the needs of fine circuits; (13) Outer layer pattern production: Use LDI to produce fine lines to meet the requirements of 3 / 3mil and below lines; (14) Graphic secondary electroplating: by thickening the copper to meet the customer's hole surface copper requirements, and by tin plating, it protects the circuit during the etching process and improves the cloak problem caused by the half-hole in the later process; (15) Molding: CNC cutting to form a semi-hole groove structure, with a dimensional tolerance of ±0.1mm; (16) SES etching: The required circuits are etched out by stripping the film and etching, and the cloak problem caused by the half-hole is etched away at the same time, improving product quality, and stripping the tin to expose the required circuit layer; (17) Post-processing: complete solder mask, surface treatment, shape processing and electrical testing, etc.

2. The method for manufacturing a high-reliability half-hole AI computing power card PCB according to claim 1, characterized in that: In step (4), the hole filling process is used to control the dimple to ensure the flatness of the filled hole and optimize the flatness of the filled hole, and the hole mouth depression is controlled to be ≤5μm.

3. The method for manufacturing a high-reliability half-hole AI computing power card PCB according to claim 1, characterized in that: In step (11), a double-sided grinding process is used to ensure that the height difference between the surface of the resin plug hole and the plane of the substrate is ≤3μm.

4. The method for manufacturing a high-reliability half-hole AI computing power card PCB according to claim 1, characterized in that: The pattern electroplating in steps (9) and (14) both uses pulse reverse current technology, with the current density controlled at 2-3ASD and the coating uniformity ≥85%.

5. The method for manufacturing a high-reliability half-hole AI computing power card PCB according to claim 1, characterized in that: Step (15) After forming, alkaline etching solution is used for treatment, with the solution concentration controlled at 50-70 g / L and the temperature at 40-50°C to remove burrs on the hole wall and copper wire residues.

6. The method for manufacturing a high-reliability half-hole AI computing power card PCB according to claim 1, characterized in that: Step (8) The dry film window opening accuracy is controlled to ±15μm, and the window size in the half-hole groove area is 0.05mm larger than the design value.

7. The method for manufacturing a high-reliability half-hole AI computing power card PCB according to claim 1, characterized in that: Step (14) The secondary electroplating of the pattern adopts a positive film process, combining direct electroplating with whole-board electroplating, and the thickness of the tin layer is controlled to 8±0.5μm.

8. The method for manufacturing a high-reliability half-hole AI computing power card PCB according to claim 1, characterized in that: The plasma cleaning parameters in step (3) are: gas flow rate 200-300 sccm, RF power 800-1000 W, and processing time 3-5 min.

9. The method for manufacturing a high-reliability half-hole AI computing power card PCB according to claim 1, characterized in that: In step (13), the fine circuit is made using an 8μm thick dry film, the exposure energy is controlled at 80-100mJ / cm², and the development parameters are controlled at 0.8-1.2% Na2CO3 solution.

10. The method for manufacturing a high-reliability half-hole AI computing power card PCB according to claim 1, characterized in that: Suitable for AI computing card module PCBs with line width and line spacing ≤3 / 3mil, containing half-hole slots and resin plug hole structures, and the finished product warpage ≤0.7%.