A SiC MOSFET device and a method of manufacturing the same

Abstract

The application discloses a SiC MOSFET device and a preparation method thereof, and is applied to the technical field of semiconductors. In the device, a P body region and an N type active region are formed from bottom to top in the upper half of an epitaxial silicon wafer by injection; a source electrode trench is etched downward on the upper surface of the N type active region; the lower surface of the source electrode trench extends into an un-injected region of the epitaxial silicon wafer; a source electrode is filled in the source electrode trench; a gate electrode trench is etched downward on one side of the upper surface of the source electrode; a connecting hole is etched downward on the other side of the upper surface of the source electrode; a gate oxide layer covers the surface of the gate electrode trench; the gate oxide layer is in a trench shape; a gate electrode is filled in the trench of the gate oxide layer; an oxide layer covers the upper surface region of the N type active region, the gate oxide layer, the gate electrode and the source electrode except the connecting hole; and a metal layer covers the upper surface of the oxide layer and the connecting hole, so that the SiC MOSFET device with high reliability, low on-resistance and simple process is provided.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor, and particularly relates to a SiC (silicon carbide) MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) device and a preparation method thereof. BACKGROUND

[0002] SiC has excellent characteristics such as wide band gap, high breakdown voltage, high critical breakdown field, high thermal conductivity, high saturated electron drift velocity, etc., and is mainly divided into planar type and trench type. The trench type SiC MOSFET device has no JFET (Junction Field-Effect Transistor) effect, has lower on-resistance and greater current density, and has the advantages of high integration, low on-resistance, small reverse capacitance, fast switching speed, and small switching loss, etc. However, the trench type power SiC MOSFET device has the problems of large electric field at the bottom of the trench and easy breakdown or injection of interface states, which limits its long-term application reliability. For high reliability and high voltage application scenarios, the mainstream product still uses planar SiC MOSFET devices.

[0003] At present, the planar SiC MOSFET has low channel density, and has the problem of high on-resistance due to the existence of JFET resistance. In contrast, the trench type SiC MOSFET device can effectively improve the channel density, and the on-resistance will be greatly reduced because there is no JFET resistance.

[0004] And for the foregoing problem that the current trench type SiC MOSFET device has low long-term application reliability. At present, the trench type SiC MOSFET device is usually protected by trench bottom injection or increasing Dummy trench (dummy trench) injection to protect the gate oxide from reverse high field depletion, so as to realize gate oxide protection and improve the reliability of the device. However, the ion diffusion in SiC material is difficult and the activation rate is low, so that the gate oxide protection method depending on ion implantation has very high process requirements; at the same time, the existence of Dummy trench will reduce the channel utilization rate, thereby increasing the on-resistance of the device.

[0005] Therefore, how to provide a SiC MOSFET device with high reliability, low on-resistance and simple process has become an important problem. SUMMARY

[0006] In order to solve the above problems existing in the prior art, the present application provides a SiC MOSFET device and a preparation method thereof.

[0007] The technical problem to be solved by the present application is achieved by the following technical solutions.

[0008] In a first aspect, the present application provides a SiC MOSFET device, which comprises:

[0009] an epitaxial silicon wafer; a P body region and an N-type active region are formed from bottom to top by implantation in the upper half of the epitaxial silicon wafer; a source trench is etched downward on the upper surface of the N-type active region, and the lower surface of the source trench extends into the region of the epitaxial silicon wafer which is not implanted;

[0010] a source; the source is filled in the source trench; one side of the upper surface of the source is etched downward to form a gate trench; the other side of the upper surface of the source is etched downward to form a connecting hole;

[0011] a gate oxide layer; the gate oxide layer covers the surface of the gate trench; the gate oxide layer is in the form of a trench;

[0012] a gate; the gate is filled in the trench of the gate oxide layer;

[0013] an oxide layer; the oxide layer covers the upper surface region of the N-type active region, the gate oxide layer, the gate, and the source except the connecting hole;

[0014] a metal layer; the metal layer covers the upper surface of the oxide layer and the connecting hole.

[0015] Optionally, the P body region, the N-type active region, and the lower surface of the source trench are all in the form of an arc.

[0016] Optionally, the depth of the gate trench is greater than the total depth of the P body region and the N-type active region.

[0017] Optionally, the number of the source trenches is multiple, and the interval distance between each source trench ranges from 1.5 to 2 μm.

[0018] Optionally, the width of the source trench ranges from 2 to 2.5 μm, and the depth of the source trench ranges from 2 to 3 μm.

[0019] Optionally, the depth of the gate trench ranges from 1 to 1.5 μm, and the width of the gate trench ranges from 1 to 1.5 μm.

[0020] Optionally, the doping element of the P body region is aluminum element, the doping concentration of the P body region ranges from 1.5 to 2.5×1018 cm-3, and the implantation depth of the P body region ranges from 0.6 to 0.7 μm; the doping element of the N-type active region is nitrogen element, and the doping concentration of the N-type active region ranges from 1.5 to 2.5×1018 cm-3. ​The injection depth of the N-type active region ranges from 0.2 to 0.3 μm.

[0021] Optionally, the doping concentration of the gate ranges from 1E17 to 1E18 cm-3. .

[0022] Optionally, the material of the metal layer is AlCu.

[0023] In a second aspect, the application provides a preparation method of the SiC MOSFET device, which comprises the following steps:

[0024] selecting an epitaxial silicon wafer;

[0025] forming a source trench by etching downward from the upper surface of the epitaxial silicon wafer, and filling the source trench with a source;

[0026] forming a gate trench by etching downward from one side of the upper surface of the source, and depositing a gate oxide layer in the gate trench; the gate oxide layer is in a trench shape;

[0027] depositing a gate in the trench of the gate oxide layer;

[0028] forming a P body region and an N-type active region by implanting from the upper surface of the epitaxial silicon wafer in turn;

[0029] forming a connecting hole by etching downward from the side of the upper surface of the source which is not etched;

[0030] depositing an oxide layer on the upper surface region of the N-type active region, the gate oxide layer, the gate and the source except the connecting hole;

[0031] depositing a metal layer on the oxide layer and the connecting hole.

[0032] In the SiC MOSFET device provided by the application, the source is filled in the source trench, one side of the upper surface of the source is etched downward to form a gate trench, and a gate oxide layer covers the surface of the gate trench. The double-trench structure formed by the source trench and the gate trench can effectively cut off the high electric field generated by the SiC device when working in reverse bias, thereby protecting the gate oxide layer from the high electric field, improving the reliability of the device, and eliminating the need for a Dummy trench on both sides of the gate to protect the gate oxide layer, thereby improving the channel utilization rate, reducing the on-resistance of the device, increasing the current-carrying capacity of the device, and greatly reducing the process difficulty.

[0033] The application will be further described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1is a cross-sectional view of a SiC MOSFET device provided by an embodiment of the present application;

[0035] Figure 2 is a flowchart of a preparation method of a SiC MOSFET device provided by an embodiment of the present application;

[0036] Figure 3 is a preparation process diagram of a SiC MOSFET device provided by an embodiment of the present application.

[0037] The figure mark: 1, epitaxial silicon wafer; 2, source; 3, gate oxide layer; 4, gate; 5, P body region; 6, N-type active region; 7, connecting hole. DETAILED DESCRIPTION

[0038] The present application will be further described in detail below in conjunction with specific embodiments, but the embodiments of the present application are not limited thereto.

[0039] In order to solve the problems of low reliability, high on-resistance and complex process of the existing SiC MOSFET device, an embodiment of the present application provides a SiC MOSFET device, referring to Figure 1 , Figure 1 is a cross-sectional view of a SiC MOSFET device provided by an embodiment of the present application, which comprises an epitaxial silicon wafer 1, a P body region 5, an N-type active region 6, a source 2, a gate oxide layer 3, a gate 4, an oxide layer and a metal layer.

[0040] In the embodiment of the present application, the epitaxial silicon wafer 1 is specifically an N-type epitaxial SiC wafer, and the doping concentration range thereof is . The thickness of the epitaxial silicon wafer 1 can be about 10 μm.

[0041] In the embodiment of the present application, the P body region 5 and the N-type active region 6 are formed by implanting from bottom to top on the upper half of the epitaxial silicon wafer 1. That is, the P body region 5 is located closer to the bottom layer of the epitaxial silicon wafer 1, providing the basis for the voltage resistance of the device, and the N-type active region 6 is covered on the P body region 5, serving as the main conduction channel.

[0042] The lower surface of the P body region 5 and the N-type active region 6 is arc-shaped. Along the lateral cross section of the device, the midpoint of the arc-shaped interface has the deepest implantation depth, and the depth gradually decreases when extending to both sides, forming a smooth transition curved surface. The arc-shaped interface can improve the electric field distribution by reducing the curvature effect, avoid the sharp tip discharge, and improve the voltage resistance and reliability of the device.

[0043] Specifically, the doping element of the P body region 5 is aluminum element, and the doping concentration range thereof is The doping element of the N-type active region 6 is nitrogen element, and the doping concentration range is The implantation depth range is 0.2-0.3 μm.

[0044] In the embodiment of the present application, the upper surface of the N-type active region 6 is etched downward to form a source trench, and the lower surface of the source trench penetrates the N-type active region 6 and the P-body region 5 and extends into the un-implanted region of the epitaxial silicon wafer 1 to form a through structure across the implanted region and the un-implanted region.

[0045] In an implementation, the lower surface of the source trench is arc-shaped, the depth range is 2-3 μm, the width range is 2-2.5 μm, and the arc-shaped interface presents the characteristics of the deepest middle region and gradually shallow sides, forming a smooth transition.

[0046] In an implementation, the number of the source trenches is multiple, and the interval distance range between the source trenches is 1.5-2 μm.

[0047] In the embodiment of the present application, the source 2 is filled in the source trench. The material of the source 2 is polysilicon, which has excellent semiconductor characteristics and process compatibility. In order to further improve the conductivity, the polysilicon source is subjected to N-type doping treatment, for example, by introducing donor impurities such as phosphorus and arsenic to form a stable electron conduction channel, which can further reduce the on-resistance, improve the charge carrier injection, reduce the JFET effect, and improve the performance and reliability of the device.

[0048] Specifically, the source 2 can be N-type doped polysilicon, and the doping concentration range is .

[0049] In the embodiment of the present application, a gate trench is etched downward on one side of the upper surface of the source 2, and a connecting hole 7 is etched downward on the other side of the upper surface of the source 2.

[0050] The lower surface and one side of the gate trench are in contact with the source 2, and the other side is in contact with the P-body region 5 and the N-type active region 6.

[0051] In an implementation, the depth of the gate trench is greater than the total depth of the P-body region 5 and the N-type active region 6.

[0052] Specifically, the depth of the gate trench ranges from 1 to 1.5 μm, and the width of the gate trench ranges from 1 to 1.5 μm.

[0053] In the embodiment of the present application, the width of the connecting hole 7 ranges from about 0.2 μm, and the depth ranges from 0.2 to 0.3 μm.

[0054] In the embodiment of the present application, the gate oxide layer 3 covers the surface of the gate trench, and the gate oxide layer 3 is in a trench shape, which can more evenly distribute the electric field and avoid damage to the gate oxide layer 3 caused by a local electric field that is too high, thereby ensuring that the device can work stably under high voltage conditions. The thickness of the gate oxide layer 3 is in the range of 500-1000 nm, and the material is silicon dioxide.

[0055] In the embodiment of the present application, the gate 4 is filled in the trench of the gate oxide layer 3, and the material of the gate 4 is polysilicon, which has good conductivity and stability. The polysilicon is N-doped, and the purpose of N-doping is to improve the conductivity of the polysilicon so that the gate 4 can more efficiently transmit electrical signals and thus quickly and accurately regulate the on and off states of the device. Through N-doping, the free electron concentration in the polysilicon is greatly increased, and its resistivity is significantly reduced, thereby meeting the requirement of the gate 4 for high conductivity.

[0056] In one implementation, the doping concentration of the gate 4 is in the range of 1e18-1e20 cm-3. Within this doping concentration range, the polysilicon can have good conductivity while taking into account its structural stability and compatibility with the gate oxide layer 3, so that the gate 4 can perform better in device operation.

[0057] In the embodiment of the present application, the oxide layer covers the upper surface area of the N-type active region 6, the gate oxide layer 3, the gate 4, and the source 2 except the connection hole 7, and plays a role of insulation and protection for the covered area. The material of the oxide layer is BPSG (boron phosphorus silicon glass), and the thickness is about 1 μm.

[0058] In the embodiment of the present application, the metal layer covers the upper surface of the oxide layer and the connection hole 7, and the material of the metal layer can be AlCu (aluminum-copper alloy). AlCu has the characteristics of excellent conductivity, good compatibility with silicon-based materials, excellent processing performance, and relatively low cost. The thickness of the metal layer can be in the range of 3-4 μm.

[0059] In the embodiment of the present application, the source 2 can be connected to the metal layer through the connection hole 7 that is not covered by the oxide layer, and the electrode interconnection is formed through the metal layer.

[0060] In the embodiment of the present application, the source 2 is filled in the source trench, one side of the upper surface of the source 2 is etched downward to form a gate trench, and the gate oxide layer 3 covers the surface of the gate trench. The double-trench structure formed by the source trench and the gate trench can effectively cut off the high electric field generated by the SiC device in reverse bias operation, thereby protecting the gate oxide layer 3 from the high electric field, significantly improving the reliability of the device, and not needing to protect the gate oxide layer 3 by the Dummy trench on both sides of the gate, improving the channel utilization, thereby reducing the on-resistance of the device, increasing the current-carrying capacity of the device, and greatly reducing the process difficulty.

[0061] Based on the same inventive concept, the embodiment of the present application also provides a preparation method of a SiC MOSFET device, as shown in Figure 2 and Figure 3 , Figure 2 is a flowchart of the preparation method of the SiC MOSFET device provided by the embodiment of the present application, Figure 3 is a preparation process diagram of the SiC MOSFET device, and the preparation method of the SiC MOSFET device provided by the embodiment of the present application specifically includes the following steps:

[0062] Step S201, selecting an epitaxial silicon wafer 1.

[0063] Referring to Figure 3 (a), the selected epitaxial silicon wafer 1 is specifically an N-type epitaxial SiC wafer, and the doping concentration range is . The thickness of the epitaxial silicon wafer 1 can be about 10 μm.

[0064] Step S202, etching a source trench downward from the upper surface of the epitaxial silicon wafer 1, and filling a source 2 in the source trench.

[0065] In the embodiment of the present application, the source trench can be formed by photoetching and dry etching from the upper surface of the epitaxial silicon wafer 1 downward, as shown in Figure 3 (b). The lower surface of the source trench is arc-shaped, and the depth range is 2-3 μm, and the width range is 2-2.5 μm.

[0066] In one implementation manner, the number of source trenches is multiple, and the interval distance range between each source trench is 1.5-2 μm.

[0067] In the embodiment of the present application, the N-type doped polysilicon is filled in the source trench to form the source 2, as shown in Figure 3 (c).

[0068] In step S203 , a gate trench is formed by etching downward from one side of the upper surface of the source electrode 2 , and a gate oxide layer 3 is deposited in the gate trench; the gate oxide layer 3 is in a trench shape.

[0069] See also Figure 3 In (d), a gate trench is formed by etching downward from one side of the upper surface of the source 2 through photolithography and dry etching; wherein the depth of the gate trench is in the range of 1 to 1.5 μm, and the width of the gate trench is in the range of 1 to 1.5 μm.

[0070] In the embodiment of the present invention, the gate oxide layer 3 may be formed by depositing silicon dioxide with a thickness of 500-1000 nm in the gate trench.

[0071] Step S204 , depositing a gate 4 in the trench of the gate oxide layer 3 .

[0072] See also Figure 3 In (e), N-type doped polysilicon may be deposited in the trench of the gate oxide layer 3 by a process such as chemical vapor deposition until the polysilicon completely fills the trench of the gate oxide layer 3 to form the gate 4.

[0073] Step S205 , implanting from the top surface of the epitaxial silicon wafer 1 from bottom to top to form a P-body region 5 and an N-type active region 6 in sequence.

[0074] In the embodiment of the present invention, after the gate 4 is prepared, ion implantation is performed from the top surface of the epitaxial silicon wafer 1 to form a P-body region and an N-type active region in sequence. Figure 3 (f) in which the lower surfaces of the P-body region 5 and the N-type active region 6 are both arc-shaped.

[0075] The depth of the gate trench is greater than the total depth of the P-body region 5 and the N-type active region 6 .

[0076] Specifically, the doping element of the P body region 5 is aluminum, and the doping concentration range is , the depth range is 0.6~0.7μm, the N-type active region 6 doping element is nitrogen, and the doping concentration range is , the depth range is 0.2~0.3μm.

[0077] Step S206 , etching downward from the unetched side of the upper surface of the source 2 to form a connection hole 7 .

[0078] In the embodiment of the present invention, the connection hole 7 is formed by etching downward from the unetched side of the upper surface of the source electrode 2 by photolithography and dry etching. Figure 3 (g) in.

[0079] Step S207 , depositing an oxide layer on the upper surface areas of the N-type active region 6 , the gate oxide layer 3 , the gate electrode 4 and the source electrode 2 except for the connection hole 7 .

[0080] In the embodiment of the present application, an oxide layer is deposited on the N-type active region 6, the gate oxide layer 3, the gate electrode 4 and the source electrode 2 except the upper surface region of the connection hole 7, and the connection hole 7 is exposed.

[0081] In step S208, a metal layer is deposited on the oxide layer and the connection hole 7.

[0082] In the embodiment of the present application, an AlCu thin film is deposited on the oxide layer and the connection hole 7 by sputtering process to form the metal layer. The source electrode 2 is connected to the metal layer through the connection hole 7, and an electrode interconnection is formed through the metal layer, thus completing the preparation of the SiC MOSFET device.

[0083] In the embodiment of the present application, the source electrode 2 is filled in the source trench, and one side of the upper surface of the source electrode 2 is etched downward to form a gate trench. The gate oxide layer 3 covers the surface of the gate trench. The double-trench structure formed by the source trench and the gate trench enables the source electrode 2 to effectively cut off the high electric field generated by the SiC device in reverse bias operation, thereby protecting the gate oxide layer 3 from the high electric field, significantly improving the reliability of the device, and eliminating the need for the Dummy trench on both sides of the gate electrode to protect the gate oxide layer 3, thereby improving the channel utilization rate, reducing the on-resistance of the device, increasing the current-carrying capacity of the device, and greatly reducing the process difficulty.

[0084] It should be noted that the terms "first", "second", and so on are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the application described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of devices and methods consistent with some aspects of the present application.

[0085] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in the present specification.

[0086] Although the present application is described in conjunction with the preferred embodiments thereof, numerous modifications and alterations are possible thereby within the scope and spirit of the present application which are apparent to those skilled in the art. In the description of the present application, the term "comprising" does not exclude other components or steps, the term "a" or "an" does not exclude a plurality, and the term "multiple" means two or more, unless otherwise explicitly specified. Furthermore, some of the embodiments described herein are described as processes containing a series of steps of executing instructions to achieve a particular result. However, those skilled in the art will understand that the processes result in machine operations and / or compositions of matter having a particular property or properties within the scope and spirit of the present application.

[0087] In the description of the present application, it is to be understood that the terms "central", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like indicate relative or positional relationships based on the orientation or position shown in the drawings, and are merely used to facilitate the description of the present application and simplify the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0088] In the present application, unless otherwise explicitly specified and limited, "on" or "under" of a first feature to a second feature can include that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, "on", "above" and "over" of a first feature to a second feature includes that the first feature is directly above and obliquely above the second feature, or only means that the first feature is higher in horizontal height than the second feature. "Under", "below" and "underneath" of a first feature to a second feature includes that the first feature is directly below and obliquely below the second feature, or only means that the first feature is lower in horizontal height than the second feature.

[0089] The above is a further detailed description of the present application in conjunction with specific preferred embodiments, and cannot be considered as a limitation of the specific implementation of the present application. For those skilled in the art, without departing from the concept of the present application, a number of simple deductions or substitutions can be made, which should be considered as falling within the scope of protection of the present application.

Claims

1. A SiC MOSFET device, characterized by, The SiC MOSFET device comprises: an epitaxial silicon wafer; a P body region and an N-type active region are formed from bottom to top by implantation in the upper half of the epitaxial silicon wafer; a source trench is etched downward on the upper surface of the N-type active region, and the lower surface of the source trench extends into the unimplanted region of the epitaxial silicon wafer; the epitaxial silicon wafer is an N-type epitaxial SiC wafer; a source; the source is filled in the source trench; a gate trench is etched downward on one side of the upper surface of the source; a connecting hole is etched downward on the other side of the upper surface of the source; the source trench and the gate trench form a double-trench structure; the source is N-type doped polysilicon; a gate oxide layer; the gate oxide layer covers the surface of the gate trench; the gate oxide layer is in a trench shape; a gate; the gate is filled in the trench of the gate oxide layer; an oxide layer; the oxide layer covers the upper surface region of the N-type active region, the gate oxide layer, the gate, and the source except the connecting hole; a metal layer; the metal layer covers the upper surface of the oxide layer and the connecting hole.

2. The SiC MOSFET device of claim 1, wherein, The P body region, the N-type active region, and the lower surface of the source trench are all arc-shaped.

3. The SiC MOSFET device of claim 1, wherein, The depth of the gate trench is greater than the total depth of the P body region and the N-type active region.

4. The SiC MOSFET device of claim 1, wherein, The number of the source trenches is multiple, and the interval distance between each source trench ranges from 1.5 to 2 μm.

5. The SiC MOSFET device of claim 1, wherein, The width of the source trench ranges from 2 to 2.5 μm, and the depth of the source trench ranges from 2 to 3 μm.

6. The SiC MOSFET device of claim 1, wherein, The depth of the gate trench ranges from 1 to 1.5 μm, and the width of the gate trench ranges from 1 to 1.5 μm.

7. The SiC MOSFET device of claim 1, wherein, The doping element of the P body region is aluminum element, the doping concentration of the P body region ranges from 0.6 to 0.7 μm; the doping element of the N type active region is nitrogen element, the doping concentration of the N type active region ranges from 0.2 to 0.3 μm.

8. The SiC MOSFET device of claim 1, wherein, The doping concentration of the gate ranges from .

9. The SiC MOSFET device of claim 1, wherein, The material of the metal layer is AlCu.

10. A method of fabricating a SiC MOSFET device, characterized by, The preparation method comprises: selecting an epitaxial silicon wafer; the epitaxial silicon wafer is an N-type epitaxial SiC wafer; forming a source trench by etching downward from the upper surface of the epitaxial silicon wafer, and filling a source in the source trench; the source is N-type doped polysilicon; forming a gate trench by etching downward from one side of the upper surface of the source, and depositing a gate oxide layer in the gate trench; the gate oxide layer is in a trench shape; the source trench and the gate trench form a double-trench structure; depositing a gate in the trench of the gate oxide layer; implanting from bottom to top on the upper surface of the epitaxial silicon wafer to form a P body region and an N-type active region in sequence; forming a connecting hole by etching downward from the unetched side of the upper surface of the source; depositing an oxide layer on the upper surface region of the N-type active region, the gate oxide layer, the gate, and the source except the connecting hole; depositing a metal layer on the oxide layer and the connecting hole.

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