Method for forming interconnection structure

Abstract

A method of forming a device includes forming a dielectric layer on a substrate, the dielectric layer including at least one feature defining a gap, the feature including sidewalls and a bottom. A self-assembled monolayer (SAM) is formed at the bottom of the gap that is resistant to degradation when exposed to ambient atmosphere. A barrier layer is selectively deposited on the sidewalls of the gap rather than on the bottom. The SAM is removed after the barrier layer is selectively deposited on the sidewalls.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to methods for forming interconnect structures in microelectronic devices formed on substrates in a processing chamber. More specifically, embodiments of the present disclosure relate to methods for improving the selective deposition of metal on dielectric surfaces during the formation of interconnect structures in microelectronic devices in processes in which the substrates are exposed to air during processing. Background Art

[0002] When scaling transistors and interconnects to the 3nm node and beyond, multiple challenges hinder improvements in power consumption and performance. Interconnects include metal lines, which carry current within the same device layer, and metal vias, which carry current between layers. Decreasing pitch shrinks the width and increases resistance of both, which in turn increases voltage drop across the circuit, throttling circuit speed and increasing power consumption.

[0003] While transistor performance improves with shrinking dimensions, the same cannot be said for interconnect metal. Interconnect via resistance can increase by a factor of 10 with shrinking dimensions. This increase in interconnect via resistance can lead to resistance-capacitance (RC) delays, which can degrade performance and increase power consumption. Traditional copper interconnect structures include a barrier layer deposited on the sidewalls of the gap. This layer provides a dielectric sidewall that provides good adhesion and prevents copper diffusion into the dielectric layer and other adverse interactions between dielectric layers. It can also include a metal liner deposited on the barrier layer. When present, the metal liner deposited on the barrier layer adheres to the barrier layer and facilitates subsequent copper (Cu) filling of the gap between the sidewalls. Copper is deposited into the remaining volume of the gap. Due to its high resistivity, the barrier layer can often be the largest contributor to via resistance. Past approaches have focused on reducing the thickness of the barrier layer or finding barrier layers with lower resistivity to reduce via resistance. As the percentage of via volume formed by the barrier layer on the sidewalls continues to increase, especially in smaller features, increased via resistance remains a concern.

[0004] During the manufacture of microelectronic devices, substrates are typically processed in multiple substrate processing chambers to form various layers. The entire manufacturing process can be performed while processing the substrate under vacuum conditions and avoiding exposure to the ambient atmosphere, or what may be referred to as an "airbreak." However, such processing may introduce limitations and additional costs during manufacturing. Flexibility in the manufacturing process flow may be desirable, wherein the substrate is removed from vacuum conditions and exposed to ambient conditions. Therefore, a method for depositing material layers during the formation of interconnect structures is needed, wherein the substrate is exposed to ambient conditions or air. Summary of the Invention

[0005] Embodiments of the present disclosure relate to methods for forming microelectronic devices. In one or more embodiments, the method includes: forming a dielectric layer on a substrate, the dielectric layer including at least one feature defining a gap, the feature including sidewalls and a bottom including a metal surface; selectively depositing a self-assembled monolayer (SAM) on the bottom of the gap and the metal surface, the SAM including densely packed molecules on the metal surface, the densely packed molecules protecting the metal surface from exposure to an ambient atmosphere; selectively depositing a barrier layer on the sidewalls but not on the metal surface; and removing the SAM after selectively depositing the barrier layer on the sidewalls. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The features of the present invention have been briefly summarized above and discussed in more detail below, and can be understood by reference to the embodiments of the present invention illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, as the invention may admit to other equally effective embodiments.

[0007] Figure 1A depicts a portion of a microelectronic device having a metal surface on a bottom of a gap during a manufacturing stage according to one embodiment;

[0008] Figure 1B A diagram illustrating a self-assembled monolayer on a metal surface according to an embodiment. Figure 1A device;

[0009] Figure 1C Draw Figure 1A The self-assembled monolayer on the metal surface shown is exposed to the ambient atmosphere;

[0010] Figure 1D Draw on Figure 1A a barrier layer formed on the sidewalls of the gap of the device shown;

[0011] Figure 1E Draw Figure 1D removal of the self-assembled monolayer; and

[0012] Figure 2 A process flow diagram of a method of fabricating a microelectronic device according to one or more embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0013] Before describing several exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of construction or processing steps set forth in the following description. The present disclosure is capable of other embodiments and can be practiced or carried out in various ways.

[0014] As used in this specification and the appended claims, the terms "substrate" and "wafer" are used interchangeably and both refer to a surface or portion of a surface upon which a process is performed. Those skilled in the art will also understand that, unless the context clearly indicates otherwise, reference to a substrate may also refer to only a portion of a substrate. Additionally, reference to deposition on a substrate may refer to both a bare substrate and a substrate having one or more films or features deposited or formed thereon.

[0015] As used herein, "substrate" refers to any substrate or material surface formed on a substrate to which film processing is applied during a manufacturing process. For example, substrate surfaces on which processing is performed include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other material (such as metals, metal nitrides, metal alloys, and other conductive materials), depending on the application. Substrates include, but are not limited to, semiconductor wafers. The substrate can be exposed to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate (or otherwise create or implant target chemical groups to impart chemical functionality), anneal, and / or bake the substrate surface. In addition to direct film processing directly on the substrate surface itself, any of the film processing steps disclosed in this disclosure may also be performed on an underlayer formed on the substrate, as disclosed in more detail below, and the term "substrate surface" is intended to include such an underlayer as indicated by the context. Thus, for example, where a film / layer or portion of a film / layer is already deposited on a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface. What a given substrate surface contains will depend on the film to be deposited and the specific chemistry used.

[0016] As used in this specification and the appended claims, the terms "reactant gas," "precursor," "reactant," and the like are used interchangeably to refer to a gas that includes a species that reacts with a substrate surface. For example, a first "reactant gas" may simply adsorb onto the surface of a substrate and be available for further chemical reaction with a second reactant gas.

[0017] Some embodiments of the present disclosure provide methods for improving the performance of interconnects. The interconnects include metal lines that carry current within the same device layer and metal vias that carry current between layers. These lines and vias are formed in gaps formed within the device by conductive metals (such as copper or cobalt). In one or more embodiments, the dielectric layer includes at least one feature defining the gap, the feature including sidewalls and a bottom. In one or more embodiments, the gap includes metal lines and metal vias. In one or more embodiments, the metal lines have sidewalls and a bottom. In one or more embodiments, the metal vias have sidewalls and a bottom. As used in this specification and the appended claims, unless otherwise indicated, reference to the "bottom of the gap" is intended to mean the bottom of the metal via closest to the substrate.

[0018] As technology nodes advance, for example, as microelectronic devices and interconnects scale to the 3nm node and beyond, the thickness budget for barrier and liner layers for metal interconnects decreases. One solution is to provide bottomless via barriers and liners to reduce via resistance. Current solutions use self-assembled monolayers (SAMs) to inhibit nucleation and growth at the bottom of the via. However, in many processes, the substrate is continuously under vacuum or "load lock" conditions and is not exposed to an ambient atmosphere containing air when the substrate is moved from one chamber to the next. The transfer chamber is under vacuum and "pumped down" at vacuum pressure. An inert gas may be present in the processing chamber or transfer chamber. Such processing under constant vacuum throughout the process is not always possible, and there may be processes and manufacturing flows that would benefit from exposing the substrate to an ambient atmosphere containing air where the vacuum conditions are broken.

[0019] However, it has been found that certain SAM molecules are air sensitive, and the performance of air-sensitive SAMs degrades when there is a vacuum break during substrate processing. This is an obstacle to extending integrated processes to processes that require or prefer a vacuum break, in which the substrate is exposed to ambient conditions after the SAM is deposited on the metal surface at the bottom of the gap and before the barrier layer is selectively deposited on the gap sidewalls.

[0020] Embodiments of the present disclosure provide methods for fabricating microelectronic devices in which a SAM is chemically inert to the surrounding environment and stable under standard atmospheric conditions. By providing a process for utilizing air to stabilize the SAM, substrates having SAMs deposited on metal surfaces can be processed during a vacuum break, thereby increasing the flexibility of integrated process flows. Applicants have discovered that selecting SAM molecules that exhibit a high packing density on the metal surface prevents the SAM from degrading when exposed to a vacuum break. When the SAM is exposed to air, the SAM molecules resist degradation.

[0021] While the claims of this disclosure should not be limited by a particular theory, it is believed that for existing SAM molecules deposited on the metal surface at the bottom of the gap, the packing density of the SAM on the metal surface is greatly limited by the steric hinderance of the SAM molecules because the binding groups are not terminal. When exposed to a vacuum break, air in the ambient atmosphere triggers chemical interactions with the SAM molecules, thereby degrading the SAM and preventing optimal selective deposition of the barrier material on the sidewalls of the gap. In contrast, the SAM molecules described herein were determined to have head groups that bind to the metal surface, and the SAM molecules are densely packed on the metal surface. It was determined that these SAM molecules are more stable when exposed to an ambient atmosphere containing air, thereby enhancing the selective deposition of the barrier material on the sidewalls of the gap. In some embodiments, the metal surface comprises copper. In other embodiments, the metal surface is tungsten.

[0022] Embodiments of the present disclosure provide methods for forming interconnect structures in the manufacture of microelectronic devices. In one or more embodiments, the microelectronic devices described herein include at least one top interconnect structure interconnected to at least one bottom interconnect structure. Embodiments of the present disclosure provide microelectronic devices and methods for manufacturing microelectronic devices that improve interconnect performance, such as reducing through-hole resistance.

[0023] References Figures 1A-1E Methods of forming microelectronic devices are described. Figure 2 It's about Figures 1A-1E A flow chart of an exemplary method of forming a microelectronic device.

[0024] refer to Figures 1A-1E, depicts a portion of a microelectronic device 100 during a manufacturing stage, wherein the substrate is in a substrate processing chamber, such as an atomic layer deposition processing chamber, a chemical vapor deposition processing chamber, a cyclic vapor deposition processing chamber, or a pre-cleaning chamber. In one or more embodiments, the substrate processing chamber includes a local plasma source, a remote plasma source, or both. In some embodiments, the plasma source includes an inductively coupled plasma source or a capacitively coupled plasma source.

[0025] In one aspect, a method includes forming a dielectric layer on a substrate, the dielectric layer including at least one feature defining a gap, the feature including sidewalls and a bottom including a metal surface, selectively depositing a self-assembled monolayer (SAM) on the bottom of the gap and the metal surface, the metal surface being resistant to degradation in an ambient atmosphere, selectively depositing a barrier layer on the sidewalls but not on the metal surface, and removing the SAM after selectively depositing the barrier layer on the sidewalls.

[0026] exist Figure 1A In the embodiment, microelectronic device 100 includes substrate 110, barrier layer 120 on substrate 110, conductive filled gap 140, aluminum oxide etch stop layer 142, dielectric layer 145 on aluminum oxide etch stop layer 142, dielectric layer 145 including at least one feature defining gap 146, the feature including sidewalls 148 and bottom 149. According to one or more embodiments, metal surface 131 is at bottom 149 of gap. It should be understood that, in one or more embodiments, conductive filled gap 140 forms a metal line that carries current within the same device layer.

[0027] In one or more embodiments, substrate 110 is a wafer, such as a semiconductor substrate. In one or more embodiments, substrate 110 is an etch stop layer on a wafer. In one or more embodiments, substrate 110 is an aluminum oxide etch stop layer on a wafer. In one or more embodiments, barrier layer 120 comprises tantalum nitride (TaN) or doped TaN. In one or more embodiments, barrier layer 120 comprises tantalum nitride (TaN) formed by ALD. In one or more embodiments, conductive fill gap 140 comprises one or more of copper (Cu), cobalt (Co), or tungsten (W). In one or more embodiments, etch stop layer 142 comprises one or more of aluminum oxide, silicon nitride, and aluminum nitride.

[0028] In one or more embodiments, dielectric layer 145 is a low-k dielectric layer. In certain embodiments, dielectric layer 145 comprises silicon oxide (SiO x In one or more embodiments, the dielectric layer 145 includes SiO x H y (CHz ). Other embodiments provide that the dielectric layer 145 comprises porous or carbon-doped SiO x In some embodiments, dielectric layer 145 is a porous or carbon-doped SiO2 layer having a k value of less than about 5. x In other embodiments, the dielectric layer 145 is a multi-layer structure. For example, in one or more embodiments, the dielectric layer 145 includes a multi-layer structure including one or more of a dielectric layer, an etch stop layer, and a hard mask layer.

[0029] In one or more embodiments, dielectric layer 145 includes at least one feature defining gap 146, the feature including sidewalls 148 and a bottom 149. For illustrative purposes, the figures show a substrate having a single feature, however, one of ordinary skill in the art will understand that there may be more than one feature. The shape of the feature can be any suitable shape, including but not limited to a trench, a cylindrical via that conducts current between layers when filled with metal, and a line that conducts current within the same device layer. In some embodiments, this feature defines gap 146 in dielectric layer 145. In some embodiments, gap 146 defines a via portion 146V and a line portion 146L, but the embodiments shown are not intended to be limiting. As used herein, the term "feature" refers to any intentional surface irregularity. Suitable examples of features include but are not limited to a trench having a top, two sidewalls, and a bottom, a peak having a top and two sidewalls. The feature can have any suitable aspect ratio (the ratio of the depth of the feature to the width of the feature). In some embodiments, the aspect ratio is greater than or equal to about 5:1, 10:1, 15:1, 20:1, 25:1, 30:1, 35:1, or 40:1.

[0030] refer to Figure 1B , a passivation layer (such as a self-assembled monolayer (SAM)) 150 is formed on the metal surface. In one or more embodiments, the SAM 150 is formed on the metal surface 131. The SAM 150 is deposited by exposing the bottom 149 of the gap to a hydrocarbon or silane carried in an inert carrier gas (such as argon (Ar) gas). In one or more embodiments, the SAM 150 comprises a silane or an unsaturated hydrocarbon as further described herein. The SAM blocks the deposition of the barrier layer on the metal surface. In some embodiments, after the SAM has been exposed to an ambient atmosphere other than vacuum, the SAM molecules described herein provide a 100% block of the deposition barrier layer on the metal surface. In some embodiments, the barrier layer comprises a layer of tantalum nitride (TaN), doped TaN, or ruthenium (Ru).

[0031] It has been discovered that certain SAM molecules, such as those comprising the hydrocarbon formula R1-C≡C-R2, wherein R1 and R2 are linear alkyl chains, and particularly identical linear alkyl chains having 5-15 carbon atoms, cause SAM degradation and inhibited deposition of the barrier layer on the metal surface upon exposure of the substrate having the SAM deposited on the metal surface 131. This results in less selective deposition of the barrier layer and results in the barrier layer being deposited on the metal surface. Experiments have determined that when the SAM molecule is 5-decyne, the SAM exhibits degradation upon exposure to ambient atmosphere, and during deposition of a TaN barrier layer in a gap, a thick TaN layer is formed on the metal surface comprising copper, nearly four times thicker than when a SAM resistant to degradation is deposited and exposed to ambient atmosphere.

[0032] According to one or more embodiments, selectively depositing the SAM comprises exposing the bottom of the gap to a silane or hydrocarbon having the formula HC≡C-R3, wherein R3 is a linear alkyl chain containing 1 to 20 carbon atoms. In other embodiments, the silane has the formula R-SiH3, wherein R is selected from a linear alkyl chain and a branched alkyl chain containing 2 to 20 carbon atoms.

[0033] In some embodiments, the substrate is immersed in a vapor of an unsaturated hydrocarbon or silane. In some embodiments, the processing conditions for exposing the substrate to the unsaturated hydrocarbon or silane can be controlled.

[0034] In some embodiments, the pressure of the processing chamber is controlled. The pressure of the processing chamber can be any suitable pressure for forming the barrier layer. In some embodiments, the pressure of the processing chamber is maintained at less than or equal to about 80 Torr, less than or equal to about 70 Torr, less than or equal to about 60 Torr, less than or equal to about 50 Torr, less than or equal to about 40 Torr, less than or equal to about 30 Torr, less than or equal to about 20 Torr, less than or equal to about 15 Torr, less than or equal to about 10 Torr, or less than or equal to about 5 Torr. In some embodiments, the pressure of the processing chamber is maintained at about 10 Torr, about 20 Torr, about 30 Torr, about 40 Torr, or about 50 Torr.

[0035] In one or more embodiments, the flow of argon (Ar) gas is configured to carry the unsaturated hydrocarbon or silane from the container to the processing chamber. In some embodiments, the flow rate of the argon (Ar) gas configured to carry the unsaturated hydrocarbon or silane into the processing chamber is controlled. The flow rate of the argon (Ar) gas can be any suitable flow rate for forming the passivation layer. In some embodiments, the flow rate of the argon (Ar) gas is in the range of about 50 sccm to about 100 sccm, or in the range of about 75 sccm to about 100 sccm. In one or more embodiments, the flow rate of the argon (Ar) gas is about 600 sccm. In some embodiments, the flow rate of argon (Ar) is less than or equal to about 600 sccm, less than or equal to about 500 sccm, less than or equal to about 400 sccm, less than or equal to about 300 sccm, less than or equal to about 250 sccm, less than or equal to about 200 sccm, less than or equal to about 150 sccm, less than or equal to about 100 sccm, less than or equal to about 75 sccm, or less than or equal to about 50 sccm.

[0036] In some embodiments, the soak period during which the unsaturated hydrocarbon or silane is exposed to the substrate is controlled. The soak period can be any suitable time for forming the barrier layer. In certain embodiments, the soak period is greater than or equal to about 10 seconds, greater than or equal to about 20 seconds, greater than or equal to about 30 seconds, greater than or equal to about 45 seconds, greater than or equal to about 60 seconds, greater than or equal to about 80 seconds, greater than or equal to about 120 seconds, greater than or equal to about 150 seconds, or greater than or equal to about 200 seconds. In some embodiments, the soak period is about 40 seconds. In some embodiments, the soak period is about 200 seconds.

[0037] In one or more embodiments, when the unsaturated hydrocarbon or silane is in a container (such as an ampoule or a measuring cylinder), the unsaturated hydrocarbon or silane is in a liquid phase and the unsaturated hydrocarbon or silane is transported from the container to the chamber in a carrier gas. In some embodiments, when the container has a pressure of about 0.1 Torr, the unsaturated hydrocarbon or silane is in a saturated gas phase in the container. In one or more embodiments, the temperature of the container is lower than the temperature in the processing chamber. In one or more embodiments, a carrier gas (such as argon (Ar) gas) carries the unsaturated hydrocarbon or silane in the saturated gas phase from the container to the processing chamber. In some embodiments, the temperature of the processing chamber is controlled during exposure to the unsaturated hydrocarbon or silane. The temperature of the processing chamber may also be referred to as the operating temperature. In some embodiments, the temperature of the processing chamber is in the range of about 200°C to about 450°C. In some embodiments, the temperature of the processing chamber is less than or equal to about 300°C, less than or equal to about 275°C, less than or equal to about 250°C, less than or equal to about 225°C, or less than or equal to about 200°C.

[0038] refer to Figure 1C After the SAM 150 has been deposited on the metal surface, the microelectronic device 100 including the SAM 150 is exposed to the ambient atmosphere, and molecules 133 in the ambient atmosphere, such as H2O and O2, interact with the SAM 150. According to an embodiment of the present disclosure, when the SAM 150 is a silane having the chemical formula R—SiH3, where R is selected from linear and branched alkyl chains containing 2 to 20 carbon atoms, or a hydrocarbon having the chemical formula HC≡C—R3, where R3 is a linear alkyl chain containing 1 to 20 carbon atoms, the chemical interaction of H2O in the ambient environment with the metal surface 131 is prevented by the dense packing of the SAM 150.

[0039] refer to Figure 1D , barrier layer 160 is shown on SAM 150 and above sidewalls 148. In one or more embodiments, barrier layer 160 has the same properties as barrier layer 120. In one or more embodiments, when SAM 150 is not present, the deposition of barrier layer 160 is substantially conformal. As used herein, a "substantially conformal" layer refers to a layer having a thickness that is approximately the same throughout (e.g., on the top, middle, and bottom of sidewalls 148 and at bottom 149 of gap 146). A substantially conformal layer has a thickness variation of less than or equal to about 5%, 2%, 1%, or 0.5%.

[0040] In one or more embodiments, barrier layer 160 is formed on sidewalls 148 and substantially prevents barrier layer 160 from forming on metal surface 131 at bottom 149 of gap 146. In one or more embodiments, barrier layer 160 is formed on sidewalls 148 but not on metal surface 131 at bottom 149 of gap 146. In some embodiments, the SAM molecules described herein completely prevent barrier layer 160 from forming on metal surface 131 at the bottom of gap 146, and no barrier layer 160 material is deposited on the metal surface. In one or more embodiments, barrier layer 160 is selectively deposited on at least a portion of sidewalls 148. In one or more embodiments, barrier layer 160 may cover the entire sidewalls 148.

[0041] Embodiments significantly improve SAM selectivity and eliminate the formation of a thick TaN barrier layer or a Ru barrier layer on the metal surface 131. In some embodiments, this results in a significant reduction in via resistance.

[0042] In one or more embodiments, the barrier layer 160 is selectively deposited by atomic layer deposition (ALD) and has a thickness of about to about In some embodiments, the barrier layer 160 is deposited in a single ALD cycle. In other embodiments, the barrier layer 160 is deposited in 1 to 20 ALD cycles. In one or more embodiments, each of the 1 to 20 ALD cycles is configured to deposit a thickness of about barrier layer 160.

[0043] In a typical ALD process, alternating pulses or flows of an "A" precursor and a "B" precursor can be used to deposit a film. The surface continues to be exposed to reactants "A" and "B" alternately until a film of desired thickness is achieved. However, instead of pulsing the reactants, gases can be flowed simultaneously from one or more gas delivery heads or nozzles, and the substrate and / or gas delivery heads can be moved so that the substrate is exposed to each of the reactant gases sequentially. Of course, the above-described ALD cycles are merely examples of a variety of ALD process cycles in which deposited layers are formed from alternating layers of precursors and co-reactants.

[0044] In one or more embodiments, the reactants and / or co-reactants are in vapor or gaseous form. The reactants may be delivered using a carrier gas. The carrier gas, purge gas, deposition gas, or other process gas may comprise nitrogen, hydrogen, argon, neon, helium, or a combination thereof. The various plasmas described herein (e.g., nitrogen plasma or inert gas plasma) may be ignited by and / or comprise a plasma co-reactant gas.

[0045] In one or more embodiments, the various gases used in the process can be pulsed into an inlet, passed through the gas channel, and then out of the multiple holes or outlets and into the central channel. In one or more embodiments, the deposition gases can be pulsed sequentially to and through the showerhead. Alternatively, as described above, the gases can flow simultaneously through the gas supply showerhead or heads, and the substrate and / or gas supply head can be moved so that the substrate is exposed to the gases sequentially.

[0046] In one or more embodiments, the barrier layer material and the SAM are deposited using a multi-chamber process, wherein the barrier layer material (e.g., tantalum nitride (TaN)) is deposited in a separate second substrate processing chamber after the substrate 110 is removed from a first substrate processing chamber in which the SAM 150 has been deposited and exposed to ambient atmosphere.

[0047] Some embodiments of the present invention relate to barrier applications, such as copper barrier applications. The barrier layer formed by one or more embodiments can be used as a copper barrier. Suitable barrier layers for copper barrier applications include, but are not limited to, TaN and MnN. For copper barrier applications, suitable dopants include, but are not limited to, Ru, Cu, Co, Mn, Al, Ta, Mo, Nb, V, or combinations thereof. Plasma treatment can be used after doping to promote the formation of intermetallic compounds between the matrix and the dopant, remove film impurities, and increase the density of the barrier layer. In other embodiments, post-treatment can include, but is not limited to, physical vapor deposition (PVD) treatment, thermal annealing, chemical enhancement, and the like. In some copper barrier applications, a high-frequency plasma (defined as greater than approximately 14 MHz or approximately 40 MHz or higher) can be used with any inert gas, including, but not limited to, one or more of neon (Ne), hydrogen (H2), and argon (Ar). In one or more embodiments, a higher plasma frequency (greater than 13.56 MHz) can be used to prevent low-k damage. In some embodiments, the barrier layer is a copper barrier layer and includes Ru-doped TaN.

[0048] refer to Figure 1E In one or more embodiments, the methods described herein have been used to Figure 1D In one or more embodiments, the SAM 150 is removed from the structure shown in FIG. In one or more embodiments, the SAM 150 is removed. In one or more embodiments, the SAM 150 is removed by a plasma treatment process including flowing one or more of hydrogen (H2) or argon (Ar). In one or more embodiments, the plasma treatment process includes increasing the density of the barrier layer 160. In one or more embodiments, the gap filling process includes filling the barrier layer 160 with one or more of copper (Cu) or cobalt (Co). Figure 1E Gap 146 is shown.

[0049] Figure 2 A process flow diagram of a method 300 for forming a microelectronic device is shown. Figure 2 Drawing Formation Figures 1A-1E A method for any microelectronic device according to one or more embodiments of the present invention. Figure 2Method 300 includes, at operation 310, forming a dielectric layer on the substrate. The dielectric layer includes at least one feature defining a gap, the feature including sidewalls and a bottom. At operation 320, method 300 includes selectively depositing a self-assembled monolayer (SAM) at the bottom of the gap. Specifically, the SAM is a silane having the chemical formula R—SiH 3 , where R is selected from a linear alkyl chain and a branched alkyl chain containing 2 to 20 carbon atoms, or a hydrocarbon having the chemical formula HC≡C—R 3 , where R 3 is a linear alkyl chain containing 1 to 20 carbon atoms. At operation 330, method 300 includes, for example, removing substrate 110 from a substrate processing chamber in which SAM 150 is deposited on metal surface 131 to expose substrate 110 and SAM 150 to an ambient atmosphere including air.

[0050] At operation 340, method 300 includes forming a barrier layer on sidewalls 148. At operation 340, method 300 includes selectively depositing a barrier layer 160 on sidewalls 148 of gap 146. At operation 340, in some embodiments, barrier layer 160 is deposited at a thickness on the sidewalls but not on metal surface 131. At operation 350, method 300 includes removing the SAM after selectively depositing barrier layer 160 on sidewalls 148. At operation 360, method 300 includes performing a gapfill process in gap 146. The gapfill process may include forming one or more of vias and lines to form interconnects in the device.

[0051] In one or more embodiments, the methods described herein include an optional post-processing operation. The optional post-processing operation can be, for example, a process that modifies film properties (such as annealing) or a further film deposition process (such as an additional ALD or CVD process) to grow additional films. In some embodiments, the optional post-processing operation can be a process that modifies the properties of the deposited film. In some embodiments, the optional post-processing operation includes annealing the as-deposited film. In some embodiments, the annealing is performed at a temperature in the range of about 300°C, 400°C, 500°C, 600°C, 700°C, 800°C, 900°C, or 1000°C. The annealing environment of some embodiments includes one or more of the following: an inert gas (such as molecular nitrogen (N2), argon (Ar)) or a reducing gas (such as molecular hydrogen (H2) or ammonia (NH3)) or an oxidant (such as, but not limited to, oxygen (O2), ozone (O3), or a peroxide). The annealing can be performed for any suitable length of time. In some embodiments, the film is annealed for a predetermined time in a range from about 15 seconds to about 90 minutes, or in a range from about 1 minute to about 60 minutes.

[0052] In some embodiments, the substrate is moved from the first chamber to a separate, next chamber for further processing. The substrate can be moved directly from the first chamber to a separate processing chamber, or the substrate can be moved from the first chamber to one or more transfer chambers and then to a separate processing chamber. In some embodiments, the deposition of the barrier layer and the dopant film can be completed in a single chamber, and then post-processing can be performed in separate chambers. Thus, the processing equipment can include multiple chambers connected to a transfer station. Such equipment can be referred to as a "cluster tool" or a "cluster system," etc. However, as described herein, after the SAM 150 is deposited, the substrate 110 is exposed to the ambient environment to move the substrate 110 having the SAM 150 on the metal surface 131 to another chamber for deposition of the barrier layer 160.

[0053] In general, a cluster tool is a modular system that includes multiple chambers that perform various functions, including substrate centering and orientation, degassing, annealing, deposition, and / or etching. According to one or more embodiments, the cluster tool includes at least a first chamber and a central transfer chamber. The central transfer chamber can accommodate a robot that can shuttling substrates between processing chambers and a load lock chamber. The transfer chamber is typically maintained under vacuum conditions and provides an intermediate stage for shuttling substrates from one chamber to another and / or to a load lock chamber located at the front end of the cluster tool. However, the exact arrangement and combination of chambers can be varied to perform specific steps of the processes described herein. Other process chambers that can be used include, but are not limited to, cyclic deposition including a deposition step and an annealing or treatment step, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etching, pre-cleaning, chemical cleaning, plasma nitridation, degassing, orientation, hydroxylation, and other substrate processes.

[0054] During processing, the substrate may be heated or cooled. This heating or cooling may be achieved by any suitable means, including but not limited to changing the temperature of the substrate support and flowing a heated or cooled gas to the substrate surface. In some embodiments, the substrate support includes a heater / cooler that can be controlled to change the substrate temperature by conduction. In one or more embodiments, the gas (reactive gas or inert gas) used is heated or cooled to locally change the substrate temperature. In some embodiments, the heater / cooler is positioned within the chamber adjacent to the substrate surface to change the substrate temperature by convection.

[0055] During processing, the substrate can also be stationary or rotated. The rotating substrate can be rotated continuously or in discrete steps (about the substrate axis). For example, the substrate can be rotated throughout the process, or the substrate can be rotated a small amount between exposures to different reactant or purge gases. Rotating the substrate during processing (either continuously or in steps) can help produce a more uniform deposition or etching by minimizing the effects of local variations in, for example, gas flow geometry.

[0056] Another aspect of the present disclosure relates to a non-transitory computer-readable medium comprising instructions that, when executed by a controller of a processing system, cause the processing system to perform the operations of the method described herein. In one embodiment, another aspect of the present disclosure relates to a non-transitory computer-readable medium comprising instructions that, when executed by a controller of a processing system, cause the processing system to perform the operations of the method described herein. Figures 1A to 1E and Figure 2 The operation of the method described.

[0057] References throughout this specification to "one embodiment," "certain embodiments," "one or more embodiments," or "an embodiment" refer to a particular feature, structure, material, or characteristic described in connection with that embodiment that is included in at least one embodiment of the present disclosure. Thus, phrases such as "in one or more embodiments," "in certain embodiments," "in one embodiment," or "in an embodiment" appearing throughout this specification are not necessarily referring to the same embodiment of the present disclosure. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0058] Although the present disclosure has been described with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It will be apparent to one skilled in the art that various modifications and variations can be made to the methods and apparatus of the present disclosure without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure is intended to include modifications and variations within the scope of the appended claims and their equivalents.

Claims

1. A method of forming a microelectronic device, the method comprising: forming a dielectric layer on the substrate, the dielectric layer comprising at least one feature defining a gap, the feature comprising sidewalls and a bottom including a metal surface; selectively depositing a self-assembled monolayer (SAM) on the bottom of the gap and on the metal surface, the SAM comprising densely packed molecules on the metal surface, the densely packed molecules protecting the metal surface from exposure to ambient atmosphere; selectively depositing a barrier layer on the sidewalls but not on the metal surface; and The SAM is removed after selectively depositing the barrier layer on the sidewalls.

2. The method of claim 1 , wherein the substrate is in a first substrate processing chamber and the SAM is selectively deposited in the first substrate processing chamber, and the method further comprises: The substrate is removed from the first substrate processing chamber and the substrate and the SAM are exposed to the ambient atmosphere.

3. The method of claim 2, further comprising: The barrier layer is selectively deposited on the sidewalls in a second substrate processing chamber separate from the first substrate processing chamber.

4. The method of claim 3, wherein the SAM resists degradation when the SAM is exposed to air.

5. The method of claim 4, wherein the SAM is selected from the group consisting of silanes and hydrocarbons.

6. The method of claim 3, wherein selectively depositing the SAM comprises: The bottom of the gap is exposed to a silane or hydrocarbon having the chemical formula HC≡C-R3, wherein R3 is a linear alkyl chain containing 1 to 20 carbon atoms.

7. The method of claim 6, wherein the silane has the chemical formula R-SiH3, wherein R is selected from the group consisting of linear and branched alkyl chains containing 2 to 20 carbon atoms.

8. The method of claim 7, wherein the silane resists degradation when the silane is exposed to air.

9. The method of claim 6, wherein the hydrocarbon has the chemical formula HC≡C-R3.

10. The method of claim 9, wherein the hydrocarbon resists degradation when exposed to air.

11. The method of claim 5, wherein the SAM prevents deposition of the barrier layer on the metal surface after the substrate has been exposed to the ambient atmosphere.

12. The method of claim 11, wherein the metal surface comprises Cu. The method of claim 12 , wherein the barrier layer comprises TaN. The method of claim 12 , wherein the barrier layer comprises doped TaN. The method of claim 12 , wherein the barrier layer comprises Ru.

16. The method of claim 1, wherein the SAM is deposited by atomic layer deposition. The method of claim 16 , wherein the barrier layer is deposited by atomic layer deposition.

18. The method of claim 17, wherein removing the SAM comprises: The SAM is exposed to plasma.

19. The method of claim 18, wherein the plasma is an inductively coupled plasma.

20. The method of claim 18, wherein the plasma is a capacitively coupled plasma.

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