Selective deposition method enabling high dopant incorporation

Abstract

A method for forming a doped layer is disclosed. The doped layer can be used in NMOS or silicon germanium applications. For example, a halide precursor can be used to create a doped layer in an n-type dopant application.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to selective deposition of semiconductor films on substrates. More specifically, the present disclosure relates to selective deposition with dopants. Dopant precursors can include hydrides and halogenated Group V elements. BACKGROUND

[0002] For logic applications, FinFET transistors have been made through epitaxial deposition processes. Dopants have been used to match specific channel types, such as n-type dopant layers for NMOS applications. Specific n-type layers formed can include, for example, silicon carbide (SiC), silicon carbon phosphide (SiCP), and silicon phosphide (SiP).

[0003] When grown on substitutional lattice sites, it can be difficult to form the layers. There can be issues that can result in at least one of selectivity, growth rate, dopant concentration, and resistivity of the sacrificial growth layers. For example, to achieve a specific selectivity to the layers, a flow of a specific chemical or a reduction in process temperature can be required, which can adversely affect the growth rate and / or dopant incorporation of the layers.

[0004] Accordingly, it would be desirable to develop a process that allows for optimal growth rates of the doped layers while achieving the desired selectivity and geometry of the doped layers. SUMMARY

[0005] This Summary is provided to introduce a selection of concepts in a simplified form. These concepts are described in greater detail below in the detailed description of example embodiments of the disclosure. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

[0006] A method for forming a contact layer is disclosed. The method can include: removing any oxide of a device on a semiconductor substrate, the semiconductor substrate disposed on a susceptor in a reaction chamber; stabilizing a temperature of the reaction chamber; flowing a halide precursor onto the device, the halide precursor comprising at least one of: hydrogen fluoride (HF); hydrogen chloride (HCI); hydrogen bromide (HBr); hydrogen iodide (HI); chlorine (CI2); fluorine (F2); bromine (Br2); or iodine (I2); flowing a silicon precursor onto the device, the silicon precursor comprising at least one of: silane (SiH4); dichlorosilane (DCS); disilane; or trisilane; and flowing a dopant precursor onto the device, the dopant precursor comprising at least one of: PCI3; PCI5; PBr3; PBr5; PI3; PI5; AsCI3; AsCI5; AsBr3; AsBr5; AsI3; AsI5; SbCI3; SbCI5; SbBr3; SbBr5; SbI3; SbI5; arsine (AsH3); or phosphine (PH3); wherein the halide precursor prevents deposition onto a dielectric layer disposed on the semiconductor substrate; wherein the silicon precursor and the dopant precursor react to form a contact layer; wherein any of the flowing steps are repeated to form a desired thickness of the contact layer. BRIEF DESCRIPTION OF DRAWINGS

[0007] These and other features, aspects, and advantages of the presently disclosed invention will be described below with reference to the accompanying drawings of certain embodiments, which are intended to illustrate, but not limit, the present invention.

[0008] Figure 1 A cross-sectional view of an NMOS device formed in accordance with at least one embodiment of the present invention.

[0009] Figure 2 A process flow diagram in accordance with at least one embodiment of the present invention.

[0010] Figure 3 An apparatus in accordance with at least one embodiment of the present invention is illustrated.

[0011] It is to be understood that the elements of the figures are illustrated for simplicity and clarity and that they are not necessarily drawn to scale. For example, the dimensions of some of the elements in the figures can be exaggerated relative to other elements to help improve the DETAILED DESCRIPTION

[0012] While certain embodiments and examples are disclosed below, one skilled in the art will understand that the present invention extends beyond the specifically disclosed embodiments and / or uses and obvious modifications and equivalents thereof. Thus, it is intended that the scope of the present invention herein disclosed should not be limited by the particular disclosed embodiments described above.

[0013] The illustrations presented herein are not meant to be actual views of any particular material, structure or device, but are merely idealized representations that describe the embodiments of the present disclosure.

[0014] For FinFET applications, a contact layer can be needed on top of the fin (Fin). For silicon germanium (SiGe) applications, a contact layer can also be grown. For the contact layer in certain NMOS applications, it can be desirable to incorporate a high level of n-type dopant. This can increase the electrical active behavior of the contact layer.

[0015] Figure 1 A device 100 is illustrated in accordance with at least one embodiment of the present application. The device 100 can include a fin 110, a shallow trench isolation (STI) layer 120, a contact layer 130, and a gate 140. The fin 110 can be a stack of lateral nanowires comprising at least one of: silicon, germanium, silicon germanium, or a combination thereof. The STI layer 120 can comprise, for example, a dielectric material such as silicon oxide, silicon oxynitride, silicon oxycarbide, and combinations thereof. The gate 140 can also comprise, for example, an oxide material such as hafnium oxide or aluminum oxide.

[0016] The contact layer 130 can comprise, for example, at least one of: silicon phosphide (SiP); silicon arsenide (SiAs); silicon antimony (SiSb); or a combination thereof. The contact layer 130 can be grown in a specific crystallographic orientation according to Miller indices, such as the (111) direction.

[0017] An additional issue with selectivity can arise when growing the contact layer 130, as it can be difficult to grow the contact layer 130 without depositing a layer on the exposed dielectric material of the STI layer 120. In other applications, a way to achieve such selectivity can be to increase the flow of hydrogen chloride (HC1) or decrease the temperature of the process. However, this can not be possible in the present application, as increasing the flow of HC1 or decreasing the temperature of the process can inhibit the growth rate of the contact layer 130 and / or adversely affect the level of dopant incorporated in the contact layer 130.

[0018] To achieve an appropriate growth rate and dopant level, Figure 2 A process 200 for growing the contact layer 130 is illustrated. The process 200 can include a pre-clean step 210, a temperature stabilization step 220, a halide precursor flow step 230, a silicon precursor flow step 240, a dopant precursor flow step 250, and a repeat cycle 260. The process 200 can be performed in a deposition apparatus comprising a reaction chamber, a heating element, a susceptor, and a plurality of gas sources.

[0019] The pre-clean step 210 can include a process to remove any oxides on the device prior to growing the contact layer 130. The pre-clean step 210 can flow and sublimate chemicals in conjunction as described in U.S. Patent No. 10,053,774 entitled “Reactor System for Sublimation of Pre-Clean Byproducts and Method Thereof,” which is incorporated by reference herein. Alternatively, the pre-clean step 210 can flow NF3and ammonia (NH3) chemicals with a remote plasma. The pre-clean step 210 can be performed at a temperature range between 500 °C to 800 °C, between 550 °C to 700 °C, or between 600 °C to 650 °C.

[0020] If the pre-clean step 210 requires a different temperature than that required to form the contact layer 130, a temperature stabilization step 220 can be required. The temperature stabilization step 220 can result in the temperature of the reaction chamber to be in a range between 300 °C to 800 °C, between 400 °C to 650 °C, or between 450 °C to 550 °C.

[0021] The halide precursor flow step 230 can include a flow of at least one of: hydrogen fluoride (HF); hydrogen chloride (HC1); hydrogen bromide (HBr); hydrogen iodide (HI); chlorine (CI2); fluorine (F2); bromine (Br2); iodine (I2); or combinations thereof. The purpose of the halide precursor flow step 230 is to allow the contact layer 130 to be selectively deposited onto the fin 110 and not onto the STI layer 120. However, the halide precursor flow step 230 should not be so large as to inhibit the growth rate of the contact layer 130.

[0022] The silicon precursor flow step 240 can include a flow of at least one of: silane (SiH4); dichlorosilane (DCS); disilane; propylsilane; trichlorosilane; or combinations thereof. The silicon precursor will deposit onto the fin 110, where it will react to form the contact layer 130.

[0023] The dopant precursor flow step 250 can include, for example, a flow of at least one of: a phosphorus halide, such as PCI3, PCI5, PBr3, PBr5, PI3, or PI5; an arsenic halide, such as AsCI3, AsCI5, AsBr3, AsBr5, AsI3, or AsI5; an antimony halide, such as SbCI3, SbCI5, SbBr3, SbBr5, SbI3, or SbI5; or a hydride, such as arsine (AsH3) or phosphine (PH3). The dopant precursor flow step 250 can include a co-flow or an alternating flow of multiple dopant sources selected from the above list.

[0024] Prior art methods can have used phosphines or arsines as dopant sources, but this can lead to safety issues in handling and delivering to the reaction chamber due to the high vapor pressures involved. By including at least one of the dopant precursors listed above, the surface chemistry can be modified to incorporate more n-type dopant in the electroactive lattice sites while operating under a safe mechanism.

[0025] The method 200 can also include repeating the cycle of step 260 to form a film having a desired thickness.

[0026] Due to the steps in the method 200, the reaction chamber can be at a lower temperature and pressure. The temperature can be in a range between 400 °C and 800 °C, between 550 °C and 700 °C, or between 600 °C and 650 °C. The pressure can be in a range between 0.1 and 760 Torr, between 10 and 200 Torr, or between 30 and 100 Torr.

[0027] Further, the process 200 can result in a contact layer formed of silicon phosphide (SiP), for example, having a high phosphorous content and electroactive properties without going into a defect state. Additionally, due to the process 200, there can be a high dopant incorporation level.

[0028] Figure 3 An apparatus 300 for forming a device is illustrated in accordance with at least one embodiment of the present disclosure. The apparatus 300 includes a reaction chamber 302, a first gas source 304 configured to provide a first gas to the reaction chamber 302, a second gas source 306 configured to provide a second gas to the reaction chamber 302; and a susceptor 308 configured to hold a semiconductor substrate on which a device is formed. The apparatus 300 can also include a gas distribution apparatus 310 to provide one or more gases to the reaction chamber 302. Additionally, the apparatus 300 can include a controller 312 to, for example, control gas flow rates, reaction chamber pressure, reaction chamber temperature, and the like. The apparatus 300 can be configured to perform a method as described herein.

[0029] The particular implementations shown and described are illustrative examples of the application and its best mode and are not intended to limit the scope of aspects and implementations in any way. Indeed, for the sake of brevity, conventional manufacturing, connecting, preparing, and other functional aspects of the systems can not be described in detail. Furthermore, the connecting lines shown in the various figures are intended to represent exemplary functional relationships and / or physical couplings between the various elements. Many alternative or additional functional relationships or physical connections can be present in a practical system, and / or absent in some embodiments.

[0030] It is to be understood that the configurations and / or approaches described herein are exemplary in nature, and that these specific embodiments or examples are not to be considered in a limiting sense, because numerous variations are possible. The specific routines or methods described herein can represent one or more of any number of processing strategies. As such, various acts illustrated can be performed in the sequence illustrated, in other sequences, or omitted in some cases.

[0031] The subject matter of the present disclosure includes all novel and nonobvious combinations and subcombinations of the various processes, systems and configurations, and other features, functions, acts and / or properties disclosed herein, as well as any and all equivalents thereof.

Claims

1. A method for forming a contact layer on a fin disposed on a semiconductor substrate, the method comprising: Remove any oxides from the device on the semiconductor substrate, which is disposed on a liner in the reaction chamber; Stabilize the temperature of the reaction chamber; A halide precursor is allowed to flow onto the device, the halide precursor comprising at least one of the following: hydrogen fluoride (HF); hydrogen chloride (HCl); hydrogen bromide (HBr); hydrogen iodide (HI); chlorine (Cl2); fluorine (F2); bromine (Br2); or iodine (I2). A silicon precursor is flowed onto the device, the silicon precursor comprising at least one of the following: silane (SiH4); dichlorosilane (DCS); ethoxysilane; or propane; and The dopant precursor is allowed to flow onto the device, the dopant precursor comprising at least one of the following: PCl3; PCl5; PBr3; PBr5; PI3; PI5; AsCl3; AsCl5; AsBr3; AsBr5; AsI3; AsI5; SbCl 3； SbCl5; SbBr3; SbBr5; SbI3; SbI5; AsH3; PH3; The silicon precursor and the dopant precursor react to form a contact layer, wherein the contact layer comprises silicon phosphide (SiP); silicon arsenide (SiAs); silicon antimonide (SiSb); or a combination thereof. The halide precursor prevents the contact layer from depositing onto the dielectric layer disposed on the semiconductor substrate; and Any flow steps are repeated to form the desired thickness of the contact layer.

2. The method according to claim 1, wherein the cleaning step is performed at a temperature between 300°C and 800°C.

3. The method according to claim 2, wherein the cleaning step is performed at a temperature between 400°C and 650°C.

4. The method according to claim 3, wherein the cleaning step is performed at a temperature between 450°C and 550°C.

5. The method of claim 1, wherein the stabilization step comprises stabilizing the temperature to a temperature range between 400°C and 800°C.

6. The method of claim 5, wherein the stabilization step comprises stabilizing the temperature to a temperature range between 550°C and 700°C.

7. The method of claim 6, wherein the stabilization step comprises stabilizing the temperature to a temperature range between 600°C and 650°C.

8. The method of claim 1, wherein the pressure in the reaction chamber is in the range of 0.1 to 760 Torr.

9. The method of claim 8, wherein the pressure in the reaction chamber is in the range of 10 to 200 Torr.

10. The method of claim 9, wherein the pressure in the reaction chamber is in the range of 30 to 100 Torr.

11. The method according to claim 1, wherein the formed contact layer has a (111) crystalline orientation.

12. An apparatus for forming a device, the apparatus comprising: Reaction chamber; A first gas source, configured to supply a first gas to the reaction chamber; A second gas source, configured to supply a second gas to the reaction chamber; and A support, the support being configured to hold a semiconductor substrate on which a device is formed; The device is configured to perform the method according to claim 1.

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