Systems, methods, and non-transitory computer-readable media for inspecting current mirror circuits

Abstract

The method includes calculating a mismatch value between an input current associated with a master transistor of the current mirror circuit and a second current associated with a second transistor of the current mirror circuit, comparing the mismatch value to a preset mismatch threshold, and generating a comparison result specifying whether the mismatch value exceeds the preset mismatch threshold. When the mismatch value exceeds a preset mismatch threshold, a parameter associated with the first transistor or the second transistor is modified.

Description

Technical Field

[0001] The present disclosure relates to a system and method, and more particularly to a system and method for detecting mismatch in a current mirror circuit. Background Art

[0002] A semiconductor device (e.g., an integrated circuit and a semiconductor chip or die) may include one or more current mirror circuits. Each current mirror circuit generates an output current that is a replica or scaled version (e.g., a multiple or fraction) of an input current. The current mirror circuit can serve as a current source for other circuits within the semiconductor device, such as a bandgap reference circuit, and can provide a relatively stable current, facilitating consistent operation within the semiconductor device, such as generating a stable reference voltage. Summary of the Invention

[0003] A method for checking mismatch in a current mirror circuit disclosed herein includes: receiving a preset mismatch threshold, a voltage difference, an input current associated with a master transistor of the current mirror circuit, a channel width of the master transistor, a gate length of the master transistor, and a first preset constant; calculating a mismatch value between an output current associated with a slave transistor of the current mirror circuit and the input current based on the voltage difference, the input current, the channel width, the gate length, and the first preset constant; and comparing the mismatch value with the preset mismatch threshold and generating a comparison result, the comparison result specifying whether the mismatch value exceeds the preset mismatch threshold; wherein, when the mismatch value exceeds the preset mismatch threshold, parameters associated with the master or slave transistor are modified, wherein a device is manufactured based on the modified parameters.

[0004] A system for checking mismatch in a current mirror circuit disclosed herein includes: a receiver configured to collect: a preset mismatch threshold; a voltage difference between a source voltage of a master transistor of a current mirror circuit and a source voltage of a slave transistor of the current mirror circuit; an input current associated with the master transistor; a channel width of the master transistor; a gate length of the master transistor; and a preset constant; a calculator configured to calculate a mismatch value between an output current associated with the slave transistor and the input current based on the voltage difference, the input current, the channel width, the gate length, and the preset constant; and a comparator configured to compare the mismatch value with the preset mismatch threshold and generate a comparison result, wherein the comparison result specifies whether the mismatch value exceeds the preset mismatch threshold.

[0005] A non-transitory computer-readable medium disclosed herein stores instructions that, when executed by one or more data processors of at least one computing device, result in operations including: collecting: a preset mismatch threshold; an input current associated with a master transistor of a current mirror circuit; the number of current mirror circuits in a semiconductor chip; a chip defect level of the semiconductor chip; a channel width of the master transistor; a gate length of the master transistor; and first and second preset constants; calculating a mismatch value between an output current associated with a slave transistor of the current mirror circuit and the input current based on a voltage difference, the input current, the channel width, the gate length, and the first and second preset constants; and comparing the mismatch value with the preset mismatch threshold and generating a comparison result, the comparison result specifying whether the mismatch value exceeds the preset mismatch threshold. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the disclosure are best understood from the following detailed description when read with the accompanying drawings:

[0007] Figure 1 is a schematic block diagram illustrating an exemplary system according to various embodiments of the present disclosure;

[0008] Figure 2 is a schematic circuit diagram illustrating an exemplary current mirror circuit of a semiconductor chip according to various embodiments of the present disclosure;

[0009] Figure 3 is a schematic block diagram illustrating an exemplary system according to various embodiments of the present disclosure;

[0010] Figure 4 is a schematic diagram illustrating an exemplary graphical user interface (GUI) of a system according to various embodiments of the present disclosure;

[0011] Figure 5 is a diagram illustrating exemplary relationships between transistor parameters in a current mirror circuit according to various embodiments of the present disclosure;

[0012] Figure 6 is a diagram illustrating another exemplary relationship between transistor parameters in a current mirror circuit according to various embodiments of the present disclosure;

[0013] Figure 7 is a diagram illustrating another exemplary relationship between transistor parameters in a current mirror circuit according to various embodiments of the present disclosure;

[0014] Figure 8 is a plot illustrating exemplary standard deviation levels according to various embodiments of the present disclosure;

[0015] Figure 9 is a schematic circuit diagram illustrating an exemplary semiconductor chip according to various embodiments of the present disclosure;

[0016] Figure 10 is a flow chart illustrating an exemplary method for obtaining a mismatch value between input and output currents of a current mirror circuit according to various embodiments of the present disclosure;

[0017] Figure 11 is a schematic block diagram illustrating an exemplary computing device architecture according to various embodiments of the present disclosure. DETAILED DESCRIPTION

[0018] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the sake of simplicity and clarity and does not, by itself, indicate the relationship between the various embodiments and / or configurations discussed.

[0019] As described above, a semiconductor chip may include one or more current mirror circuits, each of which generates an output current that is a replica or scaled version (e.g., a multiple or fraction) of an input current. For example, an input current (e.g., from a current source circuit) is established through a master transistor of the current mirror circuit. The slave transistor of the current mirror circuit mirrors the input current. When the slave transistor has substantially the same characteristics as the master transistor (e.g., size, e.g., W / L ratio), it will conduct an output current substantially equal to the input current.

[0020] Mismatches between the input and output currents in a current mirror circuit can cause semiconductor chip failures and result in low manufacturing yields. Certain systems and methods described herein analyze mismatches in a current mirror circuit before manufacturing a semiconductor chip. For example, if a detected mismatch value is greater than a preset mismatch threshold, meaning a mismatch exists between the input and output currents, the circuit design of the current mirror circuit can be modified to reduce the mismatch value. Conversely, if the mismatch value is within the preset mismatch threshold, meaning the output current substantially matches the input current, the inspection and / or modification process continues for other current mirror circuits in the semiconductor chip. This can help ensure a high manufacturing yield for the semiconductor chip.

[0021] Figure 1is a schematic block diagram illustrating an example system 110 connected between an input source 120 and an output device 130 according to various embodiments of the present disclosure. As described below, the example system 110 detects whether a mismatch occurs between the input and output currents of a current mirror circuit of a semiconductor chip. For example, Figure 1 As shown, system 110 is connected between an input source 120 and an output device 130 and collects multiple inputs from input source 120. These inputs can be used to obtain a mismatch value between the input and output currents of a current mirror circuit of a semiconductor chip. The mismatch value is then compared with a preset mismatch threshold to determine whether the mismatch value is within acceptable limits. The system uses output device 130 to indicate the comparison result. For example, in some embodiments, output device 130 includes a computer display. In these embodiments, if the mismatch value exceeds the preset mismatch threshold, output device 130 displays "fail." Otherwise, output device 130 displays "pass." In other embodiments, output device 130 also includes a computer speaker, a computer printer, an indicator light, a buzzer, etc. The output current generated by the current mirror circuit can be used to bias other circuits of the semiconductor chip, such as a bandgap reference circuit to generate a relatively stable reference voltage.

[0022] As can be seen from the above description, checking for mismatch in current mirror circuits ensures the reliability and performance of semiconductor chips, helps detect potential problems early, and improves overall yield. For example, if the mismatch value of the current mirror circuit is found to exceed a preset mismatch threshold, it can be redesigned to correct the discrepancy. This iterative process improves the accuracy of the current mirror circuit, thereby increasing the yield of the semiconductor chip. Furthermore, it reduces the likelihood of field failures and optimizes the manufacturing process by identifying and resolving design flaws early. This proactive approach ultimately results in more robust and reliable semiconductor devices, benefiting both manufacturers and end users. After adjusting the design, one or more physical semiconductor chips are manufactured based on the adjusted design.

[0023] An example supporting circuit of the current mirror circuit 200 is as follows: Figure 2 It should be understood that this circuit is provided as an example only and is not limiting, and other suitable circuits are also within the scope of the present disclosure. Figure 2 FIG. 2 is a schematic circuit diagram illustrating an exemplary current mirror circuit 200 according to various embodiments of the present disclosure. Figure 2As shown, the current mirror circuit 200 includes a master transistor 210 and a slave transistor 220, at least one of which is in the form of a metal-oxide-semiconductor field-effect transistor (MOSFET), such as an n-type or p-type MOSFET. The master transistor 210 has a first source / drain terminal and a gate terminal connected to each other and to the gate of the slave transistor. A second source / drain terminal of the master transistor and a second source / drain terminal of the slave transistor are connected to each other and to a reference voltage or electrical ground.

[0024] In the example operation, the input current (I IN ) is provided by, for example, a constant current source to the first source / drain terminal of the master transistor 210. Since the gate terminal of the master transistor 210 is connected to the first source / drain terminal of the master transistor 210, the master transistor 210 operates in a saturation mode, ensuring that the input current (I IN The voltage at the gate terminal of the master transistor 210 is shared with the gate terminal of the slave transistor 220. This ensures that both transistors 210, 220 have substantially the same gate-source voltage (V GS1 、V GS2 ). Due to this shared gate-source voltage (V GS1 、V GS2 ), the slave transistor 220 also operates in saturation mode and mirrors the input current (I IN In some embodiments, the output current (I OUT ) may be substantially equal to the input current (I IN In other embodiments, the output current (I OUT ) may be scaled to the input current (I IN ), for example, by adjusting the size of the slave transistor 220 relative to the master transistor 210, such as the W / L ratio.

[0025] Input current (I IN ) can be calculated using equation (1):

[0026]

[0027] where μ n C OX is a preset constant, L is the gate length of the main control transistor 210, W is the channel width of the main control transistor 210, V GS is the gate-source voltage of the master transistor 210, V TH is the threshold voltage of the main control transistor 210 .

[0028] In addition, the voltage difference (ΔV S , ΔV TH ) is defined by equations (2) and (3):

[0029] ΔV S =V GS2 -V GS1 (2)

[0030] Where V GS1 is the gate-source voltage of the master transistor 210, V GS2 is the gate-source voltage of the slave transistor 220 .

[0031] ΔV TH =V TH2 -V TH1 (3)

[0032] Where V TH1 is the threshold voltage of the master transistor 210, V TH2 is the threshold voltage of the slave transistor 220 .

[0033] In addition, the input and output currents (I IN , I OUT ) between the mismatch value (M V ) is given by equation (4):

[0034]

[0035] As will be further described below, these equations (1)-(4) help verify current mismatch and assist in analyzing and optimizing the design and performance of the current mirror circuit 200 to ensure that it meets desired specifications and operating standards.

[0036] In some embodiments, the output current (I OUT ) can be the input current (I IN ). This can be achieved when the size of the slave transistor 220 is different from the master transistor 210. For example, if the W / L ratio of the slave transistor 220 is n times the W / L ratio of the master transistor 210, the output current (I OUT ) will be approximately n times the input current. Conversely, if the W / L ratio of the slave transistor 220 is 1 / n times the W / L ratio of the master transistor 210, the output current (I OUT ) will be roughly the input current (I IN ) times of 1 / n.

[0037] Figure 3FIG. 1 is a schematic block diagram illustrating another exemplary system 110 according to various embodiments of the present disclosure. Figure 3 As shown, the example system 110 includes a receiver 310, a capturer 320, an extractor 330, a calculator 340, and a comparator 350. The receiver 310 collects one or more inputs from one or more input sources, such as an input device 360, a lookup table (LUT) 370, and a circuit design 380. For example, further reference is made to Figure 2 , the input device 360 ​​receives one or more specifications, including a predetermined mismatch threshold (Source MM ), voltage difference (ΔV S ) and input current (I IN ). The input device 360 ​​then transmits these specifications to the receiver 310. In some embodiments, the input device 360 ​​is in the form of a computer keyboard, a computer mouse, a touch screen, other suitable input devices, or a combination thereof.

[0038] The preset mismatch threshold (Source MM ), for example expressed as a percentage (such as 5%), representing the input and output current (I IN , I OUT ) between the maximum mismatch value (M V1 ). That is, when the mismatch value (M V1 ) exceeds the preset mismatch threshold (Source MM ), indicating the output current (I OUT ) significantly deviates from the input current (I IN ), which means that the current mirror circuit 200 does not accurately replicate the input current (I IN On the other hand, when the mismatch value (M V1 ) at the preset mismatch threshold (Source MM ) when the output current (I OUT ) closely replicates the input current (I IN ), indicating that the performance of the current mirror circuit 200 is reliable and meets the expected specifications.

[0039] Extractor 320 extracts one or more parameters from circuit design 380 corresponding to current mirror circuit 200 and transmits the extracted parameters to receiver 310. For example, these parameters include channel width (W) and gate length (L). In some embodiments, circuit design 380 may be generated by a circuit design engineer using electronic design automation (EDA) tools or circuit simulation software. In these embodiments, extractor 320 communicates with the circuit design tool / software, for example, via a local or wide area network (LAN or WAN), to obtain the parameters.

[0040] The channel width (W) is given by equation (5):

[0041] W=(m)(N finger )(w) (5)

[0042] Where m is the number of master transistors 210 connected in parallel, N finger is the index of the gate region of each master transistor 210, and w is the channel width of each gate region.

[0043] The gate length (L) is given by equation (6):

[0044] L=(N stack )(l g ) (6)

[0045] where N stack is the number of master transistors 210 connected in series, l g is the gate length of each master control transistor 210 .

[0046] The acquirer 330 acquires one or more preset constants from the lookup table 370, such as the preset constant (μ n C OX ), and the preset constant (μ n C OX ) is transmitted to the receiver 310. In summary, as shown in Table 1 below, the receiver 310 receives specifications (e.g., the preset mismatch threshold Source MM , voltage difference ΔV S and input current I IN ), receives parameters (eg, channel width W and gate length L) from the extractor 320, and receives a preset constant (μ n C OX ).

[0047]

[0048] Table 1

[0049] The receiver 310 receives the specifications (ΔV S , I IN ), parameters (W, L) and preset constants (μ n C OX ) is transmitted to the calculator 340. The calculator 340 uses equation (7) based on these metrics (ΔV S , I IN ,W,L,μ n C OX )Calculate the mismatch value (M V1 ):

[0050]

[0051] Equation (7) can be derived from equations (1), (2), and (4). For example, by rearranging equation (1), we can obtain:

[0052]

[0053] Substituting equation (1) into equation (4) yields:

[0054]

[0055] By eliminating the preset constant (μ n C OX ), we get equation (10) as follows:

[0056]

[0057] Substituting equation (2) into equation (10) yields:

[0058]

[0059] Simplifying equation (11) yields:

[0060]

[0061] Finally, substituting equation (8) into equation (12) yields equation (7).

[0062] The receiver 310 receives the specification (Source MM ) is transmitted to the comparator 350. The calculator 340 calculates the mismatch value (M V1 ) is transmitted to the comparator 350. The comparator 350 then compares the mismatch value (M V1 ) does not match the preset threshold (Source MM ) and generates a comparison result. The output device 390 indicates the input current and output current (I N , I OUT ) between the output device 390 and the output device 390. For example, in some embodiments, the output device 390 is a computer display. In these embodiments, if the mismatch value (M V1 ) is greater than the preset mismatch threshold (Source MM ), the output device 390 displays "FAIL". Otherwise, the output device 390 displays "Pass". In other embodiments, the output device 390 can be a computer speaker, a computer printer, other output devices capable of indicating the comparison result, or a combination thereof.

[0063] In another embodiment, the system 110 includes at least one of a lookup table 370, a circuit design 380, and an output device 390, as shown in the dashed box. This configuration allows for a flexible and modular design, enabling the system 110 to be customized to specific needs and applications. For example, the inclusion of the lookup table 370 provides for rapid retrieval of preset constants ( n C OX ) method. Similarly, the parameters of circuit design 380 can also be reliably extracted by extractor 320. This modular approach not only enhances the versatility of system 110, but also improves its ability to be integrated into various existing settings and workflows.

[0064] The previous sections describe how to determine the input current and output current (I N , I OUT ) between the mismatch value (M V1 ) process, which is caused by the source voltage of the main control transistor 210 (V S1 ) and the source voltage of the slave transistor 220 (V S2 ) between the voltage difference (ΔV S The following sections deal with evaluating the threshold voltage (V TH1 ) and the threshold voltage of the slave transistor 220 (V TH2 ) between the voltage difference (ΔV TH ) How does it cause mismatch values ​​(M V2 ).

[0065] Reference Figure 3 , the receiver 310 collects one or more inputs from one or more input sources, such as an input device 360, a lookup table 370, and a circuit design 380. For example, further reference is made to Figure 2 , the input device 360 ​​accepts one or more specifications, including: a preset mismatch threshold (Threshold MM ), input current (I IN ), the number of current mirror circuits in the semiconductor chip (N CMC ), and the chip defect level (J) of the semiconductor chip. The input device 360 ​​then transmits these specifications to the receiver 310.

[0066] The preset mismatch threshold (Threshold MM ), for example, expressed as a percentage (such as 5%), representing the input current and output current (I IN , I OUT ) between the maximum mismatch value (M V2 ). That is, when the mismatch value (M V2 ) exceeds the preset mismatch threshold (Threshold MM), indicating the output current (I OUT ) significantly deviates from the input current (I IN ), which means that the current mirror circuit 200 cannot accurately replicate the input current (I IN ). On the contrary, when the mismatch value (M V2 ) at the preset mismatch threshold (Threshold MM ) when the output current (I OUT ) closely replicates the input current (I IN ), indicating that the current mirror circuit 200 has reliable performance and meets the expected specifications.

[0067] The extractor 320 extracts one or more parameters from the circuit design 380 corresponding to the current mirror circuit 200 and transmits the extracted parameters to the receiver 310. For example, these parameters include the channel width (W), the gate length (L), and the output current (I OUT ) and input current (I IN ) ratio (R).

[0068] The acquirer 330 retrieves one or more preset constants from the lookup table 370, such as the preset constant (μ n C OX , G), and the preset constant (μ n C OX , G) is transmitted to the receiver 310. In summary, as shown in Table 2 below, the receiver 310 receives specifications (eg, a preset mismatch threshold Threshold) from the input device 360. MM , input current I IN , the number N of current mirror circuits in the semiconductor chip CMC , and the chip defect level J of the semiconductor chip), receives parameters (eg, channel width W, gate length L, and ratio R) from the extractor 320, and receives a preset constant (μ n C OX , G).

[0069]

[0070] Table 2

[0071] The receiver 310 receives the specifications (Threshold MM , I IN , N CMC , J), parameters (W, L, R) and preset constants (μ n C OX , G) are transmitted to the calculator 340. The calculator 340 uses equation (13) based on these indicators (IIN , N CMC ,J,W,L,R,μ n C OX , G) calculate the mismatch value (M V2 ):

[0072]

[0073] in

[0074] NORMINV is an MS Excel function that returns the inverse of the normal cumulative distribution for a specified mean and standard deviation. Equation (13) can be derived from equations (1), (3), and (4). For example, by rearranging equation (1), we can obtain equation (8).

[0075] Substituting equation (1) into equation (4) yields:

[0076]

[0077] By eliminating the preset constant (μ n C OX ), we get equation (10) as follows:

[0078]

[0079] Substituting equation (3) into equation (15) yields:

[0080]

[0081] Simplifying equation (11) yields:

[0082]

[0083] Finally, substituting equation (8) into equation (17) yields equation (13).

[0084] The receiver 310 receives the specification (Threshold MM ) is transmitted to the comparator 350. The calculator 340 calculates the mismatch value (M V2 ) is transmitted to the comparator 350. The comparator 350 then compares the mismatch value (M V2 ) and the preset mismatch threshold (Threshold MM ) and generates a comparison result. The output device 390 indicates the input current and output current (I N , I OUT) between the output device 390 and the output device 390. For example, in some embodiments, the output device 390 is a computer display. In these embodiments, if the mismatch value (M V2 ) is greater than the preset mismatch threshold (Threshold MM ), the output device displays "FAIL". Otherwise, the output device 390 displays "Pass". In other embodiments, the output device 390 can be a computer speaker, a computer printer, other output devices capable of indicating the comparison result, or a combination thereof.

[0085] Referring further to Table 3 below, the defect level (J) of the chip per million parts can be determined by several factors, including the chip yield or the percentage of defect-free chips, the yield of the chip's current mirror circuit, the number of defects per million in the current mirror circuit, and the number of standard deviations (σ) required for the quality of the current mirror circuit.

[0086]

[0087] *For example, there are 10 current mirror circuits in one chip

[0088] Table 3

[0089] The chip yield is calculated as follows:

[0090]

[0091] The yield of the current mirror circuit is calculated as follows:

[0092]

[0093] The number of defects per million in the current mirror circuit is calculated as follows:

[0094]

[0095] The required quality level of the current mirror circuit is derived using the inverse normal distribution function.

[0096] For example, as can be seen in Table 3 above, achieving a chip yield of 0.99999 corresponds to a chip defect level (J) of 10. Conversely, a lower current mirror circuit yield, such as 0.99899547, results in a higher chip defect level (J), such as 10000. The chip defect level (J) is proportional to the number of defective current mirror circuits. Furthermore, a higher standard deviation (σ) value indicates a lower chip defect level (J), reflecting higher quality and lower defectivity.

[0097] The data shows that as the chip defect level (J) increases, both the chip yield and the current mirror circuit yield decrease. Conversely, the current mirror circuit defect rate increases with higher chip defect levels (J). In addition, the number of standard deviations (σ) required for each current mirror circuit decreases as the chip defect level (J) increases, indicating that higher defect levels (J) result in lower-quality circuits. For example, when the chip defect level (J) is 10ppm, the chip yield is 0.99999 and the current mirror circuit yield is 0.99999900, resulting in a current mirror circuit defect rate of 1.00ppm and a standard deviation (σ) value of 4.89. However, at a defect level (J) of 10,000ppm, the chip yield drops to 0.99 and the current mirror circuit yield drops to 0.99899547, resulting in a current mirror circuit defect rate of 1004.53ppm and a standard deviation (σ) value of 3.29. This highlights the impact of the defect level (J) on overall chip and circuit quality.

[0098] Figure 4 FIG2 is a diagram illustrating an example graphical user interface (GUI) 400 of system 110 according to various embodiments of the present disclosure. GUI 400 enables a user to interact with system 110 through graphical elements such as windows, text boxes, and buttons, rather than text-based commands. Figure 4 As shown, a window is a rectangular area on the screen that displays content on the output device 390 and can be resized, minimized, maximized, or closed. A text box allows the user to enter text for data entry, while a button is labeled with text and performs an action when pressed. For example, the GUI 400 includes a window for accepting specifications such as Source in its text box. MM , ΔV S , I IN 、Threshold MM , ΔV TH 、N CMC and J as input fields. The user interacts with the GUI 400 using an input device such as a computer mouse, a computer keyboard, or a touch screen, and the GUI 400 provides visual and auditory feedback.

[0099] Example LUT 370, Table 4, shows transistor characteristics (eg, characteristics of master / slave transistors 210, 220) versus preset constants (μ n C OX As can be seen, each row in Table 4 includes the channel width (W) of the master / slave transistors 210, 220, the gate length (L) of the master / slave transistors 210, 220, and the preset constant (μ n C OX For example, a line specifies a channel width (W) of 32nm, a gate length (L) of 3nm, and a preset constant (μn C OX ) is 3.75357812594852E-05, and the preset constant (G) is 0.143066564361755. In subsequent sections, how to generate LUT 370, such as Table 4, will be further described in detail. It can be generated by a device outside the system 110 or by the system 110 itself.

[0100]

[0101]

[0102] Table 4

[0103] Figure 5 FIG. 1 is a diagram illustrating exemplary relationships between parameters of the master transistor 210 according to various embodiments of the present disclosure. Figure 5 As shown, the x-axis represents the channel width (w) of the main control transistor 210, the number of fingers (N) in the gate region of the main control transistor 210, and the finger ) and (V GS -V TH ) 2 The product of V GS is the gate-source voltage of the master transistor, V TH is the threshold voltage of the main control transistor. The y-axis represents the input current (I IN ), the gate length (Lg) of the master transistor 210 and the number of channel regions (N stack ). The dashed line is described by the equation y = 3.32E-5x + 4.53E-14, indicating a linear relationship between the variables. The slope of this trend line is affected by the preset constant (μnCox). The preset constant (μnCox) obtained from this chart is mapped to the LUT 370. For example, equation (21) for calculating the preset constant (μnCox) can be derived from equation (1):

[0104]

[0105] Figure 6 FIG. 1 is a diagram illustrating exemplary relationships between parameters of the master transistor 210 according to various embodiments of the present disclosure. Figure 6 As shown, the x-axis represents 1 / (WL) 0.5 , where W is the channel width of the master transistor 210 and L is the gate length of the master transistor 210, both measured in nanometers. The y-axis represents ΔV TH One standard deviation (σΔV TH ), which is the standard deviation of the threshold voltage variation in volts. ΔV TH One standard deviation (σΔV TH ) is defined by equation (22):

[0106]

[0107] The dashed line on the graph represents a linear fit through the data points, and the equation "y = 0.2487x + 0.0006" further illustrates this trend. The slope of this trend line is affected by the preset constant (G). The preset constant (G) obtained from this graph is mapped to the LUT 370. For example, equation (23) for calculating the preset constant (G) can be derived from equation (22):

[0108]

[0109] Figure 7 FIG. 1 is a diagram illustrating another exemplary relationship between parameters of the master transistor 210 according to various embodiments of the present disclosure. Figure 7 As shown, three overlapping graphs each represent data for a master transistor 210 with a gate length (Lg) of 3 nm but a different width (W). The top graph corresponds to a width of 32 nm, the middle graph corresponds to a width of 42 nm, and the bottom graph corresponds to a width of 58 nm. Each graph shows ΔV TH One standard deviation (σΔV TH ) and the inverse square root of the product of the channel width and length of the master transistor 210, i.e. 1 / (WL) 0.5 The slope of each trend line in the chart is affected by a preset constant (G). The preset constant (G) obtained from these charts is mapped to the LUT 370.

[0110] In some embodiments, the preset constant (μ n C OX , G) are obtained from the same threshold voltage, such as the standard threshold voltage (SVT), and across various combinations of channel width (W) and gate length (L). In other embodiments, referring to Table 5, the preset constant (μ n C OX , G) is obtained from different threshold voltage combinations, including SVT, LVT (low threshold voltage), uLVT (ultra-low threshold voltage), channel width (W) and gate length (L).

[0111] Device Type Device Table W L NMOS svt,lvt,ulvt 32n,42n,58n 3n,22n PMOS svt,lvt,ulvt 32n,42n,58n 3n,22n

[0112] Table 5

[0113] Figure 8 is a plot illustrating example standard deviation (σ) levels according to various embodiments of the present disclosure. Figure 8The example graph shown is a standard normal distribution curve, also known as a bell curve. It's often used in the context of standard deviation levels to describe variability in manufacturing processes and predict manufacturing yield. For example, the horizontal axis represents the range of values ​​around the mean (μ), labeled by standard deviation (σ) from the mean, showing points at μ-3σ, μ-2σ, μ-1σ, μ, μ+1σ, μ+2σ, and μ+3σ. The vertical axis represents the probability density, or frequency, of these values. The area under the curve indicates that 68% of the data falls within ±1σ (one standard deviation) of the mean, meaning that in a manufacturing process, approximately 68% of produced parts will meet specifications if they fall within this range. Similarly, 95% of the data falls within ±2σ (two standard deviations), indicating a higher yield of 95%, and 99.73% falls within ±3σ (three standard deviations), meaning that virtually all (99.73%) of the produced parts will meet specifications within this range.

[0114] In the context of standard deviation levels in manufacturing yield, operating at 1σ means only 68% of products meet specification, indicating a high defect rate. At 2σ, 95% of products meet specification, an improvement but still potentially unacceptable in high-precision industries. At 3σ, 99.73% of products meet specification, significantly reducing defects. Higher standard deviation levels, such as 4σ, 5σ, and 6σ, indicate even fewer defects. 4σ achieves a yield of approximately 99.9937%, 5σ achieves a yield of approximately 99.99994%, and 6σ achieves a yield of approximately 99.9999998%, which is virtually defect-free and the near-perfect quality that the Six Sigma methodology aims to achieve. This chart emphasizes the importance of minimizing variability and improving process capability to achieve higher standard deviation levels, thereby leading to better chip quality.

[0115] Table 6 shows the target chip defect rate, target chip yield, corresponding standard deviation level, and threshold voltage change (ΔV TH ) required tolerances. For example, for a stringent target chip defect rate of ≤100ppm, achieving a very high yield of ≥99.99% requires a standard deviation level of ≥3.89 and allows for significant threshold voltage variation (ΔV TH ) tolerance (++++). As defect rate targets become more relaxed, such as ≤1000ppm, the target yield is reduced to ≥99.90%, the required standard deviation level drops to ≥3.29, and the threshold voltage variation (ΔV TH ) tolerance remains high (+++). For a target defect rate ≤ 2700ppm, a yield of ≥ 99.73% can be achieved with a standard deviation level of ≥ 3.00 and a threshold voltage variation (ΔV TH) tolerance is moderate (++). The least stringent target defect rate ≤ 10000ppm corresponds to a yield of ≥ 99.00%, requiring a standard deviation level of ≥ 2.58, and a threshold voltage variation (ΔV TH ) variation tolerance is low (+). That is, Table 7 highlights the trade-offs between achieving high yield, maintaining low defectivity, and managing threshold voltage variability in manufacturing.

[0116]

[0117] Table 6

[0118] Table 7 details how the number of current mirror circuits in a semiconductor chip affects the yield requirements of the semiconductor chip and individual current mirror circuits, as well as the threshold voltage variation (ΔV TH ) tolerance. It presents scenarios for chips with 1, 10, and 100 current mirror circuits, each designed to achieve a consistent 99% target chip yield. As the number of current mirror circuits in a semiconductor chip increases, the yield requirements for each individual current mirror circuit become more stringent. Specifically, a chip with 1 current mirror circuit requires a 99% yield for that circuit, allowing for a lower threshold voltage variation (ΔV TH ) tolerance (+). In contrast, a chip with 10 current mirror circuits requires a 99.9% yield for each circuit and requires a moderate threshold voltage variation (ΔV TH ) tolerance (++). For a chip with 100 current mirror circuits, the yield requirement for each circuit is increased to 99.9999%, which requires a high threshold voltage variation (ΔV TH ) tolerance (+++). This illustrates the trade-off between yield, variability, and process control in complex semiconductor chip designs, emphasizing the need for tight control to maintain the desired overall yield as the complexity and number of current mirror circuits in a semiconductor chip increase.

[0119]

[0120] Table 7

[0121] Figure 9 An exemplary support circuit of semiconductor chip 900 is depicted. It should be understood that this circuit is for illustration only and not limitation, and other suitable system circuits are also within the scope of the present disclosure. Figure 9 FIG. 9 is a schematic circuit diagram illustrating an exemplary semiconductor chip 900 according to various embodiments of the present disclosure. Figure 9As shown, the exemplary semiconductor chip 900 includes a current driving circuit 910 and one or more current mirror circuits 920-940. The current driving circuit 910 is connected to at least one of the current mirror circuits 920-940 and performs a predetermined circuit function. In some embodiments, the current driving circuit 910 includes a voltage regulator, a bandgap reference circuit, other circuits that rely on the current generated by at least one of the current mirror circuits 920-940, or a combination thereof.

[0122] Each current mirror circuit 920-940 includes a master transistor (M0, M5, M9) and one or more slave transistors (M1-M3, M6-M8, M10, M11) connected to the master transistor (M0, M5, M9). The master transistor (M0, M5, M9) allows an input current (I0, I5, I9) to flow, such as a current generated by a current source or a current related to another current mirror circuit. Each slave transistor (M1-M3, M6-M8, M10, M11) generates an output current (I1-I3, I6-I8, I10, I11) that is a replica, multiple, or fraction of the input current (I0, I5, I9).

[0123] In an example operation, further reference is made to Figure 3 When it is necessary to determine whether there is a mismatch between the input and output currents (I0, I5, I9, I1-I3, I6-I8, I10, I11) of the current mirror circuits 720-740, the receiver 310 receives specifications from the input device 360. These specifications include a preset mismatch threshold (Source MM 、Threshold MM ), voltage difference (ΔV S ), input current (I0, I5, I9), the number of current mirror circuits in the semiconductor chip (N CMC ) and the chip defect level (J) of the semiconductor chip. At this time, the output device 390 displays the output, such as Table 8. As can be seen from Table 8, the preset mismatch threshold (Source MM 、Threshold MM ) are expressed as percentages, for example 5% and 15% respectively.

[0124]

[0125] Table 8

[0126] Subsequently, extractor 320 extracts parameters from circuit design 380 corresponding to semiconductor chip 900 and transmits the extracted parameters to receiver 310. For example, these parameters include the channel width (W) of the master and slave transistors (M0-M11), the gate length (L) of the master and slave transistors (M0-M11), and the ratio (R) of the output current (I1-I3, I6-I8, I10, I11) to the input current (I0, I5, I9). For example, Table 8 shows that the ratio (R) of the output current (I0) to the input current (I1, I3) is 2. In other words, the output current (I0) is a multiple of the input current (I1, I3), for example, substantially twice. The ratio (R) of the output current (I0, I5, I9) to the input current (I2, I6, I8, I10, I11) is 1, meaning the output current (I0, I5, I9) is substantially equal to the input current (I2, I6, I8, I10, I11). The output current (I5) is a fraction of the input current (I7), for example, substantially half. Therefore, the ratio (R) of the output current (I5) to the input current (I7) is 1:2.

[0127] Next, the acquirer 330 acquires a preset constant from the lookup table 370, such as the preset constant (μ n C OX , G), and obtain the preset constant (μ n C OX , G) is transmitted to the receiver 310. The receiver 310 then converts the specifications (ΔV S , I IN 、N CMC , J), parameters (W, L, R) and preset constants (μ n C OX , G) are transmitted to the calculator 340. The calculator 340 uses equations (7) and (13) based on these indicators (I IN 、N CMC ,J,W,L,R,μ n C OX , G) calculate the mismatch value (M V1 、M V2 ).

[0128] The receiver 310 receives the specification (Source MM 、Threshold MM ) is transmitted to the comparator 350. The calculator 340 calculates the mismatch value (M V1 、M V2 ) is transmitted to the comparator 350. The comparator 350 then V1 、MV2 ) does not match the preset threshold (Source MM 、Threshold MM ) and generate a comparison result, such as Table 8. The output device 390 indicates the input and output currents (I N , I OUT For example, as shown in Table 8, because of the mismatch value (M) between the input current (I0, I9) and the output current (I1-I3, I10, I11), V1 、M V2 ) respectively at the preset mismatch threshold (Source MM 、Threshold MM ), the current mirror circuits 720 and 740 are indicated as "pass". On the contrary, due to the mismatch (M) between the input current (I5) and the output current (I6-I8), V1 、M V2 ) exceeds the preset mismatch threshold (Source MM 、Threshold MM ), the current mirror circuit 730 is indicated as "failed".

[0129] Figure 10 Flowchart of an exemplary method 1000 for checking mismatch of current mirror circuits (e.g., current mirror circuits 920-940) in a semiconductor chip (e.g., semiconductor chip 900) according to various embodiments of the present disclosure. Figure 1-9 To describe the example method 1000. It is understood that the method 1000 is applicable to Figure 1-9 Furthermore, it will be appreciated that additional operations may be provided before, during, and after method 1000, and that some of the operations described below may be replaced or eliminated in alternative embodiments of method 1000.

[0130] In operation 1010, the input device 360 ​​receives a preset mismatch threshold (Source MM 、Threshold MM ), voltage difference (ΔV S ), input current (I0, I5, I9), the number of current mirror circuits 920-940 in the semiconductor chip 900 (N CMC), and the chip defect level (J) of semiconductor chip 900. These specifications are then transmitted to receiver 310. In operation 1020, extractor 320 extracts the channel width (W) of the master and slave transistors (M0-M11), the gate length (L) of the master and slave transistors (M0-M11), and the ratio (R) of the output current (I1-I3, I6-I8, I10, I11) to the input current (I0, I5, I9) from circuit design 380 corresponding to semiconductor chip 900. These parameters are then transmitted to receiver 310.

[0131] In operation 1030, the acquirer 330 retrieves the preset constant (μ n C OX , G) and forwarded to the receiver 310. In an alternative embodiment, the method 1000 further includes generating a lookup table 370 (e.g., Table 4) before operation 1030, for example, by a lookup table generator external to the system 110 or by the acquirer 330. In operation 1040, the receiver 310 receives the specifications (ΔV S , I IN 、N CMC , J), parameters (W, L, R) and preset constants (μ n C OX , G) is transmitted to the calculator 340. At this time, the receiver 310 also transmits the specification (Source MM 、Threshold MM ) is sent to comparator 350.

[0132] In operation 1050, the calculator 340 calculates the value of the indicator (I IN 、N CMC ,J,W,L,R,μ n C OX , G) Calculate the mismatch value (M) using equations (7) and (13) V1 、M V2 ), and calculate the mismatch value (M V1 、M V2 ) is transmitted to the comparator 350. In operation 1060, the comparator 350 converts the mismatch value (M V1 、M V2 ) does not match the preset threshold (Source MM 、Threshold MM) are compared and a comparison result is generated. In operation 1070, output device 390 displays the comparison result, such as Table 9. In operation 1080, the current mirror circuit indicated as "FAIL" in the comparison result, such as current mirror circuit 930, is redesigned or optimized to reduce the mismatch between its input and output currents (I5, I6-I8). In operation 1090, semiconductor chip 900 is manufactured based on the optimized current mirror circuit 930.

[0133] Figure 11 is a schematic block diagram illustrating an exemplary computing device architecture according to various embodiments of the present disclosure. The exemplary computing device architecture 1100 may be used to implement the system 110 described herein. Figure 11 As shown, bus 1160 can serve as a data highway to interconnect the other hardware components shown. Processing system 1120 (e.g., one or more computer processors / data processors located in a given computer or multiple computers), labeled as a CPU (central processing unit), can perform calculations and logical operations to execute programs. Non-transitory processor-readable storage media, such as read-only memory (ROM) 1110 and random access memory (RAM) 1130, can communicate with processing system 1120 and can contain one or more program instructions for the operations specified herein. Optionally, the program instructions can be stored on a non-transitory computer-readable storage medium, such as a magnetic disk, optical disk, recordable memory device, flash memory, or other physical storage medium.

[0134] In one example, disk controller 1180 can connect one or more optional disk drives to system bus 1160. These disk drives can be external or internal CD-ROM, CD-R, CD-RW, or DVD, or solid-state drives such as 1180B, or external or internal hard drives 1180A. As previously mentioned, these various disk drives 1180A, 1180B and disk controllers are optional devices. System bus 1160 can also include at least one communication port 1170 to allow communication with external devices, which can be physically connected to the computing system or externally available via a wired or wireless network. In some cases, communication port 1170 includes or otherwise comprises a network interface.

[0135] To provide for user interaction, the subject matter described herein may be implemented on a computing device having a display 1150 (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) screen) for displaying information obtained from bus 1160 to the user, and having an input device 1190A, such as a keyboard 1190B and / or a pointing device (e.g., a mouse or trackball) and / or a touch screen, through which the user can provide input to the computer. Other types of input devices 1190A may also be used to interact with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback via a microphone, or tactile feedback); and input from the user may be received in any form, including sound, voice, or tactile input. Input devices 1190A and keyboard 1190B may be coupled to bus 1160 and transmit information via input device interface 1190A. Other computing devices, such as dedicated servers, may omit one or more of the display 1150 and display interface 1140 , the input device 1190A, the keyboard 1190B, and the input device interface 1190 .

[0136] In one embodiment, a method includes receiving a predetermined mismatch threshold, a voltage difference, an input current of a circuit associated with a first transistor, a channel width of the first transistor, a gate length of the first transistor, and a predetermined constant; calculating a mismatch value between a second current associated with a second transistor of the circuit and the first current based on the voltage difference, the input current, the channel width, the gate length, and the predetermined constant; comparing the mismatch value with the predetermined mismatch threshold and generating a comparison result, the comparison result indicating whether the mismatch value exceeds the predetermined mismatch threshold; and modifying parameters associated with the first transistor or the second transistor when the mismatch value exceeds the predetermined mismatch threshold. A device is fabricated based on the modified parameters.

[0137] In the above embodiment, the voltage difference is related to the source voltage of the current mirror circuit.

[0138] In the above embodiment, it also includes receiving the number of current mirror circuits in the semiconductor chip, the chip defect level of the semiconductor chip, and a second preset constant, wherein the voltage difference is related to the chip defect level, the number of the current mirror circuits, the channel width, the gate length, and the ratio of the output current to the input current.

[0139] In the above embodiment, the method further includes extracting the channel width and the gate length from a circuit design.

[0140] In the above embodiment, the method further includes obtaining the first preset constant from a look-up table (LUT).

[0141] In another embodiment, a system includes a receiver, a calculator, and a comparator. The receiver collects a predetermined mismatch threshold, a voltage difference between a source voltage of a master transistor in a current mirror circuit and a source voltage of a slave transistor in the current mirror circuit, an input current associated with the master transistor, a channel width of the master transistor, a gate length of the master transistor, and a predetermined constant. The calculator calculates a mismatch value between an output current associated with the slave transistor and the input current based on the voltage difference, the input current, the channel width, the gate length, and the predetermined constant. The comparator compares the mismatch value with the predetermined mismatch threshold and generates a comparison result indicating whether the mismatch value exceeds the predetermined mismatch threshold.

[0142] In the above embodiment, the receiver is configured to receive the predetermined mismatch threshold, the voltage difference, and the input current from an input device.

[0143] In the above embodiment, the invention further includes an extractor configured to extract the channel width and the gate length from a circuit design, and transmit the extracted channel width and the gate length to the receiver.

[0144] In the above embodiment, an acquirer is further included, configured to acquire the preset constant from a look-up table (LUT), and transmit the acquired preset constant to the receiver.

[0145] In the above embodiment, the lookup table is also included.

[0146] In the above embodiment, the obtainer is further configured to generate the lookup table.

[0147] In the above embodiment, a user interface is further included, configured to receive the preset mismatch threshold, the voltage difference, and the input current from an input device.

[0148] In another embodiment, a system includes a receiver, a calculator, and a comparator. The receiver collects a predetermined mismatch threshold, an input current associated with a master transistor of a current mirror circuit, the number of current mirror circuits in a semiconductor chip, a chip defect level of the semiconductor chip, a channel width of the master transistor, a gate length of the master transistor, and first and second predetermined constants. The calculator calculates a mismatch value between an output current associated with a slave transistor of the current mirror circuit and the input current based on a voltage difference, the input current, the channel width, the gate length, and the first and second predetermined constants. The comparator compares the mismatch value with the predetermined mismatch threshold and generates a comparison result indicating whether the mismatch value exceeds the predetermined mismatch threshold.

[0149] In the above embodiment, the method further includes receiving the preset mismatch threshold, the input current, the number of the current mirror circuits, and the chip defect level from an input device.

[0150] In the above embodiment, the method further includes extracting the channel width and the gate length from a circuit design, and transmitting the extracted channel width and the gate length to the receiver.

[0151] In the above embodiment, the method further includes obtaining the first and second preset constants from a look-up table (LUT), and transmitting the obtained first and second preset constants to the receiver.

[0152] In the above embodiment, the lookup table (LUT) is also included.

[0153] In the above embodiment, the method further includes generating the lookup table (LUT).

[0154] In the above embodiment, the method further includes receiving the preset mismatch threshold, the input current, the number of the current mirror circuits, and the chip defect level from an input device.

[0155] In the above embodiment, the voltage difference is based on the chip defect level, the number of the current mirror circuits, the channel width, the gate length, and the ratio of the output current to the input current.

[0156] The features of the above-described embodiments will facilitate understanding of the present disclosure by those skilled in the art. Those skilled in the art will appreciate that this disclosure can be used as a basis to design and modify other processes and structures to achieve the same objectives and / or advantages as the above-described embodiments. Those skilled in the art will also appreciate that these equivalent substitutions do not depart from the spirit and scope of the present disclosure and that changes, substitutions, or modifications may be made without departing from the spirit and scope of the present disclosure.

Claims

1. A method for inspecting a current mirror circuit, characterized in that: include: receiving a preset mismatch threshold, a voltage difference, an input current associated with a master transistor of a current mirror circuit, a channel width of the master transistor, a gate length of the master transistor, and a first preset constant; calculating a mismatch value between an output current associated with a slave transistor of the current mirror circuit and the input current based on the voltage difference, the input current, the channel width, the gate length, and the first predetermined constant; as well as comparing the mismatch value with the preset mismatch threshold and generating a comparison result specifying whether the mismatch value exceeds the preset mismatch threshold; When the mismatch value exceeds the preset mismatch threshold, parameters associated with the master or slave transistor are modified, and a device is manufactured based on the modified parameters.

2. The method according to claim 1 further includes receiving the number of current mirror circuits in the semiconductor chip, the chip defect level of the semiconductor chip, and a second preset constant, wherein the voltage difference is related to the chip defect level, the number of the current mirror circuits, the channel width, the gate length, and the ratio of the output current to the input current.

3. A system for inspecting a current mirror circuit, characterized in that: include: A receiver configured to collect: Preset mismatch threshold; a voltage difference between a source voltage of a master transistor of a current mirror circuit and a source voltage of a slave transistor of said current mirror circuit; an input current associated with the master control transistor; The channel width of the main control transistor; a gate length of the master control transistor; as well as Preset constants; a calculator configured to calculate a mismatch value between an output current associated with the slave transistor and the input current based on the voltage difference, the input current, the channel width, the gate length, and the predetermined constant; as well as The comparator is configured to compare the mismatch value with the preset mismatch threshold and generate a comparison result, wherein the comparison result specifies whether the mismatch value exceeds the preset mismatch threshold. 4 . The system of claim 3 , wherein the receiver is configured to receive the preset mismatch threshold, the voltage difference, and the input current from an input device. 5 . The system according to claim 3 , further comprising an acquirer configured to acquire the preset constant from a lookup table and transmit the acquired preset constant to the receiver. 6 . The system of claim 3 , further comprising a user interface configured to receive the predetermined mismatch threshold, the voltage difference, and the input current from an input device.

7. A non-transitory computer-readable medium for testing a current mirror circuit, the medium storing instructions, characterized in that: When executed by one or more data processors of at least one computing device, the operations resulting in include: collect: Preset mismatch threshold; The input current associated with the master transistor of the current mirror circuit; The number of current mirror circuits in a semiconductor chip; a chip defect level of the semiconductor chip; The channel width of the main control transistor; the gate length of the master control transistor; and first and second preset constants; calculating a mismatch value between an output current associated with a slave transistor of the current mirror circuit and the input current based on the voltage difference, the input current, the channel width, the gate length, and the first and second predetermined constants; and The mismatch value is compared with the preset mismatch threshold, and a comparison result is generated, which specifies whether the mismatch value exceeds the preset mismatch threshold. 8 . The non-transitory computer-readable medium of claim 7 , further comprising receiving the preset mismatch threshold, the input current, the number of the current mirror circuits, and the chip defect level from an input device.

9. The non-transitory computer-readable medium of claim 7, further comprising retrieving the channel width and the gate length from a circuit design, and transmitting the thus-retrieved channel width and the gate length to the receiver.

10. The non-transitory computer-readable medium of claim 7, further comprising retrieving the first and second preset constants from a lookup table and transmitting the first and second preset constants thus retrieved to the receiver.

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