Uncertain time sequence test method, system, equipment and medium

Abstract

The invention discloses a non-deterministic time sequence test method, system, equipment and medium, and belongs to the technical field of integrated circuit testing, and the method comprises the steps: in a test process, determining a clock phase relation in real time according to the actual function execution condition of a test circuit, and dynamically adjusting the input clock phase relation through a negative feedback mechanism, and performing fixed-point sampling and outputting a comparison result to finish the test. According to the invention, the signal excitation application position can be dynamically adjusted according to the actual output condition of the to-be-tested device. According to the method, a mixed signal tester is adopted to dynamically adjust an input excitation phase, output sampling is adaptively adjusted according to an actual chip output position, or dynamic matching is carried out by capturing a waveform, so that an accurate test on a non-deterministic time sequence of a chip is realized.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit testing, and in particular relates to a non-deterministic timing testing method, system, device and medium. Background Art

[0002] Integrated circuit testing is an essential step in the IC R&D process. In the semiconductor industry, it is used to verify the functional integrity of ICs. This process occurs throughout all stages of IC development, production, and application. Mixed-signal testers (ATE), specialized equipment for IC testing, are the final step in IC manufacturing, ensuring product quality. Their fundamental principle is to provide power and input stimulus to the circuit under test (DUT) and evaluate the circuit's output.

[0003] With the rapid development of integrated circuits, circuit timing complexity is increasing. Factors such as high-speed, cross-clock domain data transmission and phase-locked loop frequency multiplication and division increase circuit timing uncertainty. Actual project applications have shown that timing uncertainty can be ignored at the application level and does not affect the normal operation of the chip. However, traditional ATE testing relies on applying stimulus and comparing output at fixed times. If the input stimulus cannot be captured by the internal clock in a timely manner, or if the expected comparison cannot be completed at the set sampling position, the chip will be rejected according to the process. Therefore, traditional ATE testing methods cannot meet the testing requirements of circuits with non-deterministic timing. Summary of the Invention

[0004] The object of the present invention is to provide a non-deterministic sequential testing method and system, which is used to solve the problem in the background art that the traditional ATE testing method cannot meet the testing requirements of non-deterministic sequential circuits.

[0005] To achieve the above object, the present invention provides the following technical solutions: A non-deterministic timing test method, comprising: During the test, the clock phase relationship is determined in real time according to the actual function execution of the test circuit, and the input clock phase relationship is dynamically adjusted through a negative feedback mechanism, and the fixed-point sampling output comparison result is completed to complete the test.

[0006] Preferably, the step of determining the clock phase relationship in real time based on the actual functional execution of the test circuit includes: Use spec search to perform shmoo testing on the clock phase in multiple clock domains, scan the clock transition edges, and obtain the phase relationship area that can ensure stable function execution; In the timing file, the application time of the clock transition edge to be scanned is defined as a variable, and the time point of the center of the region is obtained according to the phase relationship region; Assign the time point of the center of the region to the time variables mspec1 and mspec2 applied by the clock stimulus in the timing file, and then perform the functional test.

[0007] Furthermore, scanning the clock transition edge includes: Select to scan the effective transition edges of two key clocks synchronously; Or you can choose to fix one clock phase and then scan the transition edges of another clock.

[0008] Preferably, the method further comprises, when outputting the sampling position, determining a suitable sampling position of the waveform output according to the edge of the reference signal, and dynamically compensating the output sampling point.

[0009] Furthermore, determining a suitable sampling position of the waveform output according to the edge of the reference signal includes: Use spec search or TMU to test the DQS output level transition time point T1; Determining a sampling time dynamic compensation formula based on the relative phase relationship between the signals, and calculating appropriate sampling positions of the DQS and DQ output levels based on the sampling time dynamic compensation formula; Assign the position signal in the sampling time dynamic compensation formula to the sampling time variable defined in the timing file, and then perform the functional test.

[0010] Furthermore, the function expression of the sampling time dynamic compensation formula is: S1=T1+offset1; S2=T1+offset2; Wherein, S1 and S2 are the output sampling positions of the reference signal and the signal to be observed, respectively; offset1 and offset2 are the compensation amounts, respectively; and T1 is the output level conversion time point.

[0011] Furthermore, the method also includes: after the output sampling position, when the timing position of the signal output from the TX end changes, a digital waveform capture method is used to capture the TX valid data output end of a function execution, and the captured digital waveform logic is dynamically matched with the original digital waveform logic sent from the RX end. A non-deterministic timing test system includes: a clock phase relationship determination module, a negative feedback module and a fixed-point sampling module; The clock phase relationship determination module is used to determine the clock phase relationship in real time according to the actual function execution status of the test circuit; The negative feedback module is used to dynamically adjust the input clock phase relationship through a negative feedback mechanism; The fixed-point sampling module is used to perform fixed-point sampling and output comparison results to complete the test.

[0012] A computer device comprising: a processor suitable for executing a computer program; A computer-readable storage medium having a computer program stored therein, wherein when the computer program is executed by the processor, the non-deterministic timing test method as described in any one of the above items is executed.

[0013] A computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements a non-deterministic timing test method as described in any one of the above.

[0014] Compared with the prior art, the present invention has the following beneficial technical effects: The present invention discloses a non-deterministic timing test method, which uses a mixed signal tester to dynamically adjust the input excitation phase, adaptively adjust the output sampling according to the actual chip output position, or dynamically match the captured waveform to accurately test the non-deterministic timing of the chip, thereby avoiding the ATE test's misjudgment of the non-deterministic timing phenomenon, breaking the limitations of the ATE test machine's synchronous sampling test, and solving the bottleneck problem of non-deterministic timing testing during ultra-large-scale integrated circuit ATE testing. The present invention realizes that the signal excitation application position can be dynamically adjusted according to the actual output of the device under test. It can determine the clock phase relationship for stable function execution in real time according to the actual function execution of the circuit. During the test, the input clock phase relationship is dynamically adjusted to ensure the stability of the function output, and output comparison can be completed through fixed-point sampling. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A flow chart for developing dynamic stimulus input in an embodiment of the present invention; Figure 2 Schematic diagram of clock phase variables in an embodiment of the present invention; Figure 3 This is a schematic diagram of fixed-point sampling of chips at different speeds according to an embodiment of the present invention; Figure 4 A flow chart for developing dynamic output sampling in an embodiment of the present invention is provided; Figure 5 Schematic diagram of sampling position variables in an embodiment of the present invention; Figure 6 This is a waveform diagram of the Ethernet GPHY TX output capture in an embodiment of the present invention; Figure 7 Output dynamic sampling development flow chart for the embodiment of the present invention; Figure 8Schematic diagram of waveform capture dynamic matching in an embodiment of the present invention. DETAILED DESCRIPTION

[0016] Hereinafter, only certain exemplary embodiments are briefly described. As will be appreciated by those skilled in the art, the described embodiments may be modified in various ways without departing from the spirit or scope of the present invention. Therefore, the drawings and description are to be considered as illustrative in nature and not restrictive.

[0017] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0018] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0019] In the present invention, unless otherwise expressly specified or limited, terms such as "mounted," "connected," "connect," and "fixed" should be understood broadly. For example, they may refer to fixed connection, detachable connection, or integration; mechanical connection, electrical connection, or communication; direct connection or indirect connection through an intermediate medium; and internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0020] In the present invention, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Furthermore, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0021] It will be understood that when used in this specification and the appended claims, the terms “comprises” and “comprising” indicate the presence of described features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0022] It should also be understood that the terms used in the present specification are only for the purpose of describing particular embodiments and are not intended to limit the present invention. As used in the present specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms unless the context clearly indicates otherwise.

[0023] It should be further understood that the term "and / or" used in the present description and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0024] The accompanying drawings illustrate various schematic diagrams of structures according to embodiments disclosed herein. These figures are not drawn to scale; for clarity, some details are exaggerated and some details may be omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0025] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0026] A non-deterministic timing test method of the present invention includes: During the test, the clock phase relationship is determined in real time according to the actual function execution of the test circuit, and the input clock phase relationship is dynamically adjusted through a negative feedback mechanism, and the fixed-point sampling output comparison result is completed to complete the test.

[0027] Specifically, the dynamic stimulus input testing method in this embodiment of the present invention is primarily used to address the problem of unstable circuit output logic caused by the phase relationship of the external input clock. Unlike conventional fixed-point input stimulus application testing methods, this method allows the signal stimulus application location to be dynamically adjusted based on the actual output of the device under test.

[0028] Adaptive output sampling is primarily used to address issues caused by internal clocks or timing logic, such as stable output within the same circuit but variable output positions between different circuits. Timing offsets are limited to the number of sampling compensation cycles. Unlike traditional testing methods that compare output expectations at fixed points in time, this method dynamically adjusts the output sampling position based on the chip's actual output position.

[0029] Dynamic waveform matching is primarily used to address the problem of high-speed chips experiencing inconsistent output positions during repeated execution of a single chip due to cross-clock domain data transmission and phase-locked loop frequency multiplication. Unlike conventional fixed-point sampling and adaptive output sampling, this method uses digital waveform capture technology to capture the valid output data from a single function execution and dynamically matches it to the expected output waveform logic.

[0030] Actual circuit testing and analysis revealed that the output state of a class of non-deterministic timing chips is affected by the phase relationship of multiple input clocks. When the phase relationship is appropriate, the non-deterministic timing of the chip output disappears, and fixed-point sampling of the output becomes executable. However, phase relationship scans vary between different circuits. This is especially true for high-speed chips, where the clocks themselves flip rapidly. In extreme cases, it can even be impossible to find a uniform clock phase relationship sufficient for large-scale testing. Therefore, the development of a dynamic stimulus input testing method is based on the idea of ​​determining the clock phase relationship for stable functional execution in real time based on the actual functional execution of the circuit. During testing, the input clock phase relationship can be dynamically adjusted to ensure stable functional output, and output comparison can be completed through fixed-point sampling.

[0031] The embodiment of the present invention is implemented by the mixed signal tester V93000 device, and the method flow chart is as follows: Figure 1 shown.

[0032] Specific implementation methods such as Figure 2 As shown: 1) Use spec search to perform shmoo testing on clock phases in multiple clock domains. You can choose to scan the valid transition edges of two key clocks simultaneously, or you can fix one clock phase and scan the transition edges of another clock. 2) Define the application time of the clock edge to be scanned as a variable in the timing file, such as Figure 2In mspec1 and mspec2, according to shmoo, the phase relationship area that can make the function execute stably is obtained, and the time point of the area center is obtained; 3) Assign the obtained time point to the time variables mspec1 and mspec2 applied by the clock stimulus in the timing file, and then perform functional testing.

[0033] The embodiment of the present invention further provides a non-deterministic timing test system, comprising: a clock phase relationship determination module, a negative feedback module and a fixed-point sampling module; The clock phase relationship determination module is used to determine the clock phase relationship in real time according to the actual function execution status of the test circuit; The negative feedback module is used to dynamically adjust the input clock phase relationship through a negative feedback mechanism; The fixed-point sampling module is used to perform fixed-point sampling and output comparison results to complete the test.

[0034] Specifically, in the embodiment of the present invention, a type of non-deterministic timing chip is used as an example of a DDR memory interface device. Although the time characteristics of each DDR memory interface are theoretically the same, due to the influence of manufacturing process factors, the output response positions of different chips may show certain differences. The output waveform positions of DQS and DQ will be different when testing different chips. A certain sample statistics found that the output response position of the chip will show a normal distribution. Most chips will be concentrated near a typical value, and a small number of chips will be distributed in a fast or slow area, such as Figure 3 shown.

[0035] Waveform analysis reveals that while the output positions of different chips are not fixed, the relative phase relationship between different output signals of a single chip is fixed. Therefore, the development idea of ​​the adaptive output sampling test method is: if we can capture the relatively fixed phase position of the key signal, we can use this as the reference signal position during actual testing and dynamically compensate the output sampling points to find the appropriate sampling position for the waveform output. The method flow chart is shown below. Figure 4 shown.

[0036] Specific implementation methods such as Figure 5 As shown: 1) Use spec search or TMU to test the time point T1 of DQS output level transition; 2) Based on the relative phase relationship between signals, the dynamic compensation formula for sampling time is derived: the reference signal uses S1=T1+offset1, and the signal S2=T1+offset2 is used for the position to be observed. The appropriate sampling positions for the DQS and DQ output levels are calculated. DQS and DQ are used to determine whether the expected data stream has the correct output time point T1, the output frequency and duty cycle, and the sampling positions of different signals.

[0037] 3) Assign the calculated S1 and S2 to the sampling time variables defined in the timing file, and then perform the functional test.

[0038] Specific implementation methods such as Figure 5 As shown: 1) Use spec search or TMU unit testing to determine the output level transition time point T1 of the output reference signal DQS; 2) Based on the frequency and duty cycle of the output signal to be observed, as well as the relative phase relationship between the reference signal and the signal to be observed, the dynamic compensation formula for the fixed-point sampling time of the output signal is derived: S1=T1+offset1, S2=T1+offset2 (where S1 and S2 are the output sampling positions of the reference signal and the signal to be observed, and offset1 and offset2 are the compensation amounts). This formula then calculates the appropriate observation sampling positions for the DQS and DQ output levels. 3) Assign the calculated S1 and S2 to the sampling time variables defined in the timing file, and then perform functional testing.

[0039] Specifically, in the embodiments of the present invention, high-speed chips are affected by cross-clock domain data transmission and phase-locked loop frequency multiplication, resulting in repeated execution of a single chip and unstable function output positions. For example, in loopback testing of a certain type of Ethernet transceiver, due to the difference in the circuit's main clock frequency and the GPHY internal clock frequency, and the unstable clock recovery position of the GPHY data transmission clock, data input to the RX end of the same circuit is transmitted to the TX end through an internal loopback path, resulting in unstable timing positions of the output signals for each function execution.

[0040] The waveform recovered by multiple sampling captured by ATE is as follows Figure 6As shown, analysis of the waveform reveals that even if the adaptive output sampling method is used to test and compensate the output sampling position, when the function is executed again after re-assignment, the signal timing position output by the TX end changes again, and the output sampling position at this time is not applicable. However, the output signal waveform observed by an oscilloscope for a single function execution is stable and complete. Therefore, the development idea of ​​the dynamic waveform matching test method is: if the digital waveform capture technology is used to capture the TX valid data output end of a function execution, the captured digital waveform logic can be dynamically matched with the original digital waveform logic sent by the RX end. To ensure the stability of a test, each bit of data logic can be captured at multiple points. The method flow chart is as follows: Figure 7 shown.

[0041] Taking X4-mode Digital Capture as an example, the specific implementation method is as follows Figure 8 As shown: 1) Configure Digital Capture in X4 mode; 2) Perform functional testing and store the digital waveform capture results into an array; 3) Split the array into 4 sub-arrays according to the order of each bit of data logic X4-mode Capture; 4) The expected logic of valid data is dynamically matched with the four sub-arrays, and the functional test PASS / FAIL information is output based on the matching results.

[0042] The present invention proposes a new testing technology for integrated circuits with non-deterministic timing characteristics based on a mixed signal tester. According to the characteristics of non-deterministic timing circuits, methods of dynamic stimulus input, adaptive output sampling and dynamic waveform matching are proposed.

[0043] This invention has been successfully applied to the testing of multiple SoC chips, avoiding the misjudgment of non-deterministic timing phenomena by traditional ATE testing, overcoming the limitations of synchronous sampling testing on ATE testers, improving the yield and efficiency of chip testing screening, reducing chip testing costs, and resolving the bottleneck problem of non-deterministic timing testing during ATE testing of very large-scale integrated circuits. This technology can be widely applied to the testing of similar non-deterministic timing chips, demonstrating its high practicality and versatility.

[0044] The following are device embodiments of the present invention, which can be used to perform the method embodiments of the present invention. For details not disclosed in the device embodiments, please refer to the method embodiments of the present invention.

[0045] In another embodiment of the present invention, a computer device is provided, which includes a processor and a memory, wherein the memory is used to store a computer program, the computer program includes program instructions, and the processor is used to execute the program instructions stored in the computer storage medium. The processor may be a central processing unit (CPU), or may be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. It is the computing core and control core of the terminal, which is suitable for implementing one or more instructions, specifically suitable for loading and executing one or more instructions to implement the corresponding method flow or corresponding function; the processor described in the embodiment of the present invention can be used for the operation of a non-deterministic timing test method.

[0046] In another embodiment of the present invention, a storage medium is provided, specifically a computer-readable storage medium (Memory). The computer-readable storage medium is a memory device in a computer device, used to store programs and data. It is understood that the computer-readable storage medium herein may include both built-in storage media in the computer device and, of course, extended storage media supported by the computer device. The computer-readable storage medium provides storage space, which stores the terminal's operating system. Furthermore, the storage space also stores one or more instructions suitable for being loaded and executed by a processor. These instructions may be one or more computer programs (including program code). It should be noted that the computer-readable storage medium herein may be a high-speed RAM memory or a non-volatile memory, such as at least one disk storage device. The processor may load and execute the one or more instructions stored in the computer-readable storage medium to implement the corresponding steps of the non-deterministic timing testing method described in the above-mentioned embodiment.

[0047] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Furthermore, the present application may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0048] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0049] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0050] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 The steps for the function specified in one or more boxes.

[0051] The above shows and describes the basic principles and main features of the present invention and the advantages of the present invention. It is obvious to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention. Therefore, from all points of view, the embodiments should be regarded as illustrative and non-restrictive. The scope of the present invention is defined by the appended claims rather than the above description, and it is intended that all changes that fall within the meaning and range of equivalents of the claims are included in the present invention. Any reference signs in the claims should not be construed as limiting the claim to which they relate.

[0052] In addition, it should be understood that although this specification describes the embodiments, not every embodiment contains only one independent technical solution. This description is for clarity only. Those skilled in the art should consider the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art. The above content is only for the purpose of illustrating the technical concept of the present invention and cannot be used to limit the scope of protection of the present invention. Any changes made based on the technical solution in accordance with the technical concept proposed by the present invention fall within the scope of protection of the claims of the present invention.

Claims

1. A non-deterministic timing test method, characterized in that: include: During the test, the clock phase relationship is determined in real time according to the actual function execution of the test circuit, and the input clock phase relationship is dynamically adjusted through a negative feedback mechanism, and the fixed-point sampling output comparison result is completed to complete the test.

2. A non-deterministic timing test method according to claim 1, characterized in that: The real-time determination of the clock phase relationship based on the actual functional execution of the test circuit includes: Use spec search to perform shmoo testing on the clock phase in multiple clock domains, scan the clock transition edges, and obtain the phase relationship area that can ensure stable function execution; In the timing file, the application time of the clock transition edge to be scanned is defined as a variable, and the time point of the center of the region is obtained according to the phase relationship region; Assign the time point of the center of the region to the time variables mspec1 and mspec2 applied by the clock stimulus in the timing file, and then perform the functional test.

3. The non-deterministic timing test method according to claim 2, wherein: Scanning the clock transition edge includes: Select to scan the effective transition edges of two key clocks synchronously; Or you can choose to fix one clock phase and then scan the transition edges of another clock.

4. The non-deterministic timing test method according to claim 1, wherein: The method further includes, when outputting the sampling position, determining a suitable sampling position of the waveform output according to the edge of the reference signal, and dynamically compensating the output sampling point.

5. The non-deterministic timing test method according to claim 4, characterized in that: The method of determining a suitable sampling position of the waveform output according to the edge of the reference signal includes: Use spec search or TMU to test the DQS output level transition time point T1; Determining a sampling time dynamic compensation formula based on the relative phase relationship between the signals, and calculating appropriate sampling positions of the DQS and DQ output levels based on the sampling time dynamic compensation formula; Assign the position signal in the sampling time dynamic compensation formula to the sampling time variable defined in the timing file, and then perform the functional test.

6. The non-deterministic timing test method according to claim 5, characterized in that: The functional expression of the sampling time dynamic compensation formula is: S1=T1+offset1; S2=T1+offset2; Wherein, S1 and S2 are the output sampling positions of the reference signal and the signal to be observed, respectively; offset1 and offset2 are the compensation amounts, respectively; and T1 is the output level conversion time point.

7. The non-deterministic timing test method according to claim 1, characterized in that: The method further includes: after outputting the sampling position, when the timing position of the signal output by the TX end changes, using a digital waveform capture method to capture the TX valid data output end of a function execution, and dynamically matching the captured digital waveform logic with the original digital waveform logic sent by the RX end.

8. A non-deterministic timing test system, characterized in that: include: Clock phase relationship determination module, negative feedback module and fixed-point sampling module; The clock phase relationship determination module is used to determine the clock phase relationship in real time according to the actual function execution status of the test circuit; The negative feedback module is used to dynamically adjust the input clock phase relationship through a negative feedback mechanism; The fixed-point sampling module is used to perform fixed-point sampling and output comparison results to complete the test.

9. A computer device, characterized in that: include: a processor suitable for executing a computer program; A computer-readable storage medium, wherein a computer program is stored in the computer-readable storage medium, and when the computer program is executed by the processor, a non-deterministic timing test method according to any one of claims 1 to 7 is executed.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the non-deterministic timing testing method according to any one of claims 1 to 7 is implemented.

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