A low-dropout linear regulator with bidirectional current conduction capability

Abstract

This invention discloses a low-dropout linear regulator (LDO) with bidirectional current conduction capability. The two inputs of the error amplifier are connected to signals VB and FB, respectively. The power stage of the linear transconductance loop serves as the light-load power stage. The first output of the error amplifier is connected to the first input of the linear transconductance loop, the first input of the light-load power stage, and the input of the first source follower. The output of the first source follower is connected to the first input of the heavy-load power stage. The second output of the error amplifier is connected to the second input of the linear transconductance loop, the second input of the light-load power stage, and the input of the second source follower. The output of the second source follower is connected to the second input of the heavy-load power stage. This invention solves the problem of excessive quiescent current in traditional bidirectional current-conducting LDOs under light-load and no-load conditions, and ensures that the output power transistor can be fully turned on when the LDO is operating in open-loop mode.

Description

Technical Field

[0001] This invention relates to a low-dropout linear regulator, and more particularly to a low-dropout linear regulator with bidirectional current conduction capability, belonging to the field of semiconductor integrated circuit technology. Background Technology

[0002] Low-dropout voltage regulators (LDOs) are commonly used in battery-powered systems to provide a stable voltage that does not fluctuate with power supply and load variations. A traditional LDO consists of three modules: an error amplifier, a power regulator transistor, and a feedback resistor. The power regulator transistor is typically a single P-type or N-type transistor, thus only capable of unidirectional current conduction to the output. However, applications such as motor drives, DDR memory, and thermoelectric coolers require LDOs to have bidirectional current conduction capabilities—that is, the output must both supply current to the load and absorb current from the load; it also needs rail-to-rail output capability, and the output stage power transistor needs to be fully conductive.

[0003] Existing technology 1 [R. Hogervorst, JP Tero, RGH Eschauzier and JH Huijsing, "A compact power-efficient 3 V CMOS rail-to-rail input / output operational amplifier for VLSI cell libraries," Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94, San Francisco, CA, USA, 1994, pp. 244-245, doi: 10.1109 / ISSCC.1994.344656.] uses a CLASS-AB operational amplifier structure to build an LDO, which achieves bidirectional current conduction based on the working principle of a linear transconductance loop. However, if the size of the output power regulation transistor is large, it will lead to a large quiescent current of the LDO under light load and no-load conditions, resulting in a large quiescent power consumption.

[0004] Existing technology 2 [S. Asefi, A. Saberkari, H. Martinez-Garcia and E. Alarcon, "Low-Quiescent Current Class-AB CMOS LDO Voltage Regulator," 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, 2018, pp. 1-4, doi: 10.1109 / ISCAS.2018.8351006.] introduces an error into the output stage of the error amplifier, preventing the PMOS power regulator and NMOS regulator from conducting simultaneously under no-load and light-load conditions. This effectively reduces static power consumption. However, it also means that the LDO cannot function properly under light-load and no-load conditions, failing to guarantee output accuracy, and the output stage power transistor cannot be fully turned on.

[0005] Prior art 3, Chinese patent number CN202410339151.3, discloses a Class-AB operational amplifier circuit and system. Based on prior art 1, it achieves the purpose of controlling the output stage quiescent current by adjusting the bias current of the linear transconductance loop. However, if the size of the output stage power adjustment transistor is very large, it is fundamentally impossible to improve the problem of excessive quiescent current and will affect the loop stability.

[0006] Prior art 4, Chinese patent number CN202410442690.X, discloses a bidirectional current low dropout linear regulator. Based on prior art 1, it introduces two additional operational amplifiers as level shifters to reduce the static current of the LDO under light load and no load. However, the circuit is complex, introduces additional static power consumption, increases the chip area significantly, and due to the presence of the level shifters, the large-size output stage power transistor cannot be fully turned on when the LDO is in open-loop operation.

[0007] In summary, traditional LDOs only have unidirectional current conduction capability. However, applications such as motor drives, DDR memory, and semiconductor thermoelectric coolers require LDOs to have bidirectional current conduction capability, meaning the LDO's output can both supply current to the load and absorb current from the output. Simultaneously, rail-to-rail output capability is required, and the output stage power transistors need to be fully conductive. Existing technologies 1 and 3 use a CLASS-AB operational amplifier architecture to achieve bidirectional current conduction and rail-to-rail output LDOs. However, under light or no-load conditions, the PMOS and NMOS power regulators will conduct simultaneously. With large-size power regulators, even with a linear transconductance loop controlling the gate voltage of the power stage, a large quiescent current is unavoidable. Existing technology 4 adds a level shifter to existing technology 1, which can solve the problem of excessive quiescent current under no-load and light-load conditions. However, the drawback is that the output stage power transistors cannot be fully conductive. Summary of the Invention

[0008] The technical problem to be solved by the present invention is to provide a low dropout linear regulator with bidirectional current conduction capability, which has a low quiescent current under light load and no-load conditions, and the output regulating transistor of the heavy load power stage can be fully turned on when the LDO is in open-loop operation.

[0009] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0010] A low-dropout linear regulator with bidirectional current conduction capability includes an error amplifier, a linear transconductance loop, a light-load power stage, a heavy-load power stage, a first source follower, a second source follower, and a voltage divider feedback circuit. The first input terminal of the error amplifier is connected to signal VB, and the second input terminal of the error amplifier is connected to signal FB. The power stage of the linear transconductance loop serves as the light-load power stage. The first output terminal of the error amplifier is connected to the first input terminal of the linear transconductance loop, the first input terminal of the light-load power stage, and the input terminal of the first source follower. The output terminal of the first source follower is connected to the first input terminal of the heavy-load power stage. The second output terminal of the error amplifier is connected to the second input terminal of the linear transconductance loop, the second input terminal of the light-load power stage, and the input terminal of the second source follower. The output terminal of the second source follower is connected to the second input terminal of the heavy-load power stage. The output terminals of the light-load power stage and the heavy-load power stage are connected to the input terminal of the voltage divider feedback circuit and generate an output signal VOUT. The output terminal of the voltage divider feedback circuit generates signal FB.

[0011] Further, the error amplifier includes PMOS transistors M1, M2, M3, M4, M5, M6, M7, and M8, and a tail current source I1. The gate of PMOS transistor M1 serves as the first input terminal of the error amplifier and is connected to signal VB. The gate of PMOS transistor M2 serves as the second input terminal of the error amplifier and is connected to signal FB. The source of PMOS transistor M1 is connected to one end of the tail current source I1 and the source of PMOS transistor M2. The drain of PMOS transistor M1 is connected to the drain of NMOS transistor M3, the gate of NMOS transistor M3, and the gate of NMOS transistor M6, and is connected to a bias voltage VBN2. The drain of PMOS transistor M2 is connected to the NMOS transistor M8. The drain of M4, the gate of NMOS transistor M4, and the gate of NMOS transistor M5 are connected and connected to the bias voltage VBN1. The drain of NMOS transistor M5 serves as the second output terminal of the error amplifier and generates the bias voltage VGN1. The sources of NMOS transistors M3, M4, M5, and M6 are grounded. The drain of NMOS transistor M6 is connected to the drain of PMOS transistor M7, the gate of PMOS transistor M7, and the gate of PMOS transistor M8 and connected to the bias voltage VBP1. The drain of PMOS transistor M8 serves as the first output terminal of the error amplifier and generates the bias voltage VGP1. The source of PMOS transistor M7, the other end of the tail current source I1, and the source of PMOS transistor M8 are connected to the power supply VDD.

[0012] Further, the linear transconductance loop includes PMOS transistors M9, M10, M11, M12, M13, M14, MP1, MN1, current source I2, and current source I3. The source of PMOS transistor M9 is connected to the drain of NMOS transistor M10 and serves as the first input terminal of the linear transconductance loop, connected to the bias voltage VGP1. The drain of PMOS transistor M9 is connected to the source of NMOS transistor M10 and serves as the second input terminal of the linear transconductance loop, connected to the bias voltage VGN1. The gate of PMOS transistor M9 is connected to the gate of PMOS transistor M12, MP1, MN1, current source I2, and current source I3. The drain of OS transistor M12 is connected to one end of current source I3. The source of PMOS transistor M12 is connected to the drain and gate of PMOS transistor M11. The gate of NMOS transistor M10 is connected to the gate of NMOS transistor M13, the drain of NMOS transistor M13 is connected to one end of current source I2, the source of NMOS transistor M13 is connected to the drain and gate of NMOS transistor M14, the source of PMOS transistor M11, the other end of current source I2, and the source of PMOS transistor MP1 are connected to power supply VDD, and the other end of current source I3, the source of NMOS transistor M14, and the source of NMOS transistor MN1 are grounded.

[0013] Furthermore, the PMOS transistor MP1 and NMOS transistor MN1 constitute a light-load power stage. The gate of PMOS transistor MP1 serves as the first input terminal of the light-load power stage and is connected to the bias voltage VGP1. The gate of NMOS transistor MN1 serves as the second input terminal of the light-load power stage and is connected to the bias voltage VGN1. The drain of PMOS transistor MP1 is connected to the drain of NMOS transistor MN1 and serves as the output terminal of the light-load power stage to generate the output signal VOUT.

[0014] Furthermore, the heavy-load power stage includes a PMOS transistor MP2 and an NMOS transistor MN2. The source of the PMOS transistor MP2 is connected to the power supply VDD. The gate of the PMOS transistor MP2 serves as the first input terminal of the heavy-load power stage and is connected to the bias voltage VGP2. The drain of the PMOS transistor MP2 is connected to the drain of the NMOS transistor MN2 and serves as the output terminal of the heavy-load power stage to generate the output signal VOUT. The gate of the NMOS transistor MN2 serves as the second input terminal of the heavy-load power stage and is connected to the bias voltage VGN2. The source of the NMOS transistor MN2 is grounded.

[0015] Furthermore, the first source follower includes a PMOS transistor M15, a PMOS transistor M16, an NMOS transistor M17, and a resistor R3. The source of the PMOS transistor M15 is connected to the power supply VDD, and the gate of the PMOS transistor M15 is connected to the bias voltage VBP1. The drain of the PMOS transistor M15 is connected to the source of the PMOS transistor M16 and the drain of the NMOS transistor M17, and serves as the output terminal of the first source follower to generate a bias voltage VGP2. The gate of the PMOS transistor M16 serves as the input terminal of the first source follower and is connected to the bias voltage VGP1. The drain of the PMOS transistor M16 is connected to one end of the resistor R3, and the gate of the NMOS transistor M17 is connected to the bias voltage VBN1. The other end of the resistor R3 and the source of the NMOS transistor M17 are grounded.

[0016] Furthermore, the second source follower includes an NMOS transistor M18, an NMOS transistor M19, a PMOS transistor M20, and a resistor R4. One end of the resistor R4 is connected to the power supply VDD via the source of the PMOS transistor M20, and the other end of the resistor R4 is connected to the drain of the NMOS transistor M18. The gate of the NMOS transistor M18 serves as the input terminal of the second source follower and is connected to a bias voltage VGN1. The source of the NMOS transistor M18 is connected to the drain of the NMOS transistor M19 and the drain of the PMOS transistor M20, and serves as the output terminal of the second source follower, generating a bias voltage VGN2. The gate of the PMOS transistor M20 is connected to a bias voltage VBP1, and the gate of the NMOS transistor M19 is connected to a bias voltage VBN1. The source of the NMOS transistor M19 is grounded.

[0017] Furthermore, the voltage divider feedback circuit includes resistors R1 and R2. One end of the power supply R1 is connected to the signal VC. The other end of resistor R1 is connected to one end of resistor R2 and serves as the output terminal of the voltage divider feedback circuit to generate the signal FB. The other end of resistor R2 is connected to the output signal VOUT.

[0018] Furthermore, it also includes a load circuit, which includes a load resistor RL and a load capacitor CL. One end of the resistor RL and one end of the capacitor CL are connected to the output signal VOUT, the other end of the resistor RL is connected to the signal VS, and the other end of the capacitor CL is grounded.

[0019] Compared with existing technologies, this invention has the following advantages and effects: This invention provides a low-dropout linear regulator with bidirectional current conduction capability. The error amplifier adopts a CLASS-AB output structure, and two power branches are designed: a light-load power stage and a heavy-load power stage. A linear transconductance loop structure is used to control the gate voltage of the output regulating transistor in the light-load power stage. The gate voltage of the light-load power stage regulating transistor is level-shifted through a source follower circuit to control the gate voltage of the heavy-load power stage regulating transistor. This ensures that the heavy-load output stage can be almost turned off under light-load and no-load conditions, achieving the purpose of reducing quiescent current. Furthermore, as the load current increases, the heavy-load power stage can gradually turn on. When the LDO is operating in open-loop mode, the source follower circuit of this invention enables the heavy-load power stage regulating transistor to be fully turned on. This invention solves the problem of excessive quiescent current in traditional bidirectional current-conducting LDOs under light-load and no-load conditions, and ensures that the output power transistor of the LDO can be fully turned on when operating in open-loop mode. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of a low-dropout linear regulator with bidirectional current conduction capability according to the present invention.

[0021] Figure 2 This is a schematic diagram of a typical linear transconductance ring structure according to an embodiment of the present invention.

[0022] Figure 3 This is a schematic diagram showing the change of the gate voltage of the power regulating transistor with load current according to an embodiment of the present invention. Detailed Implementation

[0023] To illustrate in detail the technical solutions adopted by the present invention to achieve the intended technical objectives, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Furthermore, the technical means or technical features in the embodiments of the present invention can be replaced without creative effort. The present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0024] like Figure 1 As shown, a low-dropout linear regulator with bidirectional current conduction capability according to the present invention includes an error amplifier, a linear transconductance loop, a light-load power stage, a heavy-load power stage, a first source follower, a second source follower, and a voltage divider feedback circuit. The first input terminal of the error amplifier is connected to signal VB, and the second input terminal of the error amplifier is connected to signal FB. The power stage of the linear transconductance loop serves as the light-load power stage. The first output terminal of the error amplifier is connected to the first input terminal of the linear transconductance loop, the first input terminal of the light-load power stage, and the input terminal of the first source follower. The output terminal of the first source follower is connected to the first input terminal of the heavy-load power stage. The second output terminal of the error amplifier is connected to the second input terminal of the linear transconductance loop, the second input terminal of the light-load power stage, and the input terminal of the second source follower. The output terminal of the second source follower is connected to the second input terminal of the heavy-load power stage. The output terminals of the light-load power stage and the heavy-load power stage are connected to the input terminal of the voltage divider feedback circuit and generate an output signal VOUT. The output terminal of the voltage divider feedback circuit generates signal FB.

[0025] The error amplifier includes PMOS transistors M1, M2, M3, M4, M5, M6, M7, and M8, and a tail current source I1. The gate of PMOS transistor M1 serves as the first input terminal of the error amplifier and is connected to signal VB. The gate of PMOS transistor M2 serves as the second input terminal of the error amplifier and is connected to signal FB. The source of PMOS transistor M1 is connected to one end of the tail current source I1 and the source of PMOS transistor M2. The drain of PMOS transistor M1 is connected to the drain of NMOS transistor M3, the gate of NMOS transistor M3, and the gate of NMOS transistor M6, and is connected to a bias voltage VBN2. The drain of PMOS transistor M2 is connected to the tail current source I1 and the tail current source I1. The drain of NMOS transistor M4, the gate of NMOS transistor M5, and the gate of NMOS transistor M5 are connected to a bias voltage VBN1. The drain of NMOS transistor M5 serves as the second output terminal of the error amplifier and generates a bias voltage VGN1. The sources of NMOS transistors M3, M4, M5, and M6 are grounded. The drain of NMOS transistor M6 is connected to the drain of PMOS transistor M7, the gate of PMOS transistor M7, and the gate of PMOS transistor M8 and a bias voltage VBP1. The drain of PMOS transistor M8 serves as the first output terminal of the error amplifier and generates a bias voltage VGP1. The source of PMOS transistor M7, the other end of the tail current source I1, and the source of PMOS transistor M8 are connected to the power supply VDD.

[0026] The linear transconductance loop includes PMOS transistors M9, M10, M11, M12, M13, M14, MP1, MN1, current source I2, and current source I3. The source of PMOS transistor M9 is connected to the drain of NMOS transistor M10 and serves as the first input terminal of the linear transconductance loop, connected to the bias voltage VGP1. The drain of PMOS transistor M9 is connected to the source of NMOS transistor M10 and serves as the second input terminal of the linear transconductance loop, connected to the bias voltage VGN1. The gate of PMOS transistor M9 is connected to the gate of PMOS transistor M12, and the gate of PMOS transistor M14 is connected to the source of NMOS transistor M10. The drain of PMOS transistor M12 is connected to one end of current source I3. The source of PMOS transistor M12 is connected to the drain and gate of PMOS transistor M11. The gate of NMOS transistor M10 is connected to the gate of NMOS transistor M13, the drain of NMOS transistor M13 is connected to one end of current source I2, the source of NMOS transistor M13 is connected to the drain and gate of NMOS transistor M14, the source of PMOS transistor M11, the other end of current source I2, and the source of PMOS transistor MP1 are connected to power supply VDD, and the other end of current source I3, the source of NMOS transistor M14, and the source of NMOS transistor MN1 are grounded.

[0027] To illustrate the embodiments of the present invention, it is necessary to briefly introduce the working principle of a typical linear transconductance ring. For example... Figure 2 As shown, ignoring body effect and channel modulation effect, according to the saturation current formula of the MOSFET:

[0028]

[0029]

[0030] in It is the source and drain current of the MOSFET; This refers to the carrier mobility of a MOSFET. There is a difference between NMOS and PMOS, but it is not distinguished here. W / L is the gate oxide capacitance of the MOSFET; W / L is the width-to-length ratio of the MOSFET. This represents the gate-source voltage of the MOSFET. This is the threshold voltage of the MOSFET.

[0031] Figure 2 The gate-source voltages of M21, M23, M24, and MP satisfy the following relationship:

[0032]

[0033] Assuming the threshold voltage of all PMOS transistors They are all the same. By setting the current values ​​of I6, I5, and I4 appropriately, M21 and M23 can be matched to obtain... According to the above The expression for the static current of MP. The following relationship must be satisfied:

[0034]

[0035] According to the above formula, the quiescent current of the output PMOS is supplied by a fixed bias current source. And it is determined by the size of MP and M24.

[0036] Similarly, Figure 2 The gate-source voltages of M22, M25, M26, and MN satisfy the following relationship:

[0037]

[0038] The static current of MN is derived through formula derivation. The following relationship must be satisfied:

[0039]

[0040] According to the above formula, the quiescent current of the output NMOS is supplied by a fixed bias current source. And it is determined by the dimensions of MN and M26.

[0041] In applications with high load current, MP and MN must ensure low on-resistance. Figure 2 The dimensions of the output power transistors MP and MN are often much larger than those of M24 and M26. According to the formula above, reducing... and Multiples or reduction of branch current and Both can control the output stage quiescent current. However, when the output capacitor is large, a large-size power transistor is used in the output stage. The gate parasitic capacitance of the power transistor is large. At this time, the LDO has two poles: one is the internal pole formed by the gate parasitic capacitance of the power transistor, and the other is the output pole formed by the output capacitor. If the output stage quiescent current is too small under light no-load conditions, both the internal pole and the output pole will be at very low frequency positions. It is difficult for compensation to meet the loop stability across the entire load range. Therefore, the traditional LDO structure based on linear transconductance loop needs to make a trade-off between the output stage quiescent current and loop stability.

[0042] PMOS transistor MP1 and NMOS transistor MN1 constitute a light-load power stage. The gate of PMOS transistor MP1 serves as the first input terminal of the light-load power stage and is connected to the bias voltage VGP1. The gate of NMOS transistor MN1 serves as the second input terminal of the light-load power stage and is connected to the bias voltage VGN1. The drain of PMOS transistor MP1 is connected to the drain of NMOS transistor MN1 and serves as the output terminal of the light-load power stage to generate the output signal VOUT.

[0043] The heavy-load power stage includes a PMOS transistor MP2 and an NMOS transistor MN2. The source of PMOS transistor MP2 is connected to the power supply VDD. The gate of PMOS transistor MP2 serves as the first input terminal of the heavy-load power stage and is connected to the bias voltage VGP2. The drain of PMOS transistor MP2 is connected to the drain of NMOS transistor MN2 and serves as the output terminal of the heavy-load power stage to generate the output signal VOUT. The gate of NMOS transistor MN2 serves as the second input terminal of the heavy-load power stage and is connected to the bias voltage VGN2. The source of NMOS transistor MN2 is grounded.

[0044] The dimensions of heavy-load power stage PMOS transistor MP2 and NMOS transistor MN2 are much larger than the dimensions of light-load power stage PMOS transistor MP1 and NMOS transistor MN1.

[0045] The first source follower includes PMOS transistors M15, M16, and M17, and resistor R3. The source of PMOS transistor M15 is connected to the power supply VDD, and the gate of PMOS transistor M15 is connected to the bias voltage VBP1. The drain of PMOS transistor M15 is connected to the source of PMOS transistor M16 and the drain of NMOS transistor M17, and serves as the output of the first source follower to generate the bias voltage VGP2. The gate of PMOS transistor M16 serves as the input of the first source follower and is connected to the bias voltage VGP1. The drain of PMOS transistor M16 is connected to one end of resistor R3, and the gate of NMOS transistor M17 is connected to the bias voltage VBN1. The other end of resistor R3 and the source of NMOS transistor M17 are grounded.

[0046] PMOS transistor M16 acts as a source follower, boosting the bias voltage VGP1 to generate the bias voltage signal VGP2. PMOS transistors M15 and M17 act as current sources, and the difference between them serves as the bias current for PMOS transistor M16. The boosted voltage value can be adjusted by changing the dimensions of PMOS transistors M15, M16, and M17. When the LDO operates in closed-loop mode, the pull-up current of PMOS transistor M15 is greater than the pull-down current of NMOS transistor M17, which boosts the voltage at the bias voltage VGP1 node by a certain value, controlling the bias voltage VGP2 and thus controlling the on / off state of the heavy-load power stage. When the LDO operates in open-loop mode, under the influence of the error amplifier's load current source, the pull-up current of PMOS transistor M15 is less than the pull-down current of NMOS transistor M17, allowing the bias voltage VGP2 to be pulled down to GND, thus enabling the output stage power transistor PMOS transistor MP2 to conduct fully.

[0047] The second source follower includes NMOS transistors M18 and M19, PMOS transistor M20, and resistor R4. One end of resistor R4 is connected to the source of PMOS transistor M20 and the power supply VDD. The other end of resistor R4 is connected to the drain of NMOS transistor M18. The gate of NMOS transistor M18 serves as the input of the second source follower and is connected to the bias voltage VGN1. The source of NMOS transistor M18 is connected to the drain of NMOS transistor M19 and the drain of PMOS transistor M20, and serves as the output of the second source follower, generating a bias voltage VGN2. The gate of PMOS transistor M20 is connected to the bias voltage VBP1. The gate of NMOS transistor M19 is connected to the bias voltage VBN1. The source of NMOS transistor M19 is grounded.

[0048] NMOS transistor M18 acts as a source follower, reducing the bias voltage VGN1 to generate the bias voltage VGN2. NMOS transistors M19 and M20 act as current sources, and the difference between them serves as the bias current for NMOS transistor M18. The voltage drop can be adjusted by changing the dimensions of NMOS transistors M18, M19, and M20. When the LDO operates in closed-loop mode, the pull-down current of NMOS transistor M19 is greater than the pull-up current of PMOS transistor M20, which reduces the voltage at the bias voltage VGN1 node by a certain value, controlling the bias voltage VGN2 and thus controlling the quiescent current of the heavy-load power stage. When the LDO operates in open-loop mode, under the influence of the error amplifier's load current source, the pull-down current of NMOS transistor M19 is less than the pull-up current of PMOS transistor M20, allowing the bias voltage VGN2 to be pulled up to VDD, thus enabling the output stage power transistor NMOS transistor MN2 to conduct fully.

[0049] The voltage-dividing feedback circuit includes resistor R1 and resistor R2. One end of power supply R1 is connected to signal VC, the other end of resistor R1 is connected to one end of resistor R2 and serves as the output end of the voltage-dividing feedback circuit to generate signal FB, and the other end of resistor R2 is connected to output signal VOUT.

[0050] A low dropout linear regulator with bidirectional current conduction ability according to the present invention further includes a load circuit. The load circuit includes load resistor RL and load capacitor CL. One end of resistor RL and one end of capacitor CL are connected to output signal VOUT, the other end of resistor R1 is connected to signal VS, and the other end of capacitor CL is grounded.

[0051] As Figure 3 shown, when VS < VOUT, the output signal VOUT at the output end provides current SourceCurrent to the load circuit; when VS > VOUT, the output end absorbs the current Sink Current injected by the load circuit. When the load current is 0 or lightly loaded, the gate bias voltage VGP2 of the heavy-load power stage PMOS transistor MP2 is lifted to a potential close to VDD by the first source follower. At this time, VDD - VGP2 < VTHP (high-side power transistor threshold voltage), and PMOS transistor MP2 can be completely turned off; the gate drive voltage VGN2 of the heavy-load power adjustment transistor MN2 is lowered to a potential close to 0 by the second source follower circuit. At this time, VGN2 < VTHN (low-side power transistor threshold voltage), and MN2 can be completely turned off. Therefore, under light-load and no-load conditions, only the light-load power stage loop works, and the heavy-load power stage of the LDO can be completely turned off. When Sink Current gradually increases, VGN2 gradually rises with VGN1, and the heavy-load power stage NMOS transistor MN2 can be gradually turned on; similarly, when Source Current gradually increases, VGP2 gradually drops with VGP1, and the heavy-load power stage PMOS transistor MP2 can be gradually turned on. Therefore, as the load current gradually increases, the light-load power stage and the heavy-load power stage can work simultaneously. And when the output signal VOUT of the LDO reaches VDD or 0, that is, when the LDO is in open-loop operation, under the action of the first source follower and the second source follower, VGP2 can be pulled down to 0, and VGN2 can be pulled up to VDD, realizing full conduction of the heavy-load power transistors.

[0052] This invention provides a low-dropout linear regulator (LDO) with bidirectional current conduction capability. The error amplifier employs a CLASS-AB output structure, featuring two power branches: a light-load power stage and a heavy-load power stage. A linear transconductance loop structure controls the gate voltage of the output regulating transistor in the light-load power stage. The gate voltage of the light-load power stage regulating transistor is level-shifted by a source follower circuit to control the gate voltage of the heavy-load power stage regulating transistor. This ensures that the heavy-load output stage can be nearly shut off under light-load and no-load conditions, reducing quiescent current. Furthermore, as the load current increases, the heavy-load power stage gradually turns on. When the LDO is operating in open-loop mode, the source follower circuit of this invention ensures that the heavy-load power stage regulating transistor is fully turned on. This invention solves the problem of excessive quiescent current in traditional bidirectional current-conducting LDOs under light-load and no-load conditions, and ensures that the output power transistor is fully turned on when the LDO is operating in open-loop mode.

[0053] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent substitutions, and improvements made to the above embodiments without departing from the scope of the present invention, based on the technical essence of the present invention and within the spirit and principles of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A low-dropout linear regulator with bidirectional current conduction capability, characterized in that: It includes an error amplifier, a linear transconductance loop, a light-load power stage, a heavy-load power stage, a first source follower, a second source follower, and a voltage divider feedback circuit. The first input terminal of the error amplifier is connected to signal VB, and the second input terminal of the error amplifier is connected to signal FB. The power stage of the linear transconductance loop serves as the light-load power stage. The first output terminal of the error amplifier is connected to the first input terminal of the linear transconductance loop, the first input terminal of the light-load power stage, and the input terminal of the first source follower. The output terminal of the first source follower is connected to the first input terminal of the heavy-load power stage. The second output terminal of the error amplifier is connected to the second input terminal of the linear transconductance loop, the second input terminal of the light-load power stage, and the input terminal of the second source follower. The output terminal of the second source follower is connected to the second input terminal of the heavy-load power stage. The output terminals of the light-load power stage and the heavy-load power stage are connected to the input terminal of the voltage divider feedback circuit and generate an output signal VOUT. The output terminal of the voltage divider feedback circuit generates signal FB. The light-load power stage includes a PMOS transistor MP1 and an NMOS transistor MN1. The gate of the PMOS transistor MP1 serves as the first input terminal of the light-load power stage and is connected to a bias voltage VGP1. The gate of the NMOS transistor MN1 serves as the second input terminal of the light-load power stage and is connected to a bias voltage VGN1. The drain of the PMOS transistor MP1 is connected to the drain of the NMOS transistor MN1 and serves as the output terminal of the light-load power stage to generate an output signal VOUT. The heavy-load power stage includes a PMOS transistor MP2 and an NMOS transistor MN2. The source of the PMOS transistor MP2 is connected to the power supply VDD. The gate of the PMOS transistor MP2 serves as the first input terminal of the heavy-load power stage and is connected to the bias voltage VGP2. The drain of the PMOS transistor MP2 is connected to the drain of the NMOS transistor MN2 and serves as the output terminal of the heavy-load power stage to generate the output signal VOUT. The gate of the NMOS transistor MN2 serves as the second input terminal of the heavy-load power stage and is connected to the bias voltage VGN2. The source of the NMOS transistor MN2 is grounded.

2. A low-dropout linear regulator with bidirectional current conduction capability according to claim 1, characterized in that: The error amplifier includes PMOS transistors M1, M2, M3, M4, M5, M6, M7, and M8, and a tail current source I1. The gate of PMOS transistor M1 serves as the first input terminal of the error amplifier and is connected to signal VB. The gate of PMOS transistor M2 serves as the second input terminal of the error amplifier and is connected to signal FB. The source of PMOS transistor M1 is connected to one end of the tail current source I1 and the source of PMOS transistor M2. The drain of PMOS transistor M1 is connected to the drain of NMOS transistor M3, the gate of NMOS transistor M3, and the gate of NMOS transistor M6, and is connected to a bias voltage VBN2. The drain of PMOS transistor M2 is connected to NMOS transistor M4... The drain of NMOS transistor M3, the gate of NMOS transistor M4, and the gate of NMOS transistor M5 are connected to a bias voltage VBN1. The drain of NMOS transistor M5 serves as the second output terminal of the error amplifier and generates a bias voltage VGN1. The sources of NMOS transistors M3, M4, M5, and M6 are grounded. The drain of NMOS transistor M6 is connected to the drain of PMOS transistor M7, the gate of PMOS transistor M7, and the gate of PMOS transistor M8 and is connected to a bias voltage VBP1. The drain of PMOS transistor M8 serves as the first output terminal of the error amplifier and generates a bias voltage VGP1. The source of PMOS transistor M7, the other end of the tail current source I1, and the source of PMOS transistor M8 are connected to the power supply VDD.

3. A low-dropout linear regulator with bidirectional current conduction capability according to claim 1, characterized in that: The linear transconductance loop includes PMOS transistors M9, M10, M11, M12, M13, M14, MP1, MN1, current source I2, and current source I3. The source of PMOS transistor M9 is connected to the drain of NMOS transistor M10 and serves as the first input terminal of the linear transconductance loop, connected to the bias voltage VGP1. The drain of PMOS transistor M9 is connected to the source of NMOS transistor M10 and serves as the second input terminal of the linear transconductance loop, connected to the bias voltage VGN1. The gate of PMOS transistor M9 is connected to the gate of PMOS transistor M12 and the gate of PMOS transistor M14. The drain of M12 is connected to one end of current source I3. The source of PMOS transistor M12 is connected to the drain and gate of PMOS transistor M11. The gate of NMOS transistor M10 is connected to the gate of NMOS transistor M13, the drain of NMOS transistor M13 is connected to one end of current source I2, the source of NMOS transistor M13 is connected to the drain and gate of NMOS transistor M14, the source of PMOS transistor M11, the other end of current source I2, and the source of PMOS transistor MP1 are connected to power supply VDD, and the other end of current source I3, the source of NMOS transistor M14, and the source of NMOS transistor MN1 are grounded.

4. A low-dropout linear regulator with bidirectional current conduction capability according to claim 1, characterized in that: The first source follower includes a PMOS transistor M15, a PMOS transistor M16, an NMOS transistor M17, and a resistor R3. The source of the PMOS transistor M15 is connected to the power supply VDD, and the gate of the PMOS transistor M15 is connected to the bias voltage VBP1. The drain of the PMOS transistor M15 is connected to the source of the PMOS transistor M16 and the drain of the NMOS transistor M17, and serves as the output terminal of the first source follower to generate the bias voltage VGP2. The gate of the PMOS transistor M16 serves as the input terminal of the first source follower and is connected to the bias voltage VGP1. The drain of the PMOS transistor M16 is connected to one end of the resistor R3, and the gate of the NMOS transistor M17 is connected to the bias voltage VBN1. The other end of the resistor R3 and the source of the NMOS transistor M17 are grounded.

5. A low-dropout linear regulator with bidirectional current conduction capability according to claim 1, characterized in that: The second source follower includes NMOS transistors M18 and M19, PMOS transistor M20, and resistor R4. One end of resistor R4 is connected to the source of PMOS transistor M20 and the power supply VDD. The other end of resistor R4 is connected to the drain of NMOS transistor M18. The gate of NMOS transistor M18 serves as the input of the second source follower and is connected to the bias voltage VGN1. The source of NMOS transistor M18 is connected to the drain of NMOS transistor M19 and the drain of PMOS transistor M20, and serves as the output of the second source follower, generating a bias voltage VGN2. The gate of PMOS transistor M20 is connected to the bias voltage VBP1. The gate of NMOS transistor M19 is connected to the bias voltage VBN1. The source of NMOS transistor M19 is grounded.

6. A low-dropout linear regulator with bidirectional current conduction capability according to claim 1, characterized in that: The voltage divider feedback circuit includes resistors R1 and R2. One end of power supply R1 is connected to signal VC. The other end of resistor R1 is connected to one end of resistor R2 and serves as the output terminal of the voltage divider feedback circuit to generate signal FB. The other end of resistor R2 is connected to the output signal VOUT.

7. A low-dropout linear regulator with bidirectional current conduction capability according to claim 1, characterized in that: It also includes a load circuit, which consists of a load resistor RL and a load capacitor CL. One end of the resistor RL and one end of the capacitor CL are connected to the output signal VOUT, the other end of the resistor RL is connected to the signal VS, and the other end of the capacitor CL is grounded.

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