Integrated circuit supporting physical unclonable function, system on chip including same, and method of operating same

Abstract

The present disclosure relates to an integrated circuit including an integrated circuit supporting a physical unclonable function (PUF). An example integrated circuit includes: a PUF block including an array of PUF cells; and a controller configured to generate the security key based on the PUF data, the PUF data being generated based on the PUF block. The controller is configured to perform an error correction operation on the PUF data to generate an initial key, perform a length extension operation on the initial key to generate an intermediate key, and generate at least one of a plurality of final keys as a security key from the intermediate key.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2024-0030904 filed on March 4, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to an integrated circuit supporting a physically unclonable function, a system on chip including the integrated circuit, and an operating method of the integrated circuit. Background Art

[0004] In recent years, with the rapid development of wired and wireless communication technologies and smart device-related technologies, the demand for building security systems for the safe use of such technologies has also increased. Consequently, security technologies using physically unclonable functions (PUFs) are attracting attention. A PUF cell is a unit implemented within a semiconductor chip that generates an unpredictable random value by exploiting process variations that occur during semiconductor manufacturing. When security keys are generated using a PUF cell, the duplication of important keys stored in secure devices, such as security keys, can be fundamentally prevented.

[0005] At the same time, the security key generated by a PUF-enabled integrated circuit can be determined during a registration phase included in the wafer testing phase of the PUF unit. Once the auxiliary data generated as a result of the registration phase is stored in the non-volatile memory of the integrated circuit, the integrated circuit can generate the same security key simply by using the auxiliary data. When the integrated circuit is exposed to an external hacking attack, the method of changing the security key by re-performing the registration phase by the integrated circuit may be inefficient because re-performing the wafer testing phase may require additional circuitry or costs. Therefore, existing PUF-enabled integrated circuits are vulnerable to external hacking attacks due to their structure in which only the same security key is repeatedly generated. Summary of the Invention

[0006] The present disclosure relates to an integrated circuit including an integrated circuit for providing enhanced security by generating at least one final key of a plurality of final keys as a security key based on PUF data generated using a minimal physically unclonable function (PUF) block; a system on a chip including the system on a chip; and a method of operating the integrated circuit.

[0007] In general, according to some aspects, an integrated circuit supporting a physically unclonable function (PUF) includes: a PUF block including an array of PUF cells; and a controller configured to generate a security key based on PUF data generated using the PUF block, wherein the controller is configured to: perform an error correction operation on the PUF data to generate an initial key, perform a length extension operation on the initial key to generate an intermediate key, and generate at least one final key of a plurality of final keys as the security key based on the intermediate key.

[0008] In general, according to some aspects, a method of operating an integrated circuit, the integrated circuit including a PUF block for supporting a physically unclonable function (PUF), includes receiving a first request for a first security key from a first security device, generating a first final key of a plurality of final keys in response to the first request, and sending the first final key as the first security key to the first security device, wherein the plurality of final keys are based on an intermediate key corresponding to a result of a length extension operation performed on an initial key, and the initial key matches a result of an error correction operation performed on PUF data generated by using the PUF block.

[0009] In general, according to some aspects, a system on chip includes: a processor; a first security device configured to perform encryption and decryption operations on first input / output data of the processor; and an integrated circuit configured to provide a first security key to the first security device by using a physically unclonable function (PUF) block, wherein the integrated circuit is configured to: generate an initial key by sequentially performing a bit decoding operation and a block decoding operation for error correction of PUF data generated by the PUF block, generate an intermediate key by sequentially performing a block encoding operation and a bit encoding operation on the initial key, and generate a first final key among multiple final keys as the first security key based on the intermediate key.

[0010] In general, according to some aspects, a system on a chip includes: a processor; a plurality of security devices; and an integrated circuit including a physically unclonable function (PUF) block, wherein the integrated circuit is configured to: generate an initial key by performing an error correction operation on PUF data generated using the PUF block, generate an intermediate key by performing a length extension operation on the initial key, generate a plurality of security keys based on the intermediate key, and provide the plurality of security keys to the plurality of security devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0012] Figure 1 is a block diagram schematically illustrating an example of an integrated circuit.

[0013] Figure 2 is a flow chart of an example of a method of operating an integrated circuit.

[0014] Figure 3 is a flow chart of an example of a method of operating an integrated circuit.

[0015] Figure 4A is a block diagram illustrating example operation of an integrated circuit in a registration phase, and Figure 4B is a block diagram illustrating example operation of an integrated circuit during a rebuild phase.

[0016] Figure 5A It shows Figure 4B FIGURE 1 shows an example of a scheme of a bit decoding operation of a bit decoder, and Figure 5B It shows Figure 4B FIG. 1 is a diagram of an example of a scheme of a block decoding operation of a block decoder.

[0017] Figure 6A It shows Figure 4B FIGURE 1 shows an example of a block encoding operation scheme of a block encoder, and Figure 6B It shows Figure 4B FIG. 1 is a diagram of an example of a scheme of a bit encoding operation of a bit encoder.

[0018] Figure 7 is a flow chart of an example of a method of operating an integrated circuit.

[0019] Figure 8A and Figure 8B is a diagram illustrating an example of an operating method of a key management circuit.

[0020] Figure 9 is a flow chart of an example of a method of operating an integrated circuit.

[0021] Figure 10A is a block diagram illustrating an example of an integrated circuit, and Figure 10B Is shown using Figure 10A A table diagram of example operations of a one-time programmable (OTP) memory integrated circuit.

[0022] Figure 11 is a flow chart of an example of a method of operating an integrated circuit.

[0023] Figure 12A and Figure 12B is a block diagram illustrating example operation of a key management circuit.

[0024] Figure 13 is a flow chart of an example of a method of operating an integrated circuit.

[0025] Figure 14 is a block diagram illustrating example operation of a key management circuit.

[0026] Figure 15 is a flow chart of an example of a method of operating an integrated circuit.

[0027] Figure 16 is a flow chart of an example of a method of operating an integrated circuit.

[0028] Figure 17 is a diagram illustrating an example of an operating method of a key management circuit.

[0029] Figure 18 is a flow chart of an example of a method of operating an integrated circuit.

[0030] Figure 19 is a diagram illustrating an example of an operating method of a key management circuit.

[0031] Figure 20 is a block diagram schematically illustrating an example of an electronic device. DETAILED DESCRIPTION

[0032] Figure 1 is a block diagram schematically illustrating an example of an integrated circuit 10. Integrated circuit 10 is an integrated circuit for supporting a physically unclonable function (PUF) and may be variously referred to as a PUF integrated circuit, a PUF device, a PUF system, etc. In some embodiments, integrated circuit 10 may be manufactured using a semiconductor process, and the components of integrated circuit 10 may be packaged in a single package or separately in two or more packages. Furthermore, integrated circuit 10 may be mounted on various types of chips (e.g., a system-on-chip) or electronic devices that encrypt and decrypt data or perform security authentication. Integrated circuit 10 may generate a security key in response to a security key request from a security device (e.g., a security circuit or a host (e.g., a processor)) and provide the security key to the security device. As examples, the security circuit may be an encryption circuit or an authentication circuit.

[0033] refer to Figure 1 , the integrated circuit 10 may include a PUF block 20 , a memory 30 and a controller 100 .

[0034] The PUF block 20 may include a PUF cell array 22 comprising a plurality of PUF cells. The PUF cells in the PUF cell array 22 can generate unique signals with unique values ​​based on the PUF. A PUF may provide a unique value corresponding to the hardware based on its inherent characteristics. For example, even when multiple hardware components (such as semiconductor chips) are manufactured using the same process, they may not be physically identical to each other, and slight variations may occur between them. Based on these variations, a unique value of the hardware can be extracted and used in security-critical applications (e.g., secure communications, secure data processing, user identification, firmware updates, etc.). In some embodiments, the PUF cells in the PUF cell array 22 may have any structure that generates k (k is an integer greater than or equal to 2) bits of data with a unique value. For example, the PUF unit may be implemented in at least one of the following structures: a transistor threshold voltage-based PUF structure, a static random access memory (SRAM) type PUF structure based on a value stored in an SRAM cell, an XOR-based PUF structure having intermediate PUF units arranged in parallel, a lightweight PUF structure, a frequency variation-based ring oscillator-based PUF structure, a memory-based PUF structure (e.g., an SRAM-based PUF structure), a latch-based PUF structure, a leakage-based PUF structure based on leakage current, an arbiter-based PUF structure in which a signal path is arbitrarily determined, and a reconfigurable PUF structure that can be reconfigured by a laser beam or thermal variation.

[0035] The memory 30 may be a non-volatile memory, such as a flash memory, a magnetic random access memory (MRAM), a phase change RAM (PRAM), a ferroelectric RAM (FeRAM), or the like.

[0036] In some embodiments, the controller 100 may include a control circuit 110 and a key generator 120. The operations of the control circuit 110 and the key generator 120 included in the controller 100 may also be referred to as the operations of the integrated circuit 10 or the controller 100. The controller 100 may be implemented in hardware or as any processing unit that executes a series of instructions (or software). For example, the controller 100 may be implemented based on a field programmable gate array (FPGA) or an application-specific integrated circuit (ASIC). Furthermore, in some embodiments, the key generator 120 may be integrated with the control circuit 110.

[0037] In some embodiments, in response to a security key request received from an external security device, the control circuit 110 may provide a control signal CS to the PUF block 20 to read the PUF data PUF_DATA required for generating a security key. The control signal CS may include a signal required to output the PUF data PUF_DATA from a valid PUF cell among the plurality of PUF cells in the PUF cell array 22. The control circuit 110 may generate the control signal CS based on a validity map generated during the registration phase of the integrated circuit 10. The validity map may indicate valid PUF cells among the plurality of PUF cells in the PUF cell array 22 that have been verified to repeatedly output the same value. In some embodiments, the PUF data PUF_DATA includes PUF data output from all PUF cells, and the key generator 120 may extract only the PUF data output from the valid PUF cells from the PUF data PUF_DATA based on the validity map and use the extracted PUF data to generate a security key.

[0038] In some embodiments, the key generator 120 may include a key length expansion circuit 121 and a key management circuit 122. First, the key generator 120 may generate an initial key KEY_I by performing an error correction operation on the PUF data PUF_DATA. Specifically, for example, the key generator 120 may perform an error correction operation on the PUF data PUF_DATA based on a specific error correction-related decoding scheme and auxiliary data generated during the registration phase. At the same time, in some embodiments, due to the error correction operation, the number of bits of the initial key KEY_I may be smaller than the number of bits of the PUF data PUF_DATA.

[0039] In some embodiments, the key length extension circuit 121 may generate the intermediate key KEY_IM by performing a length extension operation on the initial key KEY_I. As a specific example, the key generator 120 may perform the length extension operation on the initial key KEY_I based on a specific length extension scheme and auxiliary data generated during the registration phase. In some embodiments, the specific length extension scheme may be associated with a specific error correction decoding scheme used by the key generator 120. For example, the auxiliary data may be stored in the memory 30, and the key generator 120 may read the auxiliary data from the memory 30, perform an error correction operation on the PUF data PUF_DATA, and perform a length extension operation on the initial key KEY_I. Furthermore, because the key length extension circuit 121 generates the intermediate key KEY_IM using the error-corrected initial key KEY_I, and the intermediate key KEY_IM does not contain errors, the intermediate key KEY_IM can be suitable for generating secure keys with guaranteed reliability. In some embodiments, the number of bits of the intermediate key KEY_IM may be the same as or similar to the number of bits of the PUF data PUF_DATA. Specifically, for example, the PUF data PUF_DATA may include 2550 bits, the initial key KEY_I may include 256 bits, and the intermediate key KEY_IM may include 2550 bits.

[0040] In some embodiments, the key management circuit 122 may generate any one of the multiple final keys, KEY_F, as a security key based on the intermediate key KEY_IM. Specifically, for example, the key management circuit 122 may randomly select any one of the multiple final keys that can be generated based on the intermediate key KEY_IM, and generate the selected final key KEY_F as a security key. In some embodiments, the key management circuit 122 may select a final key KEY_F suitable for a security device that has requested a security key from the multiple final keys that can be generated based on the intermediate key KEY_IM, and generate the selected final key KEY_F as a security key. In some embodiments, the key management circuit 122 may determine a security level or security features based on information about an application executed on the security device, and pre-set a method for generating the final key KEY_F or a length of the final key KEY_F before generating the final key KEY_F. In this specification, information about an application may also be referred to as application information.

[0041] The final key KEY_F generated by the key management circuit 122 can be provided to the security device in response to repeated security key requests from the security device. In this case, the final key KEY_F can be defined as being in use by the security device. In some embodiments, the key management circuit 122 can discard the final key KEY_F when it meets a specific invalidation condition. In this case, the final key KEY_F can be defined as being discarded. In some embodiments, the specific invalidation condition can be set based on a situation where the security of the final key KEY_F in use has degraded or is likely to degrade. Specifically, for example, the specific invalidation condition can include detecting that the final key KEY_F has been exposed to the outside world, the controller 100 outputting the final key KEY_F a threshold number of times, or the elapsed threshold time from the time the controller 100 initially output the final key KEY_F. However, these are merely example embodiments and are not limiting. A variety of other conditions can be defined as invalidation conditions. In some embodiments, the key management circuit 122 can generate another final key to replace the discarded final key KEY_F and provide the new final key to the security device.

[0042] In some embodiments, the key management circuit 122 can manage multiple final keys generated from the intermediate key KEY_IM in the in-use state, the discarded state, and the undisclosed state (or the standby state). In some embodiments, the key management circuit 122 can use a one-time programmable (OTP) memory to manage multiple final keys. Using the aforementioned management method, the key management circuit 122 can utilize multiple final keys generated from the intermediate key KEY_IM to adaptively provide highly secure security keys to the security device.

[0043] In some embodiments, when security key requests are received from multiple security devices, the key management circuit 122 may generate, in response to the security key requests, a final key KEY_F corresponding to the number of security key requests received from the multiple security devices, and provide the final key KEY_F to the multiple security devices. In some embodiments, the key management circuit 122 may generate and provide the final key KEY_F applicable to the multiple security devices based on information about applications executed on the multiple security devices.

[0044] The integrated circuit 10 can generate an intermediate key KEY_IM based on the PUF data PUF_DATA and auxiliary data stored during a registration phase, and use the intermediate key KEY_IM to provide any of a plurality of final keys to a security device, or to provide a security key to all of the plurality of security devices. Therefore, the integrated circuit 10 can enhance the security of a chip or electronic device by flexibly generating various security keys tailored to the structure of the chip or electronic device in which the integrated circuit 10 is installed.

[0045] Figure 2 is a flow chart of an example of a method of operating an integrated circuit.

[0046] refer to Figure 2 In operation S100, the integrated circuit may generate PUF data by using the PUF block. In some embodiments, the PUF data may include data output from a valid PUF unit of the PUF block.

[0047] In operation S110, the integrated circuit may perform an error correction operation on the PUF data to generate an initial key. In some embodiments, the integrated circuit may perform the error correction operation on the PUF data step by step. Specifically, for example, the integrated circuit may generate the initial key by sequentially performing a bit decoding operation and a block decoding operation for error correction on the PUF data.

[0048] In operation S120, the integrated circuit may perform a length extension operation on the initial key to generate an intermediate key. In some embodiments, the integrated circuit may perform the length extension operation on the initial key step by step. Specifically, for example, the integrated circuit may generate the intermediate key by sequentially performing a block encoding operation and a bit encoding operation on the initial key. In some embodiments, the scheme of the bit decoding operation of operation S110 may be associated with the scheme of the bit encoding operation of operation S120, and the scheme of the block decoding operation of operation S110 may be associated with the scheme of the block encoding operation of operation S120. In this specification, the scheme of the decoding operation may also be referred to as a decoding scheme.

[0049] In operation S130, the integrated circuit may generate at least one final key from the plurality of final keys based on the intermediate key. In some embodiments, upon receiving a security key request from the security device, the integrated circuit may generate one of the plurality of final keys and provide the generated security key to the security device. In some embodiments, upon receiving security key requests from multiple security devices, the integrated circuit may provide a number of the plurality of final keys corresponding to the number of received security key requests to the multiple security devices as security keys.

[0050] Figure 3 is a flow chart of an example of a method of operating an integrated circuit.

[0051] refer to Figure 3 , in operation S200 , the integrated circuit may generate PUF data by using the PUF block.

[0052] In operation S210, the integrated circuit may generate an initial key from the PUF data based on the auxiliary data and the decoding scheme. In some embodiments, the auxiliary data is data generated during the registration phase of the integrated circuit for error correction of the PUF data and stored in a memory of the integrated circuit, and the auxiliary data may be used for error correction operations on the PUF data. In some embodiments, the decoding scheme may be the basis for error correction operations on the PUF data.

[0053] In operation S220, the integrated circuit may generate an intermediate key from the initial key based on the auxiliary data and the length extension scheme. In some embodiments, the integrated circuit may also use the auxiliary data used in operation S210 in operation S220. In some embodiments, the length extension scheme may be associated with the decoding scheme of operation S210.

[0054] In operation S230 , the integrated circuit may generate at least one final key among a plurality of final keys based on the intermediate key.

[0055] Figure 4A is a block diagram illustrating example operation of the integrated circuit 200 in a registration phase, and Figure 4B 2 is a block diagram illustrating an example operation of the integrated circuit 200 in a reconstruction phase. The integrated circuit 200 includes a key generator 210 and a memory 220, and Figure 4A and Figure 4B A configuration in which the key generator 210 operates at each stage is shown.

[0056] refer to Figure 4A , the integrated circuit 200 may include a key generator 210 and a memory 220 .

[0057] In some embodiments, the key generator 210 may include a bit encoder 211 and a block encoder 212. In the registration phase, the key generator 210 may receive first PUF data PUF_DATA1 from the PUF block. The registration phase may be defined as a phase for determining a valid PUF unit by analyzing output data of a plurality of PUF units of the PUF block, and generating and storing auxiliary data for error correction of the first PUF data PUF_DATA1 output from the PUF block. Figure 4A In the embodiment, the auxiliary data may include first auxiliary data HD_1 and second auxiliary data HD_2.

[0058] In some embodiments, the bit encoder 211 may generate first auxiliary data HD_1 by performing a bit encoding operation on the layer 1-1 key KEY_L11 generated based on the first PUF data PUF_DATA1 and output the layer 2-1 key KEY_L21. In addition, the bit encoder 211 may store the first auxiliary data HD_1 in the memory 220.

[0059] In some embodiments, the block encoder 212 may perform a block encoding operation on the layer 2-1 key KEY_L21 to generate the second auxiliary data HD_2 and output the layer 3-1 key KEY_L31. In addition, the block encoder 212 may store the second auxiliary data HD_2 in the memory 220.

[0060] In some embodiments, the key generator 210 may further include a valid data checker, and the valid data checker may generate a validity map by determining valid PUF units among the plurality of PUF units in the PUF block. The valid data checker may store the validity map in the memory 220.

[0061] Further references Figure 4B , the key generator 210 may include a bit decoder 213, a block decoder 214, a key length expansion circuit 215, and a key management circuit 216. The key length expansion circuit 215 may include a block encoder 215_1 and a bit encoder 215_2. In some embodiments, the key length expansion circuit 215 may include a bit encoder 211 and a block encoder 212 operating in the registration phase. Specifically, the block encoder 215_1 may correspond to Figure 4A The block encoder 212 and the bit encoder 215_2 may correspond to Figure 4A bit encoder 211.

[0062] During the reconstruction phase, the key generator 210 may receive the second PUF data PUF_DATA2 from the PUF block in response to a security key request from a security device. The reconstruction step may be defined as a phase in which the integrated circuit 200 generates a security key in response to a security key request from at least one security device. In other words, the reconstruction phase may be a phase in which the integrated circuit 200 is installed on an electronic device and operates to generate a security key.

[0063] In some embodiments, the memory 220 may store registration information INFO_EM including the first auxiliary data HD_1 and the second auxiliary data HD_2. The key generator 210 may perform an operation for generating a security key by reading the registration information INFO_EM from the memory 220 during the reconstruction phase.

[0064] In some embodiments, the bit decoder 213 may perform a bit decoding operation on the layer-1-2 key KEY_L12 generated from the second PUF data PUF_DATA2 based on the first auxiliary data HD_1 and output the layer-2 key KEY_L22. In some embodiments, the bit decoding operation may be an operation for correcting errors in the layer-1-2 key KEY_L12 bit by bit.

[0065] In some embodiments, the block decoder 214 may perform a block decoding operation on the layer-2 key KEY_L22 based on the second auxiliary data HD_2 and output a layer-3 key KEY_L32. In some embodiments, the block decoding operation may be an operation for correcting errors in the layer-2 key KEY_L22 on a block-by-block basis. The layer-3 key KEY_L32 may correspond to the initial key KEY_I described above.

[0066] In some embodiments, the block encoder 215_1 may perform a block encoding operation on the 3-2 layer key KEY_L32 based on the second auxiliary data HD_2 and generate a 2-2' layer key KEY_L22'. In some embodiments, the number of bits of the 2-2' layer key KEY_L22' may match the number of bits of the 2-2 layer key KEY_L22. In some embodiments, the block encoding scheme and the block decoding scheme may be associated with each other.

[0067] In some embodiments, the bit encoder 215_2 may perform a bit encoding operation on the 2nd layer key KEY_L22' based on the first auxiliary data HD_1 and output the 1st layer key KEY_L12'. In some embodiments, the number of bits in the 1st layer key KEY_L12' may match the number of bits in the 1st layer key KEY_L12. The 1st layer key KEY_L12' may correspond to the intermediate key KEY_IM described above. In some embodiments, the bit encoding scheme and the bit decoding scheme may be associated with each other.

[0068] In some embodiments, the key management circuit 216 may output any one of the final keys KEY_F from the 1-2' layer key KEY_L12' as a security key. The final key KEY_F may be provided to the security device in response to a security key request from the security device.

[0069] In the same manner as above, whenever a security key request is received from the security device, the key generator 210 may generate second PUF data PUF_DATA2 of the PUF block in response to the security key request and generate the final key KEY_F based on the generated second PUF data PUF_DATA2.

[0070] Figure 5A It shows Figure 4B FIG. 2 is a diagram showing an example of a scheme of a bit decoding operation of the bit decoder 213, and Figure 5B It shows Figure 4B FIG is an example of a scheme of block decoding operation of the block decoder 214. Although Figure 5A An embodiment in which the bit decoding operation is performed in units of 5 bits of the 1-2 layer key KEY_L12 is shown, but this is merely an example embodiment to aid understanding, and the bit decoding operation can be performed in units of various bits without being limited thereto. Figure 5B An embodiment in which the layer 2-2 key KEY_L22 includes 255 bits is shown, but this is merely an example embodiment to aid understanding, and the block decoding operation may be performed on the layer 2-2 key KEY_L22 including less than or more than 255 bits.

[0071] refer to Figure 5A , the bit decoder 213 may perform a masking operation based on an XOR operation to mask "00001", which is a part of the 1-2 layer key KEY_L12 and includes two error bits, into "11000", which is the first mask data MD_1. The bit decoder 213 may generate "1", which is the 2-2 layer key KEY_L22, by applying a majority voting scheme to "11001", which is the result of the masking operation. In some embodiments, the first mask data MD_1 may be generated based on the first auxiliary data HD_1, and may be data for masking the 1-2 layer key KEY_L12 so that all bits are "1" (or "0"). Specifically, for example, the most significant bit (e.g., "1") of the first mask data MD_1 may be an even parity bit of the first auxiliary data HD_1, and the remaining bits (e.g., "1000") of the first mask data MD_1 may correspond to bits stored in Figure 4B The first auxiliary data HD_1 in the memory 220 is stored in the memory 220.

[0072] Figure 5A The illustrated embodiments are merely example embodiments, the present disclosure is not limited thereto, and the bit decoder 213 may perform a bit decoding operation based on more various schemes.

[0073] refer to Figure 5B, the block decoder 214 may divide the layer 2 key KEY_L22 into 131 more significant bits and 124 less significant bits, and may perform an XOR operation on the less significant bits and the 124-bit second auxiliary data HD_2. The block decoder 214 may generate the 124-bit layer 3 key KEY_L32 by performing a block decoding operation based on the result of the XOR operation and the more significant bits via a decoding circuit DEC. In some embodiments, the decoding circuit (DEC) may perform the block decoding operation according to a block code-based error correction decoding scheme. Specifically, for example, the decoding circuit DEC may correspond to a Bose-Chaudhuri-Hocquenghem (BCH) decoding circuit, and the length of the more significant bits input to the decoding circuit DEC may correspond to the length of the BCH code.

[0074] The key generator 210 may be configured as described above. Figure 5A and Figure 5B The bit decoding operation and the block decoding operation are performed in a manner to correct errors in the 1-2 layer key KEY_L12 and generate an error-free 3-2 layer key KEY_L32 as the initial key KEY_I.

[0075] at the same time, Figure 5A and Figure 5B The decoding scheme of KEY_I is only an example embodiment, and the key generator 210 may generate the initial key KEY_I based on various decoding schemes without being limited thereto.

[0076] Figure 6A It shows Figure 4B FIG. 2 is a diagram showing an example of a block encoding operation scheme of the block encoder 215_1, and Figure 6B It shows Figure 4B FIG is an example of a scheme of the bit encoding operation of the bit encoder 215_2. Assume that the following reference Figure 6A The block coding operation scheme described above is the same as that of Figure 5B The block decoding operation described is associated with and referenced below. Figure 6B The scheme of the bit encoding operation described above is the same as that of Figure 5A However, Figure 6A and Figure 6B The illustrated embodiments are merely example embodiments, and the present disclosure is not limited thereto. Figure 6A and Figure 6B The encoding scheme can be based on Figure 5A and Figure 5B The decoding scheme varies.

[0077] refer to Figure 6AThe block encoder 215_1 may perform a block encoding operation using the encoding circuit ENC based on the 131-bit 3-2 layer key KEY_L32 serving as the initial key KEY_I, and perform an XOR operation on the 124-bit result of the block encoding operation and the 124-bit second auxiliary data HD_2. The block encoder 215_1 may combine the 3-2 layer key KEY_L32 with the result of the XOR operation to generate a 2-2' layer key KEY_L22'. For example, the more significant bits of the 2-2' layer key KEY_L22' may correspond to the 3-2 layer key KEY_L32, and the less significant bits of the 2-2' layer key KEY_L22' may correspond to the result of the XOR operation.

[0078] Further references Figure 6B , the bit encoder 215_2 may generate a 2-2' layer key KEY_L22' including 5 bits (i.e., '11111') by applying a repetition scheme to '1' (which corresponds to a portion of the 2-2' layer key KEY_L22'). Thereafter, the bit encoder 215_2 may perform a masking operation based on an XOR operation of '11111' and '11000', where '11000' is the first mask data MD_1. As a result of the masking operation, '00111' may correspond to a portion of the 1-2' layer key KEY_L12' as the intermediate key KEY_IM. Meanwhile, '00111' of the 1-2' layer key KEY_L12' may be obtained by correcting the bit data including Figure 5A In this regard, the 1-2' layer key KEY_L12' as the intermediate key KEY_IM does not include an error and can generate a highly reliable security key.

[0079] Figure 7 is a flow chart of an example of a method of operating an integrated circuit.

[0080] refer to Figure 7 In operation S300, the integrated circuit 300 may receive a security key request from the security device 40. In some embodiments, the security device 40 may be a security circuit or a processor. In this specification, the security circuit may correspond to an encryption engine, and the encryption engine may be implemented as hardware, software, or a combination of hardware and software.

[0081] In operation S310, the integrated circuit 300 may initiate generation of a security key to be provided to the security device 40 by referring to the management table in response to the request. In some embodiments, the management table may include information for managing a plurality of final keys that can be provided as security keys in an in-use state, a discarded state, and an undisclosed state. In addition, in some embodiments, information included in the management table may be used when generating a first final key in the in-use state.

[0082] In operation S320, the integrated circuit 300 may generate a first final key among a plurality of final keys. In some embodiments, the integrated circuit 300 may sequentially generate an initial key and an intermediate key based on PUF data generated by using the PUF block, and generate a first final key among the final keys that can be generated based on the intermediate key by referring to the management table of operation S310.

[0083] In operation S330 , the integrated circuit 300 may transmit the first final key as a security key to the security device 40 .

[0084] In operation S340, the integrated circuit 300 may monitor the validity of the first final key currently in use by the security device 40 and determine whether to discard the first final key. In some embodiments, the integrated circuit 300 may periodically or aperiodically monitor whether the first final key satisfies a specific invalidation condition. When the first final key satisfies the specific invalidation condition, the integrated circuit 300 may determine to discard the first final key. In some embodiments, the integrated circuit 300 may randomly determine whether to discard the first final key, regardless of the specific invalidation condition. Specifically, the integrated circuit 300 may generate a random number associated with discarding and determine to discard the first final key when the random number has a specific value.

[0085] In operation S350, the integrated circuit 300 may update the management table based on the determination result of operation S340. In some embodiments, the integrated circuit 300 may update the management table to prevent the first final key from being generated, thereby preventing the first final key in the discarded state from being used as a security key in the future. Furthermore, in some embodiments, the integrated circuit 300 may update the management table to switch the second final key (instead of the first final key) from the undisclosed state to the in-use state, among the multiple final keys to be provided to the security device 40.

[0086] In operation S360 , the integrated circuit 300 may receive a security key request from the security device 40 .

[0087] In operation S370, the integrated circuit 300 may generate a second final key among the plurality of final keys. In some embodiments, the integrated circuit 300 may sequentially generate an initial key and an intermediate key based on the PUF data generated by using the PUF block, and generate the second final key among the final keys that can be generated based on the intermediate key by referring to the updated management table of operation S350.

[0088] In operation S380 , the integrated circuit 300 may transmit the second final key as a security key to the security device 40 .

[0089] In this regard, the integrated circuit 300 can selectively provide any one of a plurality of final keys to the security device 40 by using the auxiliary data generated in one registration phase, thereby enhancing the security performance of the security device 40. In addition, the integrated circuit 300 can change the security key provided to the security device 40 by managing the table without requiring separate logic, thereby further enhancing the security of the security device 40 at a low cost.

[0090] Figure 8A and Figure 8B 3 is a diagram showing an example of a method of operating the key management circuit 310. Figure 8A and Figure 8B In the embodiment, it is assumed that six final keys, ie, the first final key KEY_F#0 to the sixth final key KEY_F#5, can be generated according to the intermediate key. However, this is for convenience of explanation, and the present disclosure is not limited thereto.

[0091] refer to Figure 8A The key management circuit 310 can manage the first to sixth final keys KEY_F#0 to KEY_F#5 that can be generated based on the intermediate key. The key management circuit 310 can manage the first final key KEY_F#0 in use and, upon receiving a security key request from the security device, generate the first final key KEY_F#0 based on the intermediate key in response to the security key request and provide the first final key KEY_F#0 to the security device.

[0092] In some embodiments, the key management circuit 310 can manage the second to sixth final keys KEY_F#1 to KEY_F#5 in an undisclosed state, so that the second to sixth final keys KEY_F#1 to KEY_F#5 can be provided at any time in response to a second key request from a security device or other security device.

[0093] Furthermore, in some embodiments, the key management circuit 310 may index and manage the second to sixth final keys KEY_F#1 to KEY_F#5 for future use.

[0094] Further references Figure 8B , the key management circuit 310 may discard the first final key KEY_F#0. In some embodiments, when the number of times the first final key KEY_F#0 is output to the security device reaches a threshold number of times, the key management circuit 310 may discard the first final key KEY_F#0. In some embodiments, when a threshold time has passed since the time point when the first final key KEY_F#0 was first output to the security device, the key management circuit 310 may discard the first final key KEY_F#0. In some embodiments, when it is detected that the first final key KEY_F#0 is exposed to the outside or a signal indicating that the first final key KEY_F#0 is exposed is received from the security device, the key management circuit 310 may discard the first final key KEY_F#0. In some embodiments, the key management circuit 310 may randomly discard the first final key KEY_F#0.

[0095] The key management circuit 310 can manage the state of the first final key KEY_F#0 to switch it to a discarded state. The key management circuit 310 can manage the state of the second final key KEY_F#1 to switch it to an in-use state. When a security key request is received from the security device, the key management circuit 310 can generate the second final key KEY_F#1 based on the intermediate key in response to the second key request and provide the second final key KEY_F#1 to the security device.

[0096] In some embodiments, the key management circuit 310 may manage the first to sixth final keys KEY_F#0 to KEY_F#5 based on a management table, and the management table may be stored in a memory or an OTP memory included in the integrated circuit.

[0097] Figure 9 is a flow chart of an example of a method of operating an integrated circuit.

[0098] refer to Figure 9 In operation S400, the integrated circuit may determine whether the first final key satisfies an invalidation condition. In some embodiments, the first final key is in use and may be provided to the security device as a security key in response to a security key request from the security device.

[0099] If the result of the determination in operation S400 is "yes," the method proceeds to operation S410, where, upon receiving a security key request from the security device, the integrated circuit may transmit a second final key from the plurality of final keys to the security device as the security key. Furthermore, in operation S410, the integrated circuit may discard the first final key. When discarding the first final key, it may be predetermined that the second final key is used in place of the first final key.

[0100] When the determination result in operation S400 is “No”, the method proceeds to operation S420 , where, when a security key request is received from the security device, the integrated circuit may transmit the first final key as a security key to the security device.

[0101] Figure 10A is a block diagram illustrating an example of an integrated circuit 300, and Figure 10B Is shown using Figure 10A FIG. 1 is a table diagram of an example operation of the OTP memory 320 of the integrated circuit 300 . Figure 10A and Figure 10B It is assumed that Figure 8A and Figure 8B However, this is merely an example embodiment to help understanding, and the present disclosure is not limited thereto.

[0102] refer to Figure 10A , the integrated circuit 300 may include a key management circuit 310 and an OTP memory 320. In some embodiments, the OTP memory 320 may be implemented as embedded in the key management circuit 310.

[0103] In some embodiments, the OTP memory 320 may include an OTP array 322 in which OTP data OTP_D indicating the final key in use is stored. The OTP array 322 may store first digit #0 to fifth digit #4, and the OTP data OTP_D may include first digit #0 to fifth digit #4.

[0104] In some embodiments, the key management circuit 310 may provide a program control signal P_CS to the OTP memory 320 to discard the final key currently in use and generate another final key as a security key.

[0105] In some embodiments, the OTP memory 320 may perform a program operation based on the program control signal P_CS so that a value of at least one of the first to fifth bits # 0 to # 4 of the OTP array 322 is changed.

[0106] refer to Figure 10BAccording to the management table TB, when the values ​​of the first to fifth bits #0 and #4 are "00000," the key management circuit 310 may output the first final key KEY_F#0 as a security key. When the values ​​of the first to fifth bits #0 and #4 are "00001," the key management circuit 310 may output the second final key KEY_F#1 as a security key, and due to the characteristics of the OTP memory 320, the first final key KEY_F#0 may be discarded. When the values ​​of the first to fifth bits #0 and #4 are "00011," the key management circuit 310 may output the third final key KEY_F#2 as a security key, and due to the characteristics of the OTP memory 320, the second final key KEY_F#1 may be discarded. When the values ​​of the first to fifth bits #0 and #4 are "00111," the key management circuit 310 may output the fourth final key KEY_F#3 as a security key, and due to the characteristics of the OTP memory 320, the third final key KEY_F#2 may be discarded. When the values ​​of the first to fifth bits #0 to #4 are "01111," the key management circuit 310 may output the fifth final key KEY_F#4 as a security key, and the fourth final key KEY_F#3 may be discarded due to the characteristics of the OTP memory 320. Furthermore, when the values ​​of the first to fifth bits #0 to #4 are "11111," the key management circuit 310 may output the sixth final key KEY_F#5 as a security key, and the fifth final key KEY_F#4 may be discarded due to the characteristics of the OTP memory 320.

[0107] In some embodiments, the key management circuit 310 may generate a program control signal P_CS based on the management table TB to sequentially program one bit at a time to manage the first to sixth final keys KEY_F# 0 to KEY_F# 5 .

[0108] In some embodiments, the key management circuit 310 may generate a signal for generating a final key indicated by the OTP data OTP_D based on the OTP data OTP_D received from the OTP memory 320. The key management circuit 310 may generate the final key indicated by the OTP data OTP_D based on the generated signal.

[0109] Figure 11 is a flow chart of an example of a method of operating an integrated circuit. Figure 11 The specific method of generating and outputting the first final key currently being used by the security device according to the intermediate key by the integrated circuit is shown.

[0110] refer to Figure 11In operation S500 , the integrated circuit generates a plurality of sub-intermediate keys by dividing the intermediate key into N (here, N is an integer greater than or equal to 2) bit units in response to a security key request from the security device.

[0111] In operation S510, the integrated circuit may generate a first final key from a plurality of final keys that may be generated from the intermediate key based on a plurality of sub-intermediate keys and a selection signal. In some embodiments, the selection signal may be a signal for selecting M (where M is an integer less than or equal to N) bits from each of the plurality of sub-intermediate keys. In some embodiments, the integrated circuit may generate the first final key by combining the results of an XOR operation between the M bits selected from each of the plurality of sub-intermediate keys.

[0112] In operation S520 , the integrated circuit may output the first final key generated in operation S510 to the security device.

[0113] Figure 12A and Figure 12B is a block diagram illustrating example operation of key management circuit 410 .

[0114] refer to Figure 12A The key management circuit 410 may include a plurality of first multiplexers MUX1, a plurality of XOR circuits XOR, and a key selection circuit 411. The key management circuit 410 may divide the intermediate key KEY_IM into N-bit units, thereby generating a plurality of sub-intermediate keys KEY_IM_SUB, each of which includes N bits. The key selection circuit 411 may generate and output a first selection signal SEL_S1 based on OTP data OTP_DATA received from an OTP memory. The first selection signal SEL_S1 is a signal for generating a first final key KEY_F#0 indicated by the OTP data OTP_DATA and may be input to the plurality of first multiplexers MUX1. The plurality of first multiplexers MUX1 may select and output M bits for each of the plurality of sub-intermediate keys KEY_IM_SUB based on the first selection signal SEL_S1. The plurality of XOR circuits XOR may perform an XOR operation on the received M bits and output the XOR operation results, and combine the XOR operation results to generate the first final key KEY_F#0.

[0115] In some embodiments, the values ​​of N and M may vary. In some embodiments, the key management circuit 410 may control the number of final keys that can be generated based on the intermediate key KEY_IM by adjusting the values ​​of N and M. Furthermore, in some embodiments, the key management circuit 410 may adjust the values ​​of N and M to match the characteristics of the security device requesting the security key, thereby generating a first final key KEY_F#0 suitable for the security device as a security key.

[0116] Further references Figure 12B ,and Figure 12A Differently, the key selection circuit 411 may include an OTP memory 411_1 and generate a first selection signal SEL_S1 based on OTP data stored in the OTP memory 411_1 .

[0117] at the same time, Figure 12A and Figure 12B The example embodiment in which the key management circuit 410 generates the first final key KEY_F#0 according to the intermediate key KEY_IM is shown. However, the present disclosure is not limited thereto, and the key management circuit 410 may be implemented in various ways to generate the first final key KEY_F#0 in various ways.

[0118] Figure 13 is a flow chart of an example of a method of operating an integrated circuit.

[0119] refer to Figure 13 In operation S600, the integrated circuit may obtain application information corresponding to the security device requesting the security key. In some embodiments, the security device may perform security operations using security keys based on specific applications, and some security devices may perform security operations based on different applications. The integrated circuit may obtain application information corresponding to the security device from the security device, or, during an initial setup phase, the integrated circuit may collect application information corresponding to multiple security devices to which the integrated circuit will provide security keys. In some embodiments, the application information may include the security level or security characteristics of the application.

[0120] In operation S610, the integrated circuit may set the Figure 12A and Figure 12B At least one of the N value as the division unit and the M value as the selection unit described in [ 0015 ] is provided. In some embodiments, the integrated circuit may set a value of at least one of N and M reflecting the obtained application to generate a security key suitable for the obtained application information, and provide the security key to the security device.

[0121] In operation S620 , the integrated circuit may generate a first selection signal for generating a final key based on the setting result of operation S610 and the OTP data.

[0122] Figure 14 is a block diagram illustrating example operations of the key management circuit 410. Figure 14 In the description, the focus is on Figure 12A The differences from the embodiment shown in FIG. 1 are omitted, and the same description as above is omitted.

[0123] refer to Figure 14 , the key management circuit 410 may include a plurality of first multiplexers MUX1 , a plurality of XOR circuits XOR, a key selection circuit 411 and a second multiplexer MUX2 .

[0124] In some embodiments, the key selection circuit 411 may generate a first length control signal L_CS1 for adjusting the length of the first final key KEY_F#0' and provide the first final key KEY_F#0' to the second multiplexer MUX2. In some embodiments, the key selection circuit 411 may generate the first length control signal L_CS1 to generate a first final key KEY_F#0' having a security key length that meets the security device requirements or is suitable for an application executed on the security device.

[0125] In some embodiments, the second multiplexer MUX2 may output at least one of the XOR operation results received from the plurality of XOR circuits XOR based on the first length control signal L_CS1 and generate the first final key KEY_F#0′.

[0126] Figure 15 is a flow chart of an example of a method of operating an integrated circuit.

[0127] refer to Figure 15 , in operation S700, the integrated circuit may obtain application information corresponding to the security device requesting the security key.

[0128] In operation S710 , the integrated circuit may determine a length of a final key provided to the security device as a security key based on the application information obtained in operation S700 .

[0129] In operation S720 , the integrated circuit may generate a first length control signal based on the length determined in operation S710 .

[0130] Figure 16 is a flow chart of an example of a method of operating an integrated circuit.

[0131] refer to Figure 16In operation S800 , the integrated circuit may receive security key requests from K security devices (where K is an integer greater than or equal to 2). In some embodiments, when a security key is needed, the K security devices may each send a security key request to the integrated circuit.

[0132] In operation S810, the integrated circuit may generate K final keys from the plurality of final keys in response to the security key request. In some embodiments, the K final keys may be different from one another. In other words, the integrated circuit may reuse auxiliary data generated during a registration phase to generate an intermediate key and generate the K final keys based on the intermediate key, thereby efficiently providing security keys to the K security devices. In some embodiments, the K final keys may be customized to suit the security operations of the K security devices.

[0133] In operation S820, the integrated circuit may send the K final keys generated in operation S810 to the K security devices. In some embodiments, each time a security key request is received, the integrated circuit may generate any final key that can be generated based on the intermediate key and provide the generated final key to the security device that sent the security key request.

[0134] Since the integrated circuit can generate an intermediate key by using one PUF block and generate various final keys based on the intermediate key, the integrated circuit can effectively provide security keys to multiple security devices at low cost and small design area.

[0135] Figure 17 is a diagram showing an example of a method of operating the key management circuit 510. Figure 17 In the embodiment, it is assumed that six final keys can be generated based on the intermediate keys. However, this is for the convenience of explanation and the present disclosure is not limited thereto.

[0136] refer to Figure 17The key management circuit 510 can manage the first to sixth final keys KEY_F#0 to KEY_F#5, which can be generated based on the intermediate key. The key management circuit 510 can manage the first final key KEY_F#0 while it is currently in use by the first security device 50 (in-use state). Upon receiving a security key request from the first security device 50, the key management circuit 510 can generate the first final key KEY_F#0 based on the intermediate key in response to the security key request and provide the first final key KEY_F#0 to the first security device 50. Furthermore, the key management circuit 510 can manage the second final key KEY_F#1 while it is currently in use by the second security device 60 (in-use state). Upon receiving a security key request from the second security device 60, the key management circuit 510 can generate the second final key KEY_F#1 based on the intermediate key in response to the security key request and provide the second final key KEY_F#1 to the second security device 60.

[0137] In some embodiments, the generation method of the first final key KEY_F#0 and the second final key KEY_F#1 (for example, Figure 12A The values ​​of N and M) and lengths can be the same.

[0138] In some embodiments, the generation method of the first final key KEY_F#0 and the second final key KEY_F#1 (for example, Figure 12A At least one of the values ​​of N and M) and the length of the first final key KEY_F#0 may be different. In other words, at least one of the generation method and length of the first final key KEY_F#0 may be determined based on the application information about the first security device 50, and at least one of the generation method and length of the second final key KEY_F#1 may be determined based on the application information about the second security device 60.

[0139] Figure 18 is a flow chart of an example of a method of operating an integrated circuit.

[0140] refer to Figure 18 , in operation S900 , the integrated circuit may receive a security key request from a first security device.

[0141] In operation S910, the integrated circuit may select a first final key set corresponding to a first security device from a plurality of final key sets in response to a security key request. In some embodiments, the final key set may be defined as including a first security device that can be based on Figure 12A The final key set is generated based on the intermediate key according to the setting of the N and M values. In other words, Figure 12A Specifically, for example, in order to generate a security key to be provided to the first security device, the integrated circuit may Figure 12A The values ​​of N and M are set to 4 and 3 respectively, so the final key pool to be provided to the first security device may be the first final key set. In this specification, selecting the first final key set may include setting Figure 12A The values ​​of N and M.

[0142] In operation S920 , the integrated circuit may generate a first final key in the first final key set selected in operation S910 .

[0143] In operation S930 , the integrated circuit may transmit the first final key generated in operation S920 to the first security device as a security key.

[0144] Figure 19 is a diagram showing an example of a method of operating the key management circuit 510. Figure 19 , it is assumed that six final keys KEY_F#00 to KEY_F#50 are included in the first final key set SET1, and four final keys KEY_F#01 to KEY_F#31 are included in the second final key set SET2. However, this is for convenience of explanation, and the present disclosure is not limited thereto.

[0145] refer to Figure 19 In response to the security key request of the first security device 50, the key management circuit 510 may generate the 3rd-0th final key KEY_F#20 among the 1st-0th final key KEY_F#00 to the 6th-0th final key KEY_F#50 included in the first final key set SET1, and provide the 3rd-0th final key KEY_F#20 to the first security device 50 as a security key. In some embodiments, the key management circuit 510 may generate the 3rd-0th final key KEY_F#20 based on the first application information setting corresponding to the first security device 50. Figure 12A and Figure 12B The final key pool to be provided to the first security device 50 as a security key is selected as the first final key set SET1 based on the values ​​of N and M in . At the same time, the key management circuit 510 can discard the 1-0th final key KEY_F#00 and the 2-0th final key KEY_F#10 in the first final key set SET1, as described above.

[0146] In response to the security key request of the second security device 60, the key management circuit 510 may generate the 2-1st final key KEY_F#21 among the 1-1st final key KEY_F#01 to the 4-1st final key KEY_F#31 included in the second final key set SET2, and provide the 2-1st final key KEY_F#21 to the second security device 60 as a security key. In some embodiments, the key management circuit 510 may generate the 2-1st final key KEY_F#21 based on the second application information setting corresponding to the second security device 60. Figure 12A and Figure 12B The final key pool to be provided to the second security device 60 as a security key is selected as the second final key set SET2 based on the values ​​of N and M in . At the same time, the key management circuit 510 can discard the 1-1th final key KEY_F#01 in the second final key set SET2, as described above.

[0147] The key management circuit 510 may generate security keys by changing a final key pool according to an application executed on each of the first security device 50 and the second security device 60 .

[0148] Figure 20 is a block diagram schematically illustrating an example of an electronic device 1000. In some embodiments, the electronic device 1000 may be one of various types of electronic devices for performing data encryption or security authentication, such as an application processor, a smart card, a mobile device, a data storage medium (e.g., a solid-state drive (SSD), a memory stick, a universal flash storage (UFS) device, etc.), a memory card, etc.

[0149] refer to Figure 20 , the electronic device 1000 may include at least one processor 1100, an integrated circuit 1200 supporting PUF, at least one security circuit 1300, a non-volatile memory (NVM) controller 1400, a RAM 1500, and a host interface 1600. The at least one processor 1100 and the at least one security circuit 1300 may correspond to the above-mentioned security device and may be configured according to Figures 1 to 19 The illustrated embodiment receives the security key from the integrated circuit 1200 .

[0150] The processor 1100 can control the overall operation of the electronic device 1000. The processor 1100 can be implemented as a central processing unit (CPU), a microprocessor, etc., and can include a single processor core or multiple processor cores. At the same time, the electronic device 1000 may also include a neural network processing unit (NPU) or a graphics processing unit (GPU).

[0151] The RAM 1500 may operate as a working memory of the internal system of the electronic device 1000. The RAM 1500 may include at least one of a volatile memory and a non-volatile memory. Code and / or applications for managing / operating the electronic device 1000 may be loaded into the RAM 1500, and the processor 1100 may execute the code and / or applications loaded into the RAM 1500. In this case, the code and / or applications may be stored in the NVM 1410 or a separate memory.

[0152] The host interface 1600 can be connected to an input / output device through an RGB interface, a CPU interface, a serial interface, a mobile display digital interface (MDDI), an inter-integrated circuit (I2C) interface, a serial peripheral interface (SPI), a microcontroller unit (MCU) interface, a mobile industry processor interface (MIPI), an embedded display port (eDP) interface, a D-subminiature (D-sub) interface, an optical interface, a high-definition multimedia interface (HDMI), a mobile high-definition link (MHL) interface, a secure digital (SD) card / multimedia card (MMC) interface, or an infrared data association (IrDA) interface.

[0153] The NVM controller 1400 may provide an interface between the NVM 1410 and other components of the electronic device 1000 (e.g., the processor 1100, the integrated circuit 1200, the security circuit 1300, etc.). Under the control of the NVM controller 1400, the NVM 1410 may receive data to be stored in the NVM 1410 or read data to be read from the NVM 1410.

[0154] The NVM 1410 may include one of a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (ERPOM), an electrically erasable programmable ROM (EEPROM), a flash memory, a phase-change random access memory (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), and a ferroelectric RAM (FeRAM). Code and / or applications for managing / operating the electronic device 1000 may be stored in the NVM 1410, and user data may also be stored in the NVM 1410.

[0155] The processor 1100 , the security circuit 1300 , and the NVM controller 1400 may perform encryption and decryption operations on input / output data using a security key provided from the integrated circuit 1200 .

[0156] Integrated circuit 1200 may generate an intermediate key by sequentially performing an error correction operation and a length extension operation on an initial key, and provide at least one of a plurality of final keys that may be generated based on the intermediate key to at least one of processor 1100, security circuit 1300, and NVM controller 1400. Integrated circuit 1200 may generate final keys applicable to processor 1100, security circuit 1300, and NVM controller 1400, respectively, based on corresponding applications executed on processor 1100, security circuit 1300, and NVM controller 1400, and provide the generated final keys as security keys.

[0157] refer to Figures 1 to 19 The configuration and operating method of the described integrated circuit can be applied to the PUF-enabled integrated circuit 1200. The integrated circuit 1200 can be implemented in hardware, a combination of hardware and software, or a combination of hardware and firmware.

[0158] Although this specification contains many specific implementation details, these details should not be interpreted as limitations on the scope of what can be claimed or on the scope of any invention, but rather as descriptions of features that can be applied to a particular embodiment of a particular invention. In a single embodiment, certain features described in this specification in the context of separate embodiments can also be implemented in combination. Conversely, different features described in the context of a single embodiment can also be implemented in multiple embodiments individually, or in appropriate sub-combinations. In addition, although features may be described above as working in certain combinations, one or more features from a combination may be deleted from the combination in some cases, and a combination may be directed to a sub-combination or a variation of a sub-combination.

[0159] While the present disclosure has been shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.

Claims

1. An integrated circuit configured to support a physically unclonable function (PUF), the integrated circuit comprising: A PUF block, including a PUF cell array; as well as a controller configured to generate a security key based on PUF data, the PUF data being generated based on the PUF block, Wherein, the controller is configured as follows: performing an error correction operation on the PUF data to generate an initial key, performing a length extension operation on the initial key to generate an intermediate key, and At least one final key among a plurality of final keys is generated as the security key according to the intermediate key.

2. The integrated circuit according to claim 1, wherein: The error correction operation on the PUF data is based on auxiliary data and a decoding scheme, the auxiliary data being generated during the enrollment phase, and The length extension operation on the initial key is based on the auxiliary data and a length extension scheme.

3. The integrated circuit according to claim 2, wherein: The decoding scheme is associated with the length extension scheme.

4. The integrated circuit according to claim 1, wherein: The error correction operation on the PUF data includes: a bit decoding operation that masks the PUF data based on the first auxiliary data and applies a majority voting scheme to the masked result; and A block decoding operation performs an XOR operation on a portion of the result of the bit decoding operation and the second auxiliary data, and applies a Bose-Chaudhuri-Hocquenghem (BCH) decoding scheme to a remaining portion of the result of the bit decoding operation.

5. The integrated circuit according to claim 4, wherein: The length extension operation on the initial key includes: a block encoding operation of applying a BCH encoding scheme to the initial key, performing an XOR operation on a result of applying the BCH encoding scheme and the second auxiliary data, and combining the initial key with a result of the XOR operation; and A bit encoding operation applies a repetition scheme to a result of the block encoding operation and masks the result of applying the repetition scheme based on the first auxiliary data.

6. The integrated circuit according to claim 1, wherein: The PUF data includes data output from a plurality of valid PUF cells in the PUF cell array.

7. The integrated circuit according to claim 1, wherein: The number of bits of the intermediate key matches the number of bits of the PUF data.

8. The integrated circuit according to claim 1, wherein: The at least one final key of the plurality of final keys comprises a first final key to be provided to a first security device, and The controller is configured to manage the switching of the first final key from an in-use state to a discarded state based on the first final key satisfying a specific invalidation condition.

9. The integrated circuit according to claim 8, wherein: The integrated circuit includes a one-time programmable (OTP) memory configured to store data for generating the at least one final key of the plurality of final keys, and The controller is configured to perform a programming operation on the OTP memory so that the first final key in the discarded state is not generated.

10. The integrated circuit according to claim 8, wherein: The plurality of final keys include a second final key, and Wherein, the controller is configured as follows: generating the second final key to replace the first final key in the discarded state, and The second final key is provided to the first security device.

11. The integrated circuit according to claim 1, wherein: The at least one final key of the plurality of final keys comprises a first final key, and Wherein, the controller is configured as follows: Dividing the intermediate key into a plurality of N-bit units to generate a plurality of sub-intermediate keys, where N is an integer greater than or equal to 2; and The first final key is generated based on combining results of XOR operations between M bits in each sub intermediate key selected from the plurality of sub intermediate keys, where M is an integer less than or equal to N.

12. The integrated circuit according to claim 11, wherein: The controller is configured to set at least one of an N value and an M value based on application information corresponding to a security device that receives the first final key.

13. The integrated circuit according to claim 11, wherein: The controller is configured to adjust a length of the first final key based on selectively combining some of the XOR operation results.

14. The integrated circuit of claim 1, wherein: The at least one final key of the plurality of final keys includes a first final key to be provided to a first security device and a second final key to be provided to a second security device.

15. The integrated circuit of claim 14, wherein: The number of bits of the first final key is different from the number of bits of the second final key.

16. The integrated circuit of claim 14, wherein: The controller is configured to: performing a first setting operation based on first application information corresponding to the first security device to generate the first final key, and A second setting operation is performed based on second application information corresponding to the second security device, thereby generating the second final key.

17. A method of operating an integrated circuit comprising a Physical Unclonable Function (PUF) block, the method comprising: receiving a first request for a first security key from a first security device; generating a first final key of a plurality of final keys based on the first request; as well as sending the first final key as the first security key to the first security device, wherein the multiple final keys are based on intermediate keys corresponding to the result of performing a length extension operation on the initial key, and The initial key matches a result of an error correction operation performed on PUF data generated based on the PUF block.

18. The method according to claim 17, comprising: changing the first security key from the first final key to a second final key among the plurality of final keys; receiving a second request for the first security key from the first security device; generating the second final key based on the second request; as well as The second final key is sent to the first security device as the first security key.

19. A system on a chip, comprising: processor; a first security device configured to perform encryption and decryption operations on first input / output data of the processor; as well as an integrated circuit configured to provide a first security key to the first security device based on a Physical Unclonable Function (PUF) block, Wherein, the integrated circuit is configured as: generating an initial key based on sequentially performing a bit decoding operation and a block decoding operation for error correction of PUF data generated by the PUF block, generating an intermediate key based on sequentially performing a block encoding operation and a bit encoding operation on the initial key, and A first final key among a plurality of final keys is generated according to the intermediate key as the first security key.

20. The system on chip according to claim 19, comprising: a memory controller configured to control a memory operation of second input / output data of the processor; as well as a second security device configured to perform encryption and decryption operations on the second input / output data; Wherein, the integrated circuit is configured as: generating a second final key among the plurality of final keys as a second security key, and The second security key is provided to the second security device.

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