A memory and an operating method of the memory

Abstract

The application discloses a memory and an operating method of the memory. The memory comprises a storage array and a peripheral circuit. The peripheral circuit comprises a plurality of gating switch units and a plurality of discharging switch units. Each gating switch unit comprises a first end and a second end. The first end is connected with a bit line end of any storage cell structure. The gating switch unit is configured to control an operating state of the storage cell structure. Each discharging switch unit is connected with the second end of any gating switch unit. The discharging switch unit is configured to provide a direct current signal to the second end of the gating switch unit connected with a selected storage cell structure during a discharging operation. Through the technical features, the influence of bit line leakage and capacitance sensitivity on a reading process of the storage cell structure can be reduced, the reliability of the reading process is improved, and thus the actual reading voltage corresponding to the storage cell structure is closer to an intrinsic reading voltage.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of phase change memory, in particular to a memory and an operation method of the memory. BACKGROUND

[0002] PCM (Phase Change Memory) is a kind of non-volatile memory, which represents data state through resistance difference of phase change material. In the process of reading data, the storage state of the cell is usually determined by charge sharing between BL (bit line) and DL (data line).

[0003] In the related art, the reading of the cell is easily affected by BL leakage current, BL corresponding parasitic capacitance and other factors, thereby leading to inaccurate reading state of the cell. SUMMARY

[0004] In view of the above defects of the prior art, the technical problem to be solved by the present application is how to improve the reliability of the reading process of the cell.

[0005] In order to solve at least one of the above technical problems, the present application discloses a memory and an operation method of the memory.

[0006] According to an aspect of the present application, a memory is provided, the memory comprising a storage array and a peripheral circuit, the storage array comprising a plurality of cell structures, and the peripheral circuit being electrically connected to the cell structures, the peripheral circuit comprising:

[0007] a plurality of gating switch units, each gating switch unit comprising a first end and a second end, the first end being connected to a bit line end of any cell structure, and the gating switch unit being configured to control an operating state of the cell structure;

[0008] a plurality of discharge switch units, each discharge switch unit being connected to the second end of any gating switch unit, and the discharge switch unit being configured to provide a direct current signal to the second end of the selected gating switch unit connected to the selected cell structure during a discharge operation.

[0009] Optionally, the discharge switch unit comprises:

[0010] a voltage switch, one end of which is connected to the second end of the gating switch unit, and the other end of which is connected to a negative voltage signal, and the voltage switch being configured to conduct to provide a reset voltage signal to the second end of the gating switch unit during the discharge operation of the selected cell structure.

[0011] A current switch, having one end connected to the second end of the gating switch unit and the other end connected to the negative voltage signal, the current switch being configured to be turned on to provide a direct current signal to the second end of the gating switch unit during the discharging operation on the selected memory cell structure.

[0012] Optionally, the gating switch unit comprises:

[0013] A first bit line switch, having a third end and a fourth end, the third end being connected to the bit line end of the memory cell structure, and the fourth end being connected to the local bit line of the memory array;

[0014] A second bit line switch, having a fifth end and a sixth end, the fifth end being connected to the fourth end of the first bit line switch, and the sixth end being connected to the discharging switch unit;

[0015] The gating switch unit is configured to turn on or turn off the first bit line switch and the second bit line switch synchronously.

[0016] Optionally, the peripheral circuit further comprises an equalization switch,

[0017] The equalization switch has a seventh end and an eighth end, the seventh end and the eighth end being connected to the second end of two adjacent gating switch units respectively;

[0018] The seventh end being connected to the selected memory cell structure, the equalization switch being configured to:

[0019] During the discharging operation on the selected memory cell structure, the reference voltage is obtained at the eighth end.

[0020] Optionally, the peripheral circuit further comprises a compensation capacitor, one end of the compensation capacitor being connected to the eighth end of the equalization switch, and the other end being connected to the discharging switch unit;

[0021] The compensation capacitor is configured to adjust the voltage value of the reference voltage by adjusting the capacitance value of the compensation capacitor.

[0022] Optionally, the voltage value of the reference voltage is negatively correlated with the on time of the equalization switch, and positively correlated with the capacitance value of the compensation capacitor.

[0023] Optionally, the peripheral circuit further comprises:

[0024] A signal control structure, configured to:

[0025] Perform an initialization operation, during the initialization operation, the gating switch unit is controlled to be turned on;

[0026] After the initialization operation, a discharging operation is performed, during the discharging operation, the discharging switch unit is controlled to be turned on;

[0027] The read operation is performed after the discharge operation, and in the read operation stage, the selected memory cell structure is kept open, and the discharge switch unit is turned on for a period of time and then turned off.

[0028] According to a second aspect of the present application, a method for operating the memory according to any one of the above is provided, comprising:

[0029] performing an initialization operation, and turning on the gating switch unit to control the operation state of the memory cell structure;

[0030] performing a discharge operation after the initialization operation, and turning on the discharge switch unit to provide a direct current signal to the second end of the gating switch unit;

[0031] performing a read operation after the discharge operation, and opening the selected memory cell structure.

[0032] Optionally, the discharge operation comprises:

[0033] in a first operation stage, turning on the current switch to provide a direct current signal to the second end of the gating switch unit; and,

[0034] turning on the voltage switch to provide a reset voltage signal to the second end of the gating switch unit;

[0035] in a second operation stage, turning off the voltage switch.

[0036] Optionally, the discharge operation further comprises:

[0037] in a first operation stage, turning on the equalization switch to generate a reference voltage at the eighth end of the equalization switch;

[0038] in a second operation stage, turning off the equalization switch.

[0039] The memory disclosed in the embodiments of the present application can improve the reliability of the read process of the memory cell structure by adjusting the structure of the peripheral circuit.

[0040] Specifically, the discharge switch unit is arranged in the peripheral circuit, and the discharge switch unit is connected with the gating switch unit, so that the discharge switch unit can provide a direct current signal to the gating switch unit connected with the selected memory cell structure during the discharge operation, thereby ensuring that the voltage corresponding to the gating switch unit is stable before the selected memory cell structure is opened, making the actual read voltage during the read of the memory cell structure closer to the intrinsic read voltage; and the voltage difference when the gating switch unit is turned on and the charge sharing is performed can meet the read condition corresponding to the memory cell structure, thereby improving the reliability of the read of the memory cell structure.

[0041] Other features and advantages of the present application will be described in detail in the following specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0042] In order to more clearly illustrate the technical solutions of the present application, the drawings required to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0043] In order to more completely understand the present application and its beneficial effects, the following will be described in conjunction with the drawings, wherein the same reference numerals in the following description represent the same parts.

[0044] Figure 1 The structural schematic diagram of the memory corresponding to the exemplary embodiments of the present disclosure is provided.

[0045] Figure 2 The circuit diagram of the peripheral circuit of the memory provided for the exemplary embodiments of the present disclosure is provided.

[0046] Figure 3 The voltage control timing diagram provided for the exemplary embodiments of the present disclosure is provided.

[0047] Figure 4 The switch change timing diagram provided for the exemplary embodiments of the present disclosure is provided.

[0048] Figure 5 The flowchart schematic diagram of the memory operation method corresponding to the exemplary embodiments of the present disclosure is provided.

[0049] Explanation of reference numerals:

[0050] 1- memory array, 2- peripheral circuit, 3- word line unit, 4- circuit control structure, 5- signal control structure, 6- memory cell structure, 7- selected memory cell structure;

[0051] 10- gating switch unit, 11- local bit line, 20- discharge switch unit, 30- compensation capacitor, 40- comparator;

[0052] S0- equalization switch, S1- initialization switch, S2- voltage switch, S3- current switch, S4- first bit line switch, S5- second bit line switch;

[0053] Vneg- negative voltage signal, Vref- reference voltage, Vss- initialization signal. DETAILED DESCRIPTION

[0054] With reference to the drawings of the embodiments in the specification, the technical solutions in the embodiments of the specification will be clearly and completely described. Obviously, the described embodiments are some, but not all of the embodiments of the specification. Based on the embodiments in the specification, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0055] It should be noted that the terms "first", "second" and the like in the description and claims of the present application and the above-mentioned accompanying drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or a chronological sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in other than the order illustrated or described herein. In addition, the terms "comprise" and "have" and any variations thereof, are intended to cover non-exclusive inclusion, for example, a process, method, system, product or server comprising a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0056] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numbers in the drawings represent functionally similar or the same elements. Although various aspects of the embodiments are illustrated in the drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0057] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other implementations.

[0058] The term "and / or", used herein, is a descriptive correlation of associated objects, which means that there can be three relationships, for example, A and / or B, which means that there are three cases of A alone, A and B together, and B alone. In addition, the term "at least one" herein means any one of a plurality or any combination of at least two of a plurality, for example, including at least one of A, B and C, which means including any one or more elements selected from the set consisting of A, B and C.

[0059] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the specific embodiments below. Those skilled in the art should understand that the present disclosure can also be implemented without some specific details. In some examples, methods, means, elements and circuits well known to those skilled in the art are not described in detail, in order to highlight the main idea of the present disclosure.

[0060] As described in the background, the read process of the memory cell structure cell is susceptible to BL leakage current, BL corresponding parasitic capacitance and other factors.

[0061] Figure 1 is a structural schematic diagram of a memory embodiment, as described in the background, the memory includes a memory array 1 and a peripheral circuit 2, wherein the memory array 1 has a plurality of memory cell structures 6, and the peripheral circuit 2 is connected with the memory array 1. Figure 1

[0062] In some embodiments, the memory array 1 corresponds to at least part of a phase change memory, and includes a plurality of WLs (word lines), a plurality of bit lines and a plurality of memory cell structures 6, the memory cell structures 6 are located at the intersection of the WLs and the BLs, and binary data can be written into the memory cell structures 6 or read from the memory cell structures 6.

[0063] The memory cell structure 6 can include a crystalline state and an amorphous state, and correspond to different voltage thresholds, and the crystalline state and the amorphous state of the memory cell structure 6 are converted by applying different forms of heat to the memory cell structure 6. The crystalline state is defined as 1, and the corresponding threshold voltage is low, and the amorphous state is defined as 0, and the corresponding threshold voltage is high. The programming operation of writing "1" to the memory cell structure 6 is defined as set operation, and the programming operation of writing "0" to the memory cell structure 6 is defined as reset operation. By applying a voltage greater than the set state and less than the reset state to the selected memory cell structure 7, the memory cell structure 6 in the crystalline state can be opened, but the memory cell structure 6 in the amorphous state cannot be opened, that is, the state reading of the memory cell structure 6 can be completed. Wherein, the voltage threshold value corresponding to each memory cell structure 6 itself, that is, the intrinsic reading voltage corresponding to the BL voltage when reading the selected memory cell structure.

[0064] The peripheral circuit 2 can include a word line unit 3, a circuit control structure 4 and a signal control structure 5. Wherein, the word line unit 3 is configured to determine the target WL corresponding to the target memory cell structure. The signal control structure 5 is configured to perform operations associated with the circuit control structure 4, for example, in the process of reading the memory cell structure 6, control the conduction or turn-off of the switches corresponding to each component of the circuit control structure 4.

[0065] In the embodiment, when reading any memory cell structure 6 in the memory array 1, the BL voltage is raised too early due to the BL leakage current sensitivity, resulting in inaccurate read voltage when reading the memory cell structure cell, or the BL and DL charge sharing effect is affected due to the BL capacitance sensitivity, and then the read state of the memory cell structure cell is inaccurate.

[0066] ​To solve the technical problems existing in the above-mentioned embodiments, the technical scheme of the present application provides a memory and adjusts the structural arrangement of the peripheral circuit thereof, and provides a direct current signal for the gating switch unit connected with the selected memory cell structure in the process of the discharge operation, so as to ensure that the voltage corresponding to the gating switch unit is stable before the selected memory cell structure is opened, so that the actual reading voltage when the memory cell structure is read is closer to the intrinsic reading voltage; and the voltage difference when the gating switch unit is turned on and the charge sharing is performed can meet the reading condition corresponding to the memory cell structure, so as to improve the reliability of the reading of the memory cell structure.

[0067] Figure 2 The peripheral circuit of the memory provided for the exemplary embodiments of the present disclosure is shown in the circuit diagram as shown in Figure 1 and Figure 2 The peripheral circuit 2 of the memory includes a circuit control structure 4.

[0068] The circuit control structure 4 includes:

[0069] A plurality of gating switch units 10, each of which includes a first end and a second end, the first end is connected with the bit line end of any memory cell structure 6, and the gating switch unit 10 is configured to control the operating state of the memory cell structure 6;

[0070] A plurality of discharge switch units 20, each of which is connected with the second end of any gating switch unit 10, and the discharge switch unit 20 is configured to provide a direct current signal to the second end of the gating switch unit 10 connected with the selected memory cell structure 7 in the process of the discharge operation.

[0071] In some embodiments, the peripheral circuit 2 includes the circuit control structure 4, the word line unit 3 and the signal control structure 5, the circuit control structure 4 is configured to select and read the target memory cell structure from the plurality of memory cell structures 6 of the memory array 1 to determine the storage state of the target memory cell structure. The components of the circuit control structure 4 can be equivalent to the circuit diagram as shown in Figure 2 The circuit control structure 4 includes a plurality of gating switch units 10 and a plurality of discharge switch units 20, the first end of each gating switch unit 10 is connected to a memory cell structure 6, and the second end is connected to a discharge switch unit 20, that is, each gating switch unit 10 and each discharge switch unit 20 corresponds to a memory cell structure 6.

[0072] When the gating switch unit 10 is turned on, the storage unit structure 6 corresponding to the gating switch unit 10 can be considered as the selected storage unit structure 7, i.e. the aforementioned target storage unit structure. When binary data needs to be read from the selected storage unit structure 7, the corresponding operation state is reading, and when binary data needs to be written into the selected storage unit structure 7, the corresponding operation state is writing. In this application, the operation state of the selected storage unit structure 7 is taken as an example for description.

[0073] In some embodiments, as shown in FIG. 1, the gating switch unit 10 includes: Figure 2

[0074] The first bit line switch S4 has a third end and a fourth end, the third end is connected with the bit line end of the storage unit structure 6, and the fourth end is connected with the local bit line 11 of the storage array 1.

[0075] The second bit line switch S5 has a fifth end and a sixth end, the fifth end is connected with the fourth end of the first bit line switch S4, and the sixth end is connected with the discharge switch unit 20.

[0076] The gating switch unit 10 is configured to synchronously turn on or turn off the first bit line switch S4 and the second bit line switch S5.

[0077] In some embodiments, the gating switch unit 10 includes the first bit line switch S4 connected with the bit line end of any storage unit structure 6, and the second bit line switch S5 connected with the first bit line switch S4 and the discharge switch unit 20 respectively. The third end of the first bit line switch S4 is the first end of the gating switch unit 10, and the sixth end of the second bit line switch S5 is the second end of the gating switch unit 10. The first bit line switch S4 and the second bit line switch S5 are synchronously turned on or turned off during the reading process of the selected storage unit structure 7, so that the corresponding voltage signals of the two switches change synchronously.

[0078] Figure 3 The voltage change timing diagram provided for the exemplary embodiments of the present disclosure, Figure 4 The switch control timing diagram provided for the exemplary embodiments of the present disclosure. Combined with Figure 3 and Figure 4 It can be known that the turn-on or opening of the first bit line switch S4 is synchronous with the turn-on or opening of the second bit line switch S5, and the BL voltage corresponding to the first bit line switch S4 and the LBL voltage corresponding to the second bit line switch S5 change synchronously during the reading process of the selected storage unit structure 7.

[0079] In some embodiments, the discharge switch unit 20 is connected with the gating switch unit 10, and the discharge switch unit 20 is turned on by the gating switch unit 10 after being turned on, so as to provide a direct current signal for the gating switch unit 10. ​

[0080] Specifically, as shown in Figure 2 The discharge switch unit 20 includes:

[0081] The voltage switch S2 has one end connected to the second end of the gating switch unit 10 and the other end connected to the negative voltage signal Vneg. The voltage switch S2 is configured to be turned on to provide the reset voltage signal to the second end of the gating switch unit 10 during the discharge operation on the selected memory cell structure 7.

[0082] The current switch S3 has one end connected to the second end of the gating switch unit 10 and the other end connected to the negative voltage signal Vneg. The current switch S3 is configured to be turned on to provide the direct current signal to the second end of the gating switch unit 10 during the discharge operation on the selected memory cell structure 7.

[0083] In some embodiments, the discharge switch unit 20 includes the voltage switch S2 and the current switch S3.

[0084] One end of the voltage switch S2 is connected to the sixth end of the second bit line switch S5, and the other end is connected to the negative voltage signal Vneg. When the voltage switch S2 is turned on, the voltage switch S2 can provide the reset voltage signal to the first bit line switch S4 and the second bit line switch S5, so that the BL voltage and the LBL voltage can change from 0V to the voltage value corresponding to the reset voltage signal. The voltage value of the reset voltage signal is equal to the voltage value of the negative voltage signal Vneg.

[0085] One end of the current switch S3 is connected to the sixth end of the second bit line switch S5, and the other end is connected to the negative voltage signal Vneg. When the current switch S3 is turned on, the current switch S3 can provide the direct current signal to the first bit line switch S4 and the second bit line switch S5. The direct current signal can be a direct current. By introducing the direct current signal, it can be ensured that the voltage value of the BL voltage always remains as the reset voltage signal before the selected memory cell structure 7 is turned on.

[0086] In some embodiments, please refer to Figures 3-4 When the first bit line switch S4 and the second bit line switch S5 are turned on at the p2 stage, the voltage switch S2 is turned on at the next stage p3. The BL voltage and the LBL voltage change from 0V to the reset voltage signal due to the synchronous turn-on of the first bit line switch S4 and the second bit line switch S5. At the same time, the current switch S3 is also turned on at the p3 stage to provide the direct current signal to the first bit line switch S4 and the second bit line switch S5, so that the BL voltage is not affected before the selected memory cell structure 7 is turned on, and always remains as the reset voltage signal.

[0087] Please continue to refer to Figure 2The circuit control structure 4 further comprises an initialization switch S1, one end of the initialization switch S1 is connected to the second end of the selected gating switch unit 10, and the other end is grounded.

[0088] The initialization switch S1 is configured to be turned on before the initialization operation on the selected memory cell structure 7, so as to provide the initialization signal Vss to the second end of the gating switch unit 10.

[0089] In some embodiments, please refer to Figure 3 and Figure 4 , before the initialization operation on the selected memory cell structure 7, that is, before any operation on the selected memory cell structure 7, the corresponding Figure 3 and Figure 4 p1 stage. The p1 stage is an unoperated stage, at this time, the initialization switch S1 is turned on, and other switches in the circuit control structure 4 are turned off, so that the BL voltage and the LBL voltage are kept at the voltage value of the initialization signal Vss, that is, the BL voltage and the LBL voltage are kept at 0V.

[0090] When the initialization operation is performed on the selected memory cell structure 7, the corresponding p2 stage, at this time, the initialization switch S1 is turned off, and the first bit line switch S4 and the second bit line switch S5 are turned on.

[0091] Please refer to Figure 2 The circuit control structure 4 further comprises an equalization switch S0, the equalization switch S0 has a seventh end and an eighth end, and the seventh end and the eighth end are respectively connected to the second ends of the adjacent two gating switch units 10.

[0092] The seventh end is connected to the selected memory cell structure 7, and the equalization switch S0 is configured to obtain the reference voltage Vref at the eighth end during the discharging operation on the selected memory cell structure 7.

[0093] In some embodiments, the equalization switch S0 is connected to the second ends of the adjacent two gating switch units 10, that is, connected to the sixth ends of the second bit line switches S5 of the adjacent two gating switch units 10. One end of the equalization switch S0 is connected to the selected memory cell structure 7 through the gating switch unit 10, and the other end is connected to the unselected memory cell structure through the gating switch unit 10.

[0094] In some embodiments, the equalization switch S0 comprises a seventh end and an eighth end, the seventh end is connected to the selected memory cell structure 7, and the eighth end is connected to the unselected memory cell structure. The seventh end corresponds to the DL voltage, and the eighth end corresponds to the Unsel DL voltage, and the voltage value of the Unsel DL voltage is the reference voltage Vref.

[0095] Please refer to Figure 3 andFigure 4 The equalization switch S0 is turned on in the p3 stage, and the UnselDL voltage at the eighth terminal changes from 0V to the reference voltage Vref.

[0096] In some embodiments, the DC signal is introduced through the current switch S3, so the equalization switch S0 can be equivalent to a finite resistance, and the resistance value of the effective resistance is related to the size of the selected storage unit structure 7. The discharge process after the equalization switch S0 is turned on can be equivalent to:

[0097] I*Δt=C*ΔV

[0098] Where Δt is the turn-on time of the equalization switch S0, C is the capacitance value in the discharge process, and I is the current value flowing through the equalization switch S0, and then the UnselDL voltage is the reference voltage Vref:

[0099] Vref=ΔV=-I*Δt / C

[0100] Where the positive and negative can represent the current direction, and it can be considered that charging the capacitor is positive current and discharging the capacitor is negative current.

[0101] Please continue to refer to Figure 2 The circuit control structure 4 further includes a compensation capacitor 30, one end of the compensation capacitor 30 being connected to the eighth terminal of the equalization switch S0, and the other end being connected to the discharge switch unit 20;

[0102] The compensation capacitor 30 is configured to adjust the voltage value of the reference voltage Vref by adjusting the capacitance value of the compensation capacitor 30.

[0103] In some embodiments, one end of the compensation capacitor 30 is connected to the eighth terminal of the equalization switch S0 corresponding to the selected storage unit structure 7, and the other end is connected to the discharge switch unit 20 corresponding to the unselected storage unit structure.

[0104] In some embodiments, the first bit line switch S4 corresponds to a first parasitic capacitance, the second bit line switch S5 corresponds to a second parasitic capacitance, and the seventh terminal of the equalization switch S0 corresponds to a third parasitic capacitance. The capacitance value in the discharge process can include the sum of the capacitance values of the first parasitic capacitance, the second parasitic capacitance, the third parasitic capacitance, and the compensation capacitor 30.

[0105] In some embodiments, according to the above formula, the voltage value of the reference voltage Vref is negatively related to the turn-on time of the equalization switch S0, and is positively related to the capacitance value in the discharge process. Therefore, the compensation capacitor 30 is introduced at the eighth terminal of the equalization switch S0, and the voltage value of the reference voltage Vref is adjusted by adjusting the capacitance value of the compensation capacitor 30. In addition, the voltage value of the reference voltage Vref can also be adjusted by adjusting the turn-on time of the equalization switch S0.

[0106] Please continue to refer to Figure 2 , the circuit control structure 4 further comprises a comparator 40, inputs of the comparator 40 are connected to the seventh end and the eighth end of the equalization switch S0 respectively, and an output of the comparator 40 outputs a read signal.

[0107] In some embodiments, the circuit control structure 4 further comprises the comparator 40 connected to both ends of the equalization switch S0, the comparator 40 acquires and compares the DL voltage and the Unsel DL voltage, and outputs the comparison result as the read signal corresponding to the selected memory cell structure 7, which represents the storage state corresponding to the selected memory cell structure 7.

[0108] In some embodiments, the seventh end of the equalization switch S0 is connected to the sixth end of the second bit line switch S5, and the second bit line switch S5 and the first bit line switch S4 are synchronously turned on, so that the voltage values of the DL voltage, the BL voltage and the LBL voltage are equal and synchronously changed. The eighth end of the equalization switch S0 corresponds to the Unsel DL voltage, and the voltage value of the Unsel DL voltage is the reference voltage Vref. Therefore, the comparator 40 connected to both ends of the equalization switch S0 can acquire the DL voltage and the Unsel DL voltage respectively, by comparing the DL voltage and the Unsel DL voltage, the relationship between the BL voltage and the reference voltage Vref can be determined, and then the read signal is outputted to judge the storage state corresponding to the selected memory cell structure 7. Wherein, the storage state includes "0" state and "1" state.

[0109] Please continue to refer to Figure 3 It can be known that when the selected memory cell structure 7 is in "0" state, the voltage value of the BL voltage remains unchanged at the reset voltage signal and is less than the voltage value of the reference voltage Vref. When the selected memory cell structure 7 is in "1" state, the voltage value of the BL voltage rises from the reset voltage signal and is greater than the voltage value of the reference voltage Vref.

[0110] Figure 3 In the voltage change timing diagram shown, due to the non-ideal state of the current may be too large, when the selected memory cell structure 7 is in "1" state, there is a part of the BL voltage falling back after the charging process and then tending to be stable. If it is considered as an ideal state, the BL voltage will not be affected by the current, and will be charged and stabilized without falling back.

[0111] Please refer to Figure 1 , the peripheral circuit 2 further comprises a signal control structure 5 configured to:

[0112] performing an initialization operation, in the initialization operation stage, the gating switch unit 10 is turned on;

[0113] After the initialization operation, the discharge operation is performed, in the discharge operation stage, the discharge switch unit 20 is controlled to be turned on;

[0114] After the discharge operation, the read operation is performed, in the read operation stage, the selected memory cell structure 7 remains to be opened, and the discharge switch unit 20 is turned on for a period of time and then turned off.

[0115] In some embodiments, the signal control structure 5 is configured to control the turn-on and turn-off of each switch. Please refer to Figure 3 and Figure 4 , Figure 3 and Figure 4 , the p1 stage corresponds to the non-operation stage, the p2 stage corresponds to the initialization operation stage, the p3 stage and the p4 stage correspond to the discharge operation stage, and the p5 stage-p7 stage correspond to the read operation stage.

[0116] According to Figure 4 , based on the control of the signal control structure 5, the initialization switch S1 is turned on in the p1 stage and turned off in the p2 stage; the first bit line switch S4 and the second bit line switch S5 are turned on in the p2 stage and continuously turned on from the p2 stage to the p7 stage, and are turned off in the next p1 stage; the voltage switch S2 is turned on in the p3 stage and turned off in the p4 stage; the current switch S3 is turned on in the p3 stage and continuously turned on from the p3 stage to the p6 stage, and is turned off in the p7 stage; the balance switch S0 is turned on in the p3 stage and turned off in the p4 stage, and the turn-on time is less than or equal to the time corresponding to the p3 stage. The specific turn-on duration can be adaptively adjusted according to the voltage value of the reference voltage Vref.

[0117] In some embodiments, the word line unit 3 further includes a word line switch, which is not shown in the specific position diagram, but it can be clearly seen that one end of the word line switch is connected with the word line corresponding to the selected memory cell structure 7, and in combination with Figure 4 , it can be seen that the WL switch is turned on in the p4 stage, continuously turned on to the p6 stage, and turned off in the p7 stage.

[0118] Correspondingly, the technical scheme of the present application also provides a memory, which comprises:

[0119] The storage array 1 comprises a plurality of memory cell structures 6;

[0120] As shown in Figure 2 , the peripheral circuit 2 is connected with the storage array 1. In the process of reading the memory cell structure 6, the signal control structure 5 controls the circuit control structure 4, so that the timing change as shown in Figure 3 and Figure 4 is obtained.

[0121] Correspondingly, the technical scheme of the present application also discloses a memory operation method, as shown in Figure 5 , which comprises:

[0122] S10: un-operated phase p1, turn on the initialization switch S1 to provide an initialization signal Vss to the seventh end of the first bit line switch S4, the second bit line switch S5 and the equalization switch S0;

[0123] In some embodiments, the un-operated phase can correspond to a phase in which the selected memory cell structure 7 is not read, or can correspond to a state in which the memory cell structure 6 is not selected. Please refer to Figure 3 and Figure 4 At this time, the initialization switch S1 is turned on, and the remaining switches are turned off. The BL voltage, the DL voltage, the LBL voltage and the Unsel DL voltage are all 0V.

[0124] S20: initialization operation phase p2, turn off the initialization switch S1, and turn on the first bit line switch S4 and the second bit line switch S5 to control the operation state of the memory cell structure 6;

[0125] In some embodiments, please refer to Figure 3 and Figure 4 In the initialization operation phase, the first bit line switch S4 and the second bit line switch S5 are turned on, so that the memory cell structure 6 becomes the selected memory cell structure 7. At this time, since the remaining switches are still in the off state, the BL voltage, the DL voltage, the LBL voltage and the Unsel DL voltage still remain 0V.

[0126] The first bit line switch S4 and the second bit line switch S5 are turned on synchronously to realize that the first parasitic capacitor, the second parasitic capacitor and the third parasitic capacitor are all connected to the BL in the subsequent discharge operation, so that the parasitic capacitor in the discharge operation process, i.e. the parasitic capacitor of the BL, is the sum of the first parasitic capacitor, the second parasitic capacitor and the third parasitic capacitor. The parasitic capacitor of the BL becomes larger, so it is not sensitive to the leakage and the sub-threshold conduction current before the selected memory cell structure 7 is turned on, and the BL voltage will not be charged high before the selected memory cell structure 7 is turned on, and the actual read voltage is closer to the intrinsic read voltage.

[0127] Since the BL parasitic capacitor is not sensitive, the DL voltage will rise at the same time and change synchronously with the BL voltage when the selected memory cell structure 7 is turned on, and there is no need to perform charge sharing between the BL and the DL again, which can improve the read success rate and reliability of the selected memory cell structure 7.

[0128] S30: discharge operation phase p3, turn on the current switch S3 and the voltage switch S2 to provide a direct current signal and a reset voltage signal to the second end of the gating switch unit 10; and turn on the equalization switch S0 to generate a reference voltage Vref at the eighth end of the equalization switch S0;

[0129] S40: discharging operation phase p4, turn off voltage switch S2 and equalization switch S0;

[0130] In some embodiments, referring to Figure 3 and Figure 4 , the discharging operation is followed by the reading operation. In p3 phase, i.e. the first operation phase in the discharging operation phase, voltage switch S2 is turned on and provides a reset voltage signal, so that BL voltage, DL voltage and LBL voltage change from 0V to the voltage value Vneg corresponding to the reset voltage signal.

[0131] In p3 phase, current switch S3 is turned on and provides a direct current signal, which can keep BL voltage unchanged before the selected memory cell structure 7 is turned on, and BL voltage is not affected by sub-threshold conduction current and capacitance before the selected memory cell structure 7 is turned on.

[0132] In p3 phase, equalization switch S0 is turned on, and the seventh end and the eighth end of equalization switch S0 are connected, so that equalization switch S0 is equivalent to a finite resistance, a reference voltage Vref is generated, and the voltage value of Unsel DL voltage at the eighth end is equal to the voltage value of the reference voltage Vref.

[0133] When BL voltage, DL voltage and LBL voltage change in p3 phase and remain stable for a period of time, in p4 phase, i.e. the second operation phase in the discharging operation phase, WL switch is turned on, and WL voltage rises.

[0134] S50: reading operation phase p5-p6, the selected memory cell structure 7 is turned on, and first bit line switch S4, second bit line switch S5 and current switch S3 are continuously turned on;

[0135] S60: reading operation phase p7, the selected memory cell structure 7 remains turned on, current switch S3 is turned off, and first bit line switch S4 and second bit line switch S5 are turned on.

[0136] In some embodiments, referring to Figure 3 and Figure 4 , the discharging operation is followed by the reading operation. In p5-p6 phase, WL switch continues to be turned on, and when WL voltage is stable, BL voltage is charged, and LBL voltage and DL voltage change synchronously with BL voltage. At this time, the selected memory cell structure 7 is turned on, and when cell=1, i.e. the selected memory cell structure 7 is in "1" state, BL voltage is greater than reference voltage Vref; when cell=0, i.e. the selected memory cell structure 7 is in "0" state, BL voltage is less than reference voltage Vref.

[0137] In some embodiments, in the p5 stage and the p6 stage, the current switch S3 is continuously turned on in the state of opening the selected memory cell structure 7, and a direct current signal is provided, so that the temperature of the selected memory cell structure 7 after being opened can slowly decrease from a relatively high temperature to a crystallization temperature, and the opened selected memory cell structure 7 still maintains a crystallization state, which is beneficial to improve the read disturbance problem caused by the large overshoot current when the selected memory cell structure 7 is opened.

[0138] In the p7 stage, after the reading is completed, the WL switch is turned off, the WL voltage gradually decreases, the current switch S3 is turned off, and the BL voltage, the DL voltage, the LBL voltage and the UnselDL voltage are restored to 0V.

[0139] Through the above-mentioned operation method of the memory, the read disturbance problem, the accuracy problem of the read voltage and the success rate problem of the reading in the read process of the memory cell structure can be improved, so as to improve the reliability of the read process.

[0140] In the description of the present application, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first", "second" can explicitly or implicitly include one or more features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specifically limited.

[0141] In the above-mentioned embodiments, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0142] The embodiments, implementation manners and related technical features of the present application can be combined, replaced with each other without conflict.

[0143] The above is the preferred embodiment of the present application, which does not limit the present application in any form, but any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present application without departing from the technical solution of the present application, still belongs to the scope of the technical solution of the present application. The selection of the terms used in this paper is intended to best explain the principles, practical application or technical improvement in the market of each embodiment, or to enable other ordinary skilled persons in the art to understand each embodiment disclosed in this paper.

Claims

1. A memory, the memory comprising a memory array and peripheral circuitry, the memory array comprising a plurality of memory cell structures, the peripheral circuitry being electrically connected to the memory cell structures, characterized in that, The peripheral circuit includes: Multiple gating switch units, each gating switch unit including a first terminal and a second terminal, the first terminal being connected to a bit line terminal of a memory cell structure, the gating switch unit being configured to control the operating state of the memory cell structure; Multiple discharge switch units, each of which is connected to the second end of a gating switch unit, wherein the discharge switch unit is configured to provide a DC signal to the gating switch unit connected to the selected memory cell structure during a discharge operation; The discharge switch unit includes a current switch, one end of which is connected to the second terminal of the gating switch unit, and the other end of which is connected to a negative voltage signal. The current switch is configured to turn on to provide the DC signal to the second terminal of the gating switch unit during the discharge operation of the selected memory cell structure.

2. The memory according to claim 1, characterized in that, The discharge switch unit further includes: A voltage switch, one end of which is connected to the second terminal of the gating switch unit and the other end of which is connected to the negative voltage signal, is configured to turn on during a discharge operation of the selected memory cell structure to provide a reset voltage signal to the second terminal of the gating switch unit.

3. The memory according to claim 1, characterized in that, The gating switch unit includes: The first bit line switch has a third terminal and a fourth terminal, the third terminal being connected to the bit line terminal of the memory cell structure, and the fourth terminal being connected to the local bit line of the memory array; The second position line switch has a fifth terminal and a sixth terminal, the fifth terminal being connected to the fourth terminal of the first position line switch, and the sixth terminal being connected to the discharge switch unit. The gating switch unit is configured such that the first bit line switch and the second bit line switch are synchronously turned on or off.

4. The memory according to claim 1, characterized in that, The peripheral circuit also includes an equalization switch. The equalization switch has a seventh terminal and an eighth terminal, and the seventh terminal and the eighth terminal are respectively connected to the second terminal of two adjacent gating switch units; The seventh terminal is connected to the selected storage cell structure, and the equalization switch is configured as follows: During the discharge operation of the selected memory cell structure, a reference voltage is obtained at the eighth terminal.

5. The memory according to claim 4, characterized in that, The peripheral circuit also includes a compensation capacitor, one end of which is connected to the eighth terminal of the equalization switch and one end of the discharge switch unit of the unselected storage cell, and the other end is connected to the negative voltage signal. The compensation capacitor is configured to adjust the voltage value of the reference voltage by adjusting the capacitance value of the compensation capacitor.

6. The memory according to claim 5, characterized in that, The reference voltage value is negatively correlated with the conduction time of the equalization switch and positively correlated with the capacitance value of the compensation capacitor.

7. The memory according to claim 1, characterized in that, The peripheral circuit also includes: The signal control structure is configured as follows: An initialization operation is performed, during which the gating switch unit is turned on. After the initialization operation, a discharge operation is performed, and during the discharge operation phase, the discharge switch unit is controlled to be turned on. A read operation is performed after the discharge operation. During the read operation phase, the selected storage cell structure remains open, and the discharge switch unit is turned off after being turned on for a certain period of time.

8. A method of operating the memory as described in any one of claims 1-7, characterized in that, include: An initialization operation is performed to activate the gating switch unit, thereby controlling the operating state of the memory cell structure; After the initialization operation, a discharge operation is performed to turn on the current switch to provide a DC signal to the second terminal of the gating switch unit; the discharge operation includes a first operation phase; the discharge operation includes: in the first operation phase, turning on the current switch to provide the DC signal to the second terminal of the gating switch unit; A read operation is performed after the discharge operation to enable the selected memory cell structure.

9. The method of operating the memory according to claim 8, characterized in that, The discharge switch unit further includes a voltage switch, and the discharge operation further includes a second operation stage; In the first operation phase, the discharge operation further includes: turning on the voltage switch to provide a reset voltage signal to the second terminal of the gating switch unit; In the second operation phase, the voltage switch is turned off.

10. The method of operating the memory according to claim 8, characterized in that, The peripheral circuit also includes an equalization switch; the discharge operation also includes a second operation stage. The discharge operation also includes: In the first operation phase, the equalization switch is turned on to generate a reference voltage at the eighth terminal of the equalization switch; In the second operation phase, the equalization switch is turned off.

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