DRAM (Dynamic Random Access Memory) test method, electronic equipment and storage medium
By reassigning and reloading the inaccessible address area of the DRAM test system, the problem of low accuracy of DRAM test results is solved, and the normal operation and accurate testing of the DRAM test system are achieved.
Patent Information
- Application Number
- CN202410246878.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-04
- Publication Date
- 2025-09-05
AI Technical Summary
In the existing DRAM testing system, the DRAM address function screening test results do not meet the actual evaluation due to the occupation of some address areas, and the test results are low.
By restarting the DRAM test system, the address information of the inaccessible address area is reassigned, and the updated address information is associated with the loading file driver interface for reloading, ensuring that the inaccessible address area of the DRAM can be tested.
It improves the accuracy of DRAM test results, solves the problem of inaccurate test results caused by inaccessible address areas, and ensures that the DRAM test system is running normally.
Smart Images
Figure CN120600089A_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the field of storage technology and relates to testing technology, and in particular to a DRAM testing method, electronic equipment, and storage medium. Background Art
[0002] In the related art, when a DRAM (Dynamic Random Access Memory) test system performs a DRAM address function screening test, some area addresses in the DRAM are occupied due to the DRAM test system itself, the firmware image file, and the reserved address occupation problem, resulting in some addresses being occupied and the DRAM address function screening test cannot be performed. As a result, the DRAM address function screening test results do not conform to the actual evaluation results, resulting in low accuracy of the DRAM test results. Summary of the Invention
[0003] In view of the above, it is necessary to provide a DRAM testing method, electronic device and storage medium that can solve the technical problem that some address areas cannot be subjected to DRAM address function screening test, resulting in low accuracy of DRAM test results.
[0004] On the one hand, the present application proposes a DRAM testing method, which is applied to an electronic device, wherein the electronic device includes a DRAM, and the electronic device is equipped with a DRAM testing system. The DRAM testing method includes: using the DRAM testing system to test the accessible address area of the DRAM; after completing the test, in response to a received restart instruction, restarting the DRAM testing system, and reallocating the address information of the inaccessible address area of the DRAM; reading the updated address information of the inaccessible address area after the reallocation, and associating the updated address information with the loading file driver interface of the electronic device for reloading; when the reloading is detected to be complete, testing the inaccessible address area based on the updated address information.
[0005] According to an embodiment of the present application, before the address information of the inaccessible address area of the DRAM is reallocated, the method further includes: obtaining memory allocation information of the DRAM, and counting the current memory usage of the DRAM based on the memory allocation information, wherein the memory allocation information includes information of the first address space of the accessible address area that has completed the test and address information of the inaccessible address area.
[0006] According to an embodiment of the present application, the reallocation of address information of the inaccessible address area of the DRAM includes: obtaining information of the second address space of the dependent file stored in the DRAM and information of the third address space corresponding to the kernel address of the DRAM test system from the address information of the inaccessible address area; based on the information of the first address space, the information of the second address space and the information of the third address space, the address space of the dependent file and the kernel address of the DRAM test system are respectively reallocated according to preset allocation rules.
[0007] According to an embodiment of the present application, the address space reallocation of the kernel addresses of the dependent file and the DRAM test system based on the information of the first address space, the information of the second address space and the information of the third address space according to preset allocation rules includes: obtaining memory information of all addresses from the information of the first address space; dividing the memory information into multiple address segments according to preset division rules; obtaining the actual memory capacity of each address; obtaining the first memory capacity of the second address space and the second memory capacity of the third address space; filtering out target address segments that are larger than the first memory capacity and the second memory capacity from the multiple address segments; and reallocating the address space of the kernel addresses of the dependent file and the DRAM test system based on the actual memory capacity corresponding to the filtered target address segments.
[0008] According to an embodiment of the present application, the testing of the inaccessible address area based on the updated address information includes: clearing the memory of the second address space and the third address space in the inaccessible address area; and testing the released second address space and the third address space based on the updated address information.
[0009] According to an embodiment of the present application, associating the updated address information with the loading file driver interface of the electronic device for reloading includes: filtering out the address space information of the dependent file and the kernel address information of the DRAM test system from the updated address information; associating the address space information of the dependent file, the dependent file and the kernel address information of the DRAM test system with the loading file driver interface of the electronic device for reloading.
[0010] According to an embodiment of the present application, the electronic device also includes a hardware storage device. After the address information of the inaccessible address area of the DRAM is reallocated, the method also includes: storing the updated address information corresponding to the dependent file and the kernel address of the DRAM test system after the reallocation to the hardware storage device.
[0011] According to an embodiment of the present application, the testing of the accessible address area of the DRAM using the DRAM test system includes: obtaining a preset test algorithm; and calling the preset test algorithm to test the address space corresponding to the accessible address area.
[0012] On the other hand, the present application also proposes a DRAM testing device that runs on an electronic device, wherein the electronic device includes a DRAM, and the electronic device is equipped with a DRAM testing system. The DRAM testing device includes: a testing unit for using the DRAM testing system to test the accessible address area of the DRAM; a reallocation unit for restarting the DRAM testing system in response to a received restart instruction after completing the test, and reallocating the address information of the inaccessible address area of the DRAM; a reloading unit for reading the updated address information of the inaccessible address area after reallocation, and associating the updated address information with the loading file driver interface of the electronic device for reloading; and the testing unit is also used to test the inaccessible address area based on the updated address information after detecting that the reloading is complete.
[0013] On the other hand, the present application also proposes an electronic device, which includes: a storage device storing computer-readable instructions; and a processor executing the computer-readable instructions stored in the storage device to implement a DRAM testing method.
[0014] On the other hand, the present application also proposes a storage medium, in which computer-readable instructions are stored. The computer-readable instructions are executed by a processor in an electronic device to implement a DRAM testing method.
[0015] Based on the above technical solution, after completing the DRAM accessible address area test, the embodiment of the present application restarts the DRAM test system, reallocates the address information of the DRAM inaccessible address area, and reallocates the address information so that the DRAM inaccessible address area meets the conditions for performing DRAM testing. The updated address information after reallocation is further loaded to ensure the normal operation of the restarted DRAM test system. Finally, after the loading is completed, the updated address information corresponding to the inaccessible address area is tested, which solves the problem of low DRAM test result accuracy caused by the inability to test the inaccessible address area in the prior art, and improves the accuracy of DRAM test results. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 This is a schematic diagram of the structure of an electronic device for implementing a DRAM testing method provided in an embodiment of the present application.
[0017] Figure 2This is a flowchart of a DRAM testing method provided in an embodiment of the present application.
[0018] Figure 3 This is a flowchart of a DRAM testing method provided by another embodiment of the present application.
[0019] Figure 4 This is a flowchart of a DRAM testing method provided by another embodiment of the present application.
[0020] Figure 5 This is a flowchart of address space reallocation for dependent files and kernel addresses of a DRAM test system provided by an embodiment of the present application.
[0021] Figure 6 This is a flowchart of a DRAM testing method provided by another embodiment of the present application.
[0022] Figure 7 This is a flowchart of a DRAM testing method provided by another embodiment of the present application.
[0023] Figure 8 This is a functional module diagram of the DRAM testing device provided in an embodiment of the present application. DETAILED DESCRIPTION
[0024] In order to make the objectives, technical solutions and advantages of this application clearer, this application is described in detail below with reference to the accompanying drawings and specific embodiments.
[0025] It should be noted that in this application, "at least one" means one or more, and "more than one" means two or more than two. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The terms "first", "second", "third", "fourth", etc. (if any) in the specification, claims and drawings of this application are used to distinguish similar objects, rather than to describe a specific order or sequence.
[0026] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a concrete manner. The following embodiments and features in the embodiments may be combined with each other unless there is a conflict.
[0027] like Figure 1 , which is a schematic diagram of the structure of an electronic device for implementing a DRAM testing method provided in an embodiment of the present application.
[0028] In an embodiment of the present application, the DRAM testing method is applied to one or more electronic devices 1. The electronic device 1 is a device that can automatically perform numerical calculations and / or information processing according to pre-set or stored computer-readable instructions. Its hardware includes but is not limited to a microprocessor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), an embedded device, etc.
[0029] The electronic device 1 can be any electronic product that can interact with a user, such as a personal computer, a tablet computer, a smart phone, a personal digital assistant (PDA), a game console, an interactive network television (IPTV), a smart wearable device, etc.
[0030] The electronic device 1 may include a network device and / or a user device, wherein the network device includes, but is not limited to, a single network electronic device, a group of electronic devices consisting of multiple network electronic devices, or a cloud based on cloud computing consisting of a large number of hosts or network electronic devices.
[0031] The network where the electronic device 1 is located includes, but is not limited to: the Internet, a wide area network, a metropolitan area network, a local area network, a virtual private network (VPN), etc.
[0032] In the embodiment of the present application, the electronic device 1 includes, but is not limited to, a storage device 12, a processor 13, and computer-readable instructions stored in the storage device 12 and executable on the processor 13, such as a memory test program.
[0033] Those skilled in the art will understand that the schematic diagram is merely an example of the electronic device 1 and does not constitute a limitation on the electronic device 1. The electronic device 1 may include more or fewer components than shown in the figure, or a combination of certain components, or different components. For example, the electronic device 1 may also include input and output devices, network access devices, buses, etc.
[0034] The processor 13 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor, a processor, or any conventional processor. The processor 13 is the computing core and control center of the electronic device 1, connecting various parts of the entire electronic device 1 using various interfaces and lines, and executing the operating system of the electronic device 1 as well as various installed applications and program codes.
[0035] The storage device 12 may be an external storage device and / or an internal storage device of the electronic device 1. Furthermore, the storage device 12 may be a storage device in a physical form, such as a dynamic random access memory (DRAM), a hardware storage device, and the like.
[0036] Combine Figure 2 The storage device 12 in the electronic device 1 includes a DRAM and a hardware storage device. The storage device 12 stores computer-readable instructions. The processor 13 can execute the computer-readable instructions stored in the hardware storage device 12 to implement the following. Figure 2 DRAM testing method shown.
[0037] like Figure 2 FIG. 1 is a flow chart of a DRAM testing method provided by an embodiment of the present application. The DRAM testing method is applied to electronic devices (e.g. Figure 1 In the electronic device 1), the electronic device includes a storage device, such as a DRAM. According to different requirements, the order of the steps in the flowchart can be changed, and some steps can be omitted.
[0038] 201. An electronic device uses a DRAM test system to test an accessible address area of a DRAM.
[0039] In at least one embodiment of the present application, the electronic device is equipped with a DRAM test system, and the DRAM test system may be stored in a DRAM.
[0040] In one embodiment, the DRAM test system is used to test and check the quality and performance of DRAM to ensure its reliability and stability. For example, the DRAM test system can test and verify DRAM address-related functions.
[0041] The electronic device receives the DRAM test request, responds to the DRAM test request, and starts the DRAM test system. After detecting that the DRAM test system has been started, the electronic device controls the DRAM test system to use the DRAM test system to test the accessible address area of the DRAM.
[0042] A DRAM test request can be triggered when a user performs a DRAM test, or when an electronic device receives a DRAM test request from another device. The DRAM test request carries relevant information about the DRAM test, including DRAM address test conditions, DRAM stability test conditions, and more.
[0043] The accessible address area refers to the DRAM memory space that users can directly access and manipulate. Specifically, the accessible address area is jointly managed by the operating system, CPU, or other hardware storage devices. Users can access this area through specific programming interfaces (such as pointers in the C language). In the C language, a pointer is a variable type that stores the memory address of the accessible address area. For example, the accessible address area stores user data, such as downloaded audio, video, and applications. Users can access and manipulate data in this memory space by using pointers.
[0044] The embodiments of the present application can detect and diagnose errors or problems existing in the address space corresponding to the accessible address area of the DRAM by calling a preset test algorithm, and test the accessible address area of the DRAM.
[0045] 202 , after completing the test, the electronic device restarts the DRAM test system in response to a received restart instruction, and reallocates address information of an inaccessible address area of the DRAM.
[0046] In at least one embodiment of the present application, after testing the accessible address area of the DRAM, the electronic device re-operates the underlying driver to restart the DRAM test system and reallocates address information of the inaccessible address area of the DRAM.
[0047] In at least one embodiment of the present application, an inaccessible address area refers to an area that is inaccessible due to a portion of the address being occupied due to issues such as the DRAM test system itself, the firmware image file, and reserved address occupation. Reallocation refers to reallocating address information in the inaccessible address area.
[0048] In an embodiment of the present application, by reallocating the address information of the inaccessible address area in the DRAM, the DRAM test system supports remapping of related file space addresses, ensuring that the address area after the address space reallocation can operate normally in the DRAM test system, thereby improving the accuracy of DRAM testing.
[0049] 203 , the electronic device reads updated address information of the reallocated inaccessible address area, and associates the updated address information with a loading file driver interface of the electronic device for reloading.
[0050] In at least one embodiment of the present application, after the electronic device reallocates the address information of the inaccessible address area, it then associates the updated address information after the reallocation to the DRAM test system loading file driver interface, and reloads the file, so that the DRAM test system is restored to the current executable DRAM related functional test state after loading and running, ensuring that the updated address information of the inaccessible address area can be tested normally after the DRAM test system is restarted.
[0051] 204 , after the electronic device detects that the reloading is completed, the electronic device tests the inaccessible address area based on the updated address information.
[0052] In at least one embodiment of the present application, after detecting that the loading and running of the DRAM test system is completed, the electronic device obtains the updated address information after loading, and tests the inaccessible address area based on the updated address information, that is, the spatial address of the dependent file and the kernel address of the DRAM test system are tested, and the spatial address of the dependent file and the kernel address of the DRAM test system are fixed addresses of the DRAM and belong to the inaccessible address area of the DRAM.
[0053] In an embodiment of the present application, by reallocating the address information of the inaccessible address area of the DRAM, restarting the DRAM test system, and reloading the updated address information corresponding to the address information of the inaccessible address area, the inaccessible address area is made to meet the conditions for testing and verification, thereby realizing the testing of the inaccessible address area of the DRAM, solving the problem of low accuracy of DRAM test results caused by the inability to test the inaccessible address area in the prior art, and improving the accuracy of the DRAM test results.
[0054] In an embodiment of the present application, after completing the test of the accessible address area of the DRAM, the DRAM test system is restarted, and the address information of the inaccessible address area of the DRAM is reallocated. The reallocation makes the inaccessible address area of the DRAM meet the conditions for performing the DRAM test, and the updated address information after the reallocation is further loaded to ensure the normal operation of the restarted DRAM test system. Finally, after the loading is completed, the updated address information corresponding to the inaccessible address area is tested, which solves the problem of low DRAM test result accuracy caused by the inability to test the inaccessible address area in the prior art, and improves the accuracy of the DRAM test results.
[0055] Figure 3 This is a flow chart of a DRAM testing method provided by another embodiment of the present application. The DRAM testing method is applied to electronic devices (e.g. Figure 1 In the electronic device 1), the electronic device includes a storage device, such as a DRAM. According to different requirements, the order of the steps in the flowchart can be changed, and some steps can be omitted.
[0056] 301. The electronic device uses a DRAM test system to test an accessible address area of a DRAM.
[0057] The details of step 301 can be found above. Figure 2 The detailed description of step 201 is omitted here.
[0058] 302. After completing the test, the electronic device restarts the DRAM test system in response to the received restart instruction, obtains the memory allocation information of the DRAM, and counts the current memory usage of the DRAM based on the memory allocation information, wherein the memory allocation information includes information on the first address space of the accessible address area that has completed the test and address information of the inaccessible address area.
[0059] In at least one embodiment of the present application, memory allocation information is stored in the DRAM, and the electronic device obtains the memory allocation information of the DRAM including: obtaining a target path corresponding to the memory allocation information; and obtaining the memory allocation information from a file associated with the target path.
[0060] The target path refers to the storage path of memory allocation information. The electronic device controls the DRAM test system to obtain memory allocation information from a preset path file. This memory allocation information can include information about the memory management system allocating or reclaiming memory space for programs during DRAM operation. Typically, this memory allocation information includes memory allocation, memory usage, memory reclaim, and memory leaks. This memory allocation information can be used to understand the memory usage of various programs or files.
[0061] The memory allocation information of this embodiment includes information of the first address space of the accessible address area that has completed the test and address information of the inaccessible address area, wherein the information of the first address space includes the address size, initial address and currently used memory capacity of the accessible address area.
[0062] In at least one embodiment of the present application, the current memory usage refers to the memory capacity that has been occupied or used.
[0063] In at least one embodiment of the present application, the electronic device controls the DRAM test system to count the current memory usage of the DRAM based on the memory allocation information, including: counting the currently used memory capacity of the address information of the first address space and the inaccessible address area, and then obtaining the current memory usage of the DRAM.
[0064] 303 , the electronic device reallocates address information of the inaccessible address area of the DRAM.
[0065] 304 , the electronic device reads updated address information of the reallocated inaccessible address area, and associates the updated address information with a loading file driver interface of the electronic device for reloading;
[0066] 305 , after the electronic device detects that the reloading is completed, it tests the inaccessible address area based on the updated address information.
[0067] The details of steps 303 and 305 can be found above. Figure 2 The detailed description of steps 202 and 204 is not repeated here.
[0068] Figure 4 This is a flow chart of a DRAM testing method provided by another embodiment of the present application. The DRAM testing method is applied to electronic devices (e.g. Figure 1 In the electronic device 1), the electronic device includes a storage device, such as a DRAM. According to different requirements, the order of the steps in the flowchart can be changed, and some steps can be omitted.
[0069] 401. The electronic device uses a DRAM test system to test an accessible address area of a DRAM.
[0070] The details of step 401 can be found above. Figure 2 The detailed description of step 201 is omitted here.
[0071] 402. After completing the test, the electronic device restarts the DRAM test system in response to the received restart instruction, and obtains information on the second address space of the dependent file stored in the DRAM and information on the third address space corresponding to the kernel address of the DRAM test system from the address information of the inaccessible address area.
[0072] In this embodiment, the address information of the inaccessible address area includes information about the second address space of the dependent file stored in the DRAM and information about the third address space corresponding to the kernel address of the DRAM test system. For example, the information about the second address space includes the address size, initial address, and currently used memory capacity of the dependent file; and the information about the third address space includes the address size, initial address, and currently used memory capacity corresponding to the kernel address of the DRAM test system.
[0073] Dependent files refer to files referenced or relied upon by DRAM during the DRAM testing process. Dependent files include metadata, drivers, firmware, and testing tools. DRAM metadata files contain information about the specifications, configuration, capacity, and other aspects of the memory device. DRAM drivers are provided by hardware manufacturers to ensure that the operating system can correctly identify and configure DRAM devices. DRAM firmware is usually provided by hardware manufacturers and can be updated to fix errors or add new features. DRAM testing tools include DRAM test system software and performance analyzers. This dependent file is necessary for the normal operation of DRAM, and the second address space corresponding to the dependent file belongs to the inaccessible address area in DRAM. If DRAM is to operate normally, all necessary dependent files must be present. Otherwise, DRAM may experience errors or malfunction during operation.
[0074] The kernel address is the address space where the kernel code of the DRAM test system is placed. Furthermore, the kernel address refers to the memory address allocated within the address space. This kernel address is directly accessible only to the operating system kernel, not to applications, and typically requires special permissions and access methods. It generally falls within the inaccessible address area of DRAM and is typically only directly accessible to kernel code, while applications interact with the kernel through methods such as system calls.
[0075] 403 , the electronic device reallocates the address spaces of the dependent files and the kernel addresses of the DRAM test system according to a preset allocation rule based on the information of the first address space, the information of the second address space, and the information of the third address space.
[0076] In at least one embodiment of the present application, allocation rules can be pre-set, and the preset allocation rules are pre-set based on the address size of the dependent file in the DRAM and the address size of the kernel address of the DRAM test system. For example, the address size of the dependent file is 8 bytes, and the preset allocation rule is set to be less than or equal to 8 bytes. The allocated address space can be 9 bytes or 10 bytes. This embodiment does not impose any restrictions here.
[0077] In at least one embodiment of the present application, address space reallocation refers to the division of address areas of dependent files and kernel addresses of the DRAM test system. Specifically, address space reallocation refers to the reallocation of storage space of the second address space of the dependent file and the third address space corresponding to the kernel address of the DRAM test system.
[0078] In at least one embodiment of the present application, based on the information of the first address space, the information of the second address space, and the information of the third address space, the address space of the dependent file and the kernel address of the DRAM test system are respectively reallocated according to the preset allocation rules. The specific calculation steps can be referred to below. Figure 5 The detailed description of steps 501 to 505 is not repeated here.
[0079] In an embodiment of the present application, the address space of the dependent files in the DRAM and the kernel address of the DRAM test system are reallocated according to preset allocation rules. The DRAM test system supports remapping of the related dependent file space addresses, ensuring that the address area after the address space reallocation can operate normally in the DRAM test system, thereby improving the accuracy of DRAM testing.
[0080] In at least one embodiment of the present application, the electronic device further includes a hardware storage device, and common hardware storage devices include a memory card, a network storage device, a solid-state drive (SSD), etc. After the electronic device detects that the dependent file and the kernel address of the DRAM test system are reallocated, the electronic device stores updated address information corresponding to the second address space corresponding to the dependent file and the third address space corresponding to the kernel address of the DRAM test system after the reallocation in the hardware storage device.
[0081] In the embodiment of the present application, the hardware storage device can be placed in a static access memory, and the advantage of the fast access speed of the static access memory can be utilized to improve the storage and reading efficiency of the updated address information.
[0082] 404 , the electronic device reads updated address information of the reallocated inaccessible address area, and associates the updated address information with a loading file driver interface of the electronic device for reloading.
[0083] 405 , after the electronic device detects that the reloading is completed, it tests the inaccessible address area based on the updated address information.
[0084] In an embodiment of the present application, by reallocating dependent files and the kernel addresses of the DRAM test system, and testing the dependent files and the kernel addresses of the DRAM test system after the reallocation of DRAM, the testing of the accessible address area and the inaccessible address area of DRAM is achieved, the coverage of the test address is expanded, and the accuracy of the DRAM test results is improved.
[0085] The details of steps 404 and 405 can be found above. Figure 2 The detailed description of steps 203 and 204 is omitted here.
[0086] In this embodiment, testing the inaccessible address area based on the updated address information includes: clearing the memory of the second address space and the third address space in the inaccessible address area; and testing the released second address space and the third address space based on the updated address information.
[0087] In at least one embodiment of the present application, after detecting that the DRAM test system has completed loading and running, the electronic device clears the memory of the original second address space and the third address space in the DRAM, and releases the original second address space and the third address space in the DRAM, and then tests the released second address space and the third address space.
[0088] In an embodiment of the present application, by releasing the second address space and the third address space, the second address space and the third address space meet the conditions for testing and verification, thereby realizing the testing of the inaccessible address area of DRAM and improving the accuracy of the DRAM test results.
[0089] In at least one embodiment of the present application, the second address space corresponds to the address space of the dependent file, and the third address space corresponds to the kernel address of the DRAM test system. According to the current memory usage, the address space of the dependent file and the kernel address of the DRAM test system are re-divided into address areas. By releasing the original file addresses corresponding to the address space of the dependent file and the kernel address of the DRAM test system, the condition for DRAM test verification to be performed in the address area is achieved, thereby ensuring the normal operation of the DRAM test system while increasing the test address coverage of the DRAM, thereby avoiding the problem that some addresses are occupied and the DRAM address function screening test cannot be performed, realizing the test of inaccessible address areas, and improving the accuracy of DRAM test results.
[0090] Figure 5This is a flowchart of address space reallocation of dependent files and kernel addresses of a DRAM test system provided by an embodiment of the present application.
[0091] 501. The electronic device obtains memory information of all addresses and actual memory capacity of each address from information in a first address space.
[0092] In at least one embodiment of the present application, memory information refers to information such as the address size, initial address and currently used memory capacity of the accessible address area in the information of the first address space. The first address space includes multiple addresses, and each address corresponds to actual memory capacity.
[0093] 502. The electronic device divides the memory information into a plurality of address segments according to a preset division rule.
[0094] In at least one embodiment of the present application, division rules can be pre-set, and the preset division rules can be pre-set according to the data memory capacity in the accessible address area. For example, for video data that has been downloaded by users in the accessible address area, the size of the address segment of the video data cannot exceed 2GB; for audio data that has been downloaded by users in the accessible address area, the size of the address segment of the audio data cannot exceed 500MB.
[0095] In an embodiment of the present application, the address segment is obtained by dividing the memory information according to a preset division rule. The memory information can be divided into multiple address segments of different sizes, and an address segment that is larger than the actual memory capacity of each address is searched from the multiple address segments and determined as the target address segment of the corresponding address.
[0096] 503. The electronic device obtains the first memory capacity of the second address space and the second memory capacity of the third address space.
[0097] In at least one embodiment of the present application, the first memory capacity includes the currently used memory capacity of the second address space, the currently used memory capacity of the second address space includes the memory information of the dependent files reloaded in DRAM and the memory capacity of the address information in the dependent files that need to be tested after reallocation; the second memory capacity includes the currently used memory capacity of the third address space, the currently used memory capacity of the third address space includes the memory capacity of the kernel addresses reloaded in DRAM and the memory capacity of the address information of the kernel addresses that need to be tested after reallocation.
[0098] 504. The electronic device selects a target address segment that is larger than the first memory capacity and the second memory capacity from the multiple address segments.
[0099] In an embodiment of the present application, when the DRAM test system requests a certain size of memory, the operating system may allocate memory larger than actually needed, because allocating smaller memory may waste memory space. By allocating larger memory, frequent memory allocation and release operations can be reduced. This embodiment determines the target address segment of the corresponding address by finding an address segment that is larger than the actual memory capacity of each address, so that when the DRAM test system requests memory, it is allocated a larger target address segment, according to the target memory capacity corresponding to the larger target address segment.
[0100] 505 , the electronic device reallocates the address space of the dependent file and the kernel address of the DRAM test system based on the actual memory capacity corresponding to each filtered target address segment.
[0101] In an embodiment of the present application, a target address segment that is larger than the first memory capacity and the second memory capacity is screened out from multiple address segments to obtain the target memory capacity of the corresponding target address segment, and the address space of the dependent files and the kernel address of the DRAM test system is reallocated according to the target memory capacity of each target address segment.
[0102] Figure 6 This is a flow chart of a DRAM testing method provided by another embodiment of the present application. The DRAM testing method is applied to electronic devices (e.g. Figure 1 In the electronic device 1), the electronic device includes a storage device, such as a DRAM. According to different requirements, the order of the steps in the flowchart can be changed, and some steps can be omitted.
[0103] 601. The electronic device uses a DRAM test system to test an accessible address area of a DRAM.
[0104] 602. After completing the test, the electronic device restarts the DRAM test system in response to the received restart instruction, and obtains information on the second address space of the dependent file stored in the DRAM and information on the third address space corresponding to the kernel address of the DRAM test system from the address information of the inaccessible address area.
[0105] 603 , the electronic device reallocates the address spaces of the dependent file and the kernel address of the DRAM test system according to a preset allocation rule based on the information of the first address space, the information of the second address space, and the information of the third address space.
[0106] The details of steps 601 to 603 can be found above. Figure 4 The detailed description of steps 401 to 403 is not repeated here.
[0107] 604 , the electronic device reads updated address information of the reallocated inaccessible address area, and filters out information of the address space of the dependent file and information of the kernel address of the DRAM test system from the updated address information.
[0108] 605 , the electronic device associates the address space information of the dependent file, the dependent file and the kernel address information of the DRAM test system to the loading file driver interface of the electronic device for reloading.
[0109] In at least one embodiment of the present application, by filtering out the address space information of the dependent file and the kernel address information of the DRAM test system from the updated address information, the filtered information is associated with the loading file driver interface of the DRAM test system, and the DRAM test system loads the dependent file and the kernel address of the DRAM test system, so that the DRAM test system is restored to a state where relevant functional tests can be executed, thereby facilitating subsequent testing of the inaccessible address area of the DRAM.
[0110] 606 , after the electronic device detects that the reloading is completed, it tests the inaccessible address area based on the updated address information.
[0111] The details of step 606 can be found above. Figure 2 The detailed description of step 204 is omitted here.
[0112] In an embodiment of the present application, by associating the information of the address space of the dependent file and the dependent file to the loading file driver interface for reloading, it is ensured that the DRAM test system can still operate normally after the address information of the inaccessible address area is reallocated, thereby realizing the testing of the accessible address area and the inaccessible address area of DRAM, expanding the coverage of the test address, and improving the accuracy of the DRAM test results.
[0113] Figure 7 This is a flow chart of a DRAM testing method provided by another embodiment of the present application. The DRAM testing method is applied to electronic devices (e.g. Figure 1 In the electronic device 1), the electronic device includes a storage device, such as a DRAM. According to different requirements, the order of the steps in the flowchart can be changed, and some steps can be omitted.
[0114] 701. The electronic device obtains a preset test algorithm.
[0115] In at least one embodiment of the present application, the preset test algorithm is a test algorithm pre-set for accurately testing the address space of the DRAM. The test algorithm is usually designed as an automated program, which is written into the DRAM through a pre-set test module to trigger possible errors during the DRAM test process.
[0116] 702 , the electronic device calls a preset test algorithm to test the address space corresponding to the accessible address area.
[0117] In the embodiment of the present application, since the preset test algorithm is set accordingly for accurately testing the address space of the DRAM, accurate testing of the accessible address area of the DRAM can be achieved through the preset test algorithm.
[0118] 703 , after completing the test, the electronic device restarts the DRAM test system in response to the received restart instruction, and reallocates address information of the inaccessible address area of the DRAM.
[0119] 704 , the electronic device reads the updated address information of the reallocated inaccessible address area, and associates the updated address information with a loading file driver interface of the electronic device for reloading.
[0120] 705 , after the electronic device detects that the reloading is completed, it tests the inaccessible address area based on the updated address information.
[0121] For details of steps 703-705, please refer to the above Figure 2 The detailed description of steps 202-204 is not repeated here.
[0122] In the embodiment of the present application, by testing the accessible address area and the inaccessible address area of the DRAM, the coverage of the test address is expanded and the accuracy of the DRAM test result is improved.
[0123] like Figure 8 , which is a functional block diagram of a DRAM test device provided in an embodiment of the present application. The DRAM test device 11 operates on an electronic device, which includes a storage device, such as a DRAM, and a plurality of storage cells. The DRAM test device 11 includes a test unit 110, a reallocation unit 111, and a reload unit 112. The modules / units referred to herein are a series of computer-readable instruction segments that can be accessed by the processor 13 and can perform a fixed function, and are stored in the storage device 12.
[0124] The test unit 110 is used to test the accessible address area of the DRAM using the DRAM test system; the reallocation unit 111 is used to restart the DRAM test system in response to a received restart instruction after the test is completed, and reallocate the address information of the inaccessible address area of the DRAM; the reloading unit 112 is used to read the updated address information of the inaccessible address area after the reallocation, and associate the updated address information with the loading file driver interface of the electronic device for reloading; the test unit 110 is also used to test the inaccessible address area based on the updated address information after detecting that the reloading is completed.
[0125] If the modules / units integrated in the electronic device 1 are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, and can also instruct the relevant hardware to complete them through computer-readable instructions. The computer-readable instructions can be stored in a computer-readable storage medium. When the computer-readable instructions are executed by the processor, the steps of the above-mentioned method embodiments can be implemented.
[0126] Computer-readable instructions include computer-readable instruction codes, which may be in source code form, object code form, executable files, or some intermediate form. Computer-readable media may include any entity or device capable of carrying computer-readable instruction codes, recording media, USB flash drives, mobile hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), and random access memory (RAM).
[0127] The storage device 12 can be used to store computer-readable instructions and / or modules. The processor 13 implements various functions of the electronic device 1 by running or executing the computer-readable instructions and / or modules stored in the storage device 12, and by accessing data stored in the storage device 12. The storage device 12 may primarily include a program storage area and a data storage area. The program storage area may store an operating system, at least one application required for a function (such as a sound playback function, an image playback function, etc.), and the data storage area may store data created based on the use of the electronic device. The storage device 12 may include non-volatile and volatile storage devices, such as a hard disk, memory, a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) card, a flash card, at least one disk storage device, a flash memory device, or other storage devices.
[0128] Exemplarily, the computer-readable instructions may be divided into one or more modules / units, one or more of which are stored in the storage device 12 and executed by the processor 13 to complete the present application. The one or more modules / units may be a series of computer-readable instruction segments capable of completing a specific function, and the computer-readable instruction segments are used to describe the execution process of the computer-readable instructions in the electronic device 1. For example, the computer-readable instructions may be divided into a test unit 110, a redistribution unit 111, and a reload unit 112.
[0129] For details about the functions of each module / unit, please refer to the above Figure 2-7 The detailed description is not repeated here.
[0130] The embodiments of the present application expand the coverage of the test address and improve the accuracy of the DRAM test results by testing the accessible address area and the inaccessible address area of the DRAM.
[0131] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of modules is merely a logical function division, and other division methods may be used in actual implementation.
[0132] Modules described as separate components may or may not be physically separate, and components shown as modules may or may not be physical units, that is, they may be located in one place or distributed across multiple network elements. Some or all of these modules may be selected to achieve the purpose of this embodiment based on actual needs.
[0133] In addition, the functional modules in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional modules.
[0134] Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the present application is defined by the appended claims rather than the foregoing description, and all changes that come within the meaning and range of equivalents of the claims are intended to be embraced therein. Any reference to a figure in a claim should not be construed as limiting the claim to which it relates.
[0135] Furthermore, it is clear that the word "comprising" does not exclude other units or steps, and the singular does not exclude the plural. Multiple units or devices may also be implemented by a single unit or device through software or hardware. Terms such as first and second are used to indicate names and do not imply any particular order.
Claims
1. A DRAM testing method, applied to electronic equipment, characterized in that: The electronic device includes a DRAM, and the electronic device is equipped with a DRAM testing system. The DRAM testing method includes: Testing the accessible address area of the DRAM using the DRAM test system; After completing the test, in response to a received restart instruction, restart the DRAM test system and reallocate address information of the inaccessible address area of the DRAM; Reading updated address information of the inaccessible address area after reallocation, and associating the updated address information with a loading file driver interface of the electronic device for reloading; After the reloading is detected to be complete, the inaccessible address area is tested based on the updated address information.
2. The DRAM testing method according to claim 1, wherein: Before reallocating the address information of the inaccessible address area of the DRAM, the method further includes: Memory allocation information of the DRAM is obtained, and current memory usage of the DRAM is counted based on the memory allocation information, wherein the memory allocation information includes information of a first address space of an accessible address area that has completed the test and address information of an inaccessible address area.
3. The DRAM testing method according to claim 2, wherein: The reallocation of address information of the inaccessible address area of the DRAM includes: Acquire information of a second address space of the dependent file stored in the DRAM and information of a third address space corresponding to a kernel address of the DRAM test system from address information of the inaccessible address area; Based on the information of the first address space, the information of the second address space, and the information of the third address space, address spaces of the dependent file and the kernel address of the DRAM test system are respectively reallocated according to a preset allocation rule.
4. The DRAM testing method according to claim 3, wherein: The reallocating the address spaces of the dependent file and the kernel address of the DRAM test system respectively according to a preset allocation rule based on the information of the first address space, the information of the second address space, and the information of the third address space includes: Acquire memory information of all addresses from the information of the first address space; Dividing the memory information into multiple address segments according to a preset division rule; Get the actual memory capacity of each address; Acquire a first memory capacity of the second address space and a second memory capacity of the third address space; Filtering a target address segment that is larger than the first memory capacity and the second memory capacity from the multiple address segments; The address space of the dependent file and the kernel address of the DRAM test system is reallocated based on the actual memory capacity corresponding to the filtered target address segment.
5. The DRAM testing method according to claim 3, wherein: The testing of the inaccessible address area based on the updated address information includes: clearing the memory of the second address space and the third address space in the inaccessible address area; The released second address space and the third address space are tested based on the updated address information.
6. The DRAM testing method according to claim 3, wherein: The step of associating the updated address information with a loading file drive interface of the electronic device for reloading includes: Filtering the address space information of the dependent file and the kernel address information of the DRAM test system from the updated address information; The address space information of the dependent file, the dependent file and the kernel address information of the DRAM test system are associated with the loading file driver interface of the electronic device for reloading.
7. The DRAM testing method according to claim 3, wherein: The electronic device further includes a hardware storage device. After reallocating the address information of the inaccessible address area of the DRAM, the method further includes: The updated address information corresponding to the reallocated dependent file and the kernel address of the DRAM test system is stored in the hardware storage device.
8. The DRAM testing method according to claim 1, wherein: The testing of the accessible address area of the DRAM by using the DRAM test system includes: Get the preset test algorithm; The preset test algorithm is called to test the address space corresponding to the accessible address area.
9. An electronic device, characterized in that: The electronic device comprises: a storage device storing computer-readable instructions; and A processor executes the computer-readable instructions stored in the storage device to implement the DRAM testing method according to any one of claims 1 to 8.
10. A storage medium, characterized in that: The storage medium stores computer-readable instructions, and the computer-readable instructions are executed by a processor in an electronic device to implement the DRAM testing method according to any one of claims 1 to 8.