Dynamic random access memory and method of manufacturing the same

Abstract

A DRAM is provided, which includes a silicon substrate, buried word lines and active regions. The silicon substrate has a carrier surface. The buried word lines are buried in the silicon substrate. The active regions are located on the carrier surface. The buried word lines intersect the active regions. Each buried word line has a first width in one of the active regions and a second width outside the active regions, and the first width is greater than the second width. A manufacturing method of the DRAM is also provided. By the above configuration of the DRAM, word line disturbance and single cell failure can be reduced, and the density of the DRAM can be improved.

Description

Technical Field

[0001] This disclosure relates to a dynamic random access memory (DRAM). More specifically, this disclosure relates to a DRAM with buried word lines and a method for manufacturing the same. Background Technology

[0002] Existing DRAM cells include transistors and capacitors coupled to those transistors. As DRAM density increases, the channel length of conventional planar transistors decreases, leading to short-channel effects, including drain-induced barrier lowering (DIBL). The reduction in device size decreases the distance between word lines and bit lines, ultimately resulting in higher parasitic capacitance between these word lines and bit lines.

[0003] Buried word line (BL) DRAM structures, which bury word lines within the substrate, are one solution to this problem. However, as the structure shrinks further, the etching depth of shallow trench isolation (STI) changes significantly, eventually causing word line interference after the buried word lines are formed. Summary of the Invention

[0004] Therefore, this disclosure provides a DRAM with buried word lines and a method for manufacturing the same.

[0005] According to embodiments of this disclosure, a DRAM includes a silicon substrate, buried word lines, and active regions. The silicon substrate has a carrier surface. The buried word lines are buried in the silicon substrate. The active regions are located on the carrier surface. The buried word lines intersect with the active regions. Each buried word line has a first width in one of the active regions and a second width outside the active regions, and the first width is greater than the second width.

[0006] In embodiments disclosed herein, each buried word line includes at least one conductive structure. The material of the conductive structure includes polycrystalline silicon or tungsten.

[0007] In the embodiments disclosed herein, each active region includes a drain region and a source region. The source region is located between the drain regions. Each drain region on the carrier surface is parallelogram-shaped.

[0008] According to embodiments of this disclosure, a manufacturing method includes the following steps: forming a first hard mask on a carrier surface of a silicon substrate; forming a second hard mask; etching a second trench on the silicon substrate; etching a first trench on the silicon substrate; and forming buried word lines in the second trenches respectively. The silicon substrate has active stripes and isolation stripes, with the active stripes disposed on the carrier surface and the isolation stripes separating the active stripes. The second hard mask is disposed on the first hard mask. The second trench is etched on the silicon substrate through a second opening in the second hard mask. Before etching the first trench, oxide structures are respectively disposed in the second trench. The first trench is etched on the silicon substrate through a first opening in the first hard mask, and a third trench is etched on the oxide structures in the second trench. The second trench divides the active stripes into a plurality of active regions.

[0009] In embodiments disclosed herein, each buried word line includes at least one conductive structure. The material of the conductive structure includes polycrystalline silicon or tungsten.

[0010] In embodiments disclosed herein, the first area of ​​each first opening is smaller than the second area of ​​each second opening.

[0011] In the embodiments disclosed herein, after the oxide structure is formed in the second trench, the top surface of the oxide structure in the second trench is coplanar with the surface of the carrier.

[0012] In the embodiments disclosed herein, the active strips extend along a first direction. Each active strip has a consistent third width in a second direction. The second direction is perpendicular to the first direction.

[0013] In embodiments disclosed herein, after a second hard mask is applied over a first hard mask, the second hard mask fills some of the first openings in the first hard mask.

[0014] In embodiments disclosed herein, the active strip extends along a first direction. In this first direction, each first opening has a fourth width, and each second opening has a fifth width. The fifth width is greater than the fourth width.

[0015] The above configuration of DRAM can reduce word line interference and single cell failures, and can also increase DRAM density.

[0016] The foregoing has provided a fairly broad overview of the features and technical advantages of this disclosure to facilitate a better understanding of the detailed description that follows. Additional features and technical advantages of this disclosure are described below and form the subject matter of the claims. Those skilled in the art will understand that the disclosed concepts and specific embodiments can be used as a basis for modifying or designing other structures or processes to achieve the purposes of this disclosure. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit or scope of this disclosure as set forth in the claims of the invention application.

[0017] It should be understood that the foregoing general description and the following detailed description are provided by way of example and are intended to provide further explanation of the claimed invention. Attached Figure Description

[0018] A more complete understanding of this disclosure can be obtained by referring to the accompanying drawings and by reading the following detailed description of the embodiments:

[0019] Figures 1A to 8A A schematic plan view of the DRAM manufacturing process of an embodiment of this disclosure; and

[0020] Figures 1B to 8B According to Figures 1A to 8A A schematic cross-sectional view of the secant line BB in the diagram. Detailed Implementation

[0021] Reference will now be made in detail to the present embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Where possible, the same element symbols are used in the drawings and description to refer to the same or similar parts.

[0022] It should be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers, or parts, such elements, components, regions, layers, or parts are not limited by these terms. Rather, these terms are used only to distinguish one element, component, region, layer, or part from another region, layer, or part. Therefore, without departing from the teachings of this disclosure, the first element, component, region, layer, or part discussed below may be referred to as the second element, component, region, layer, or part.

[0023] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the concepts of this disclosure. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should be further understood that, as used in this specification, the terms “comprises” and “comprising” indicate the presence of the stated feature, integer, step, operation, element, or component, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.

[0024] As used herein, the terms "patterning" and "patterned" are used in this disclosure to describe the operation of forming a predetermined pattern on a surface. Patterning operations include various steps and processes, and vary depending on the specific embodiment. In some embodiments, an existing film or layer is patterned using a patterning process. The patterning process includes the steps of: forming a mask on the existing film or layer; and removing the unmasked film or layer using an etching process or other removal process. The mask may be a photoresist or a hard mask. In some embodiments, a patterned layer is formed directly on the surface using a patterning process. The patterning process includes the steps of: forming a photosensitive film on the surface; performing a photolithography process; and performing a development process. The remaining photosensitive film is retained and integrated into a semiconductor device.

[0025] Figures 1A to 8A This is a plan view of the DRAM manufacturing process as described in the embodiments of this disclosure. Figures 1B to 8B respectively along Figures 1A to 8A A schematic cross-sectional view of the secant line BB, wherein the secant line BB is parallel to the first direction d1.

[0026] See Figure 1A and Figure 1B In the embodiments disclosed herein, the silicon substrate 100 has a carrier surface 101.

[0027] For example, in one embodiment, an oxide layer 110 and a nitride layer 111 are disposed on a carrier surface 101 of a silicon substrate 100, with the oxide layer 110 located between the silicon substrate 100 and the nitride layer 111. Furthermore, a photoresist layer 112 is disposed on the nitride layer 111, the photoresist layer 112 is patterned, and a portion of the nitride layer 111 is exposed.

[0028] Specifically, the photoresist layer 112 has a plurality of openings 113, and each opening 113 extends along a first direction d1. In a second direction d2, the gaps between the openings 113 have a width w7. For example, in an embodiment, the width w7 of the gap is approximately 12 nm. However, this embodiment is not limited to this. The width w7 of the gap can be in the range of approximately 10 nm to approximately 14 nm.

[0029] See Figure 2A and Figure 2B The silicon substrate 100 is etched. Specifically, it is removed after etching. Figure 1B The nitride layer 111 and oxide layer 110 in the silicon substrate 100 retain a plurality of active strips 102, and a plurality of isolation strips 103 are disposed between the active strips 102.

[0030] The isolation strip 103 separates the active strips 102. In other words, each isolation strip 103 is positioned between two active strips 102.

[0031] For example, the material of the isolation strip 103 may include oxides, but this disclosure is not limited thereto.

[0032] Specifically, the isolation strip 103 is parallel to the active strip 102. In addition, both the isolation strip 103 and the active strip 102 extend along the first direction d1, and in the second direction d2, the third width w3 of each active strip 102 is consistent, and the first direction d1 is perpendicular to the second direction d2.

[0033] In one embodiment, each isolation strip 103 has a sixth width w6 in the second direction d2, and the ratio of the third width w3 to the sixth width w6 is approximately 1.8:1, but this disclosure is not limited thereto. In another embodiment of this disclosure, the ratio of the third width w3 to the sixth width w6 ranges from approximately 1.4:1 to approximately 2.3:1.

[0034] See Figure 3A and Figure 3B A first hard mask 120 is disposed on the carrier surface 101 of the silicon substrate 100. In an embodiment, the first hard mask 120 has a plurality of first openings 121.

[0035] Furthermore, in the first direction d1, each first opening 121 has a fourth width w4. For example, in this embodiment, the fourth width w4 is about 24 nm, but the present disclosure is not limited thereto. In some embodiments, the fourth width w4 may range from about 23 nm to about 25 nm.

[0036] Specifically, in this embodiment, when the first hard mask 120 is set, the active strip 102 is parallel and remains untrimmed. The first opening 121 of the first hard mask 120 overlaps with the active strip 102.

[0037] For example, in one embodiment, each first opening 121 is formed as a strip, and each active strip 102 overlaps with more than one first opening 121. The first opening 121 extends along a third direction d3, and the angle between the first direction d1 and the third direction d3 is an acute angle, and the angle between the second direction d2 and the third direction d3 is also an acute angle.

[0038] Additionally, the etched hard mask layer 122 may include nitride and silicon, and is disposed between the first hard mask 120 and the carrier surface 101 of the silicon substrate 100 for silicon etching. The distribution area of ​​the first hard mask 120 on the carrier surface 101 is substantially the same as the distribution area of ​​the etched hard mask layer 122 on the carrier surface 101.

[0039] See Figure 4A and Figure 4B A second hard mask 130 is disposed on the first hard mask 120. Specifically, the second hard mask 130 is disposed on the silicon substrate 100 having the first hard mask 120, and some of the first openings 121 are filled with the second hard mask 130. The second hard mask 130 has a plurality of second openings 131, and each second opening 131 is aligned with one of the first openings 121 of the first hard mask 120. In other words, each second opening 131 exposes one of the first openings 121 of the first hard mask 120.

[0040] For example, in one embodiment, the second hard mask 130 has an oxide layer 132, a silicon layer 133, and a bottom layer 134. The bottom layer 134 includes an organic material for gap filling and uniformity. Each second opening 131 passes through the oxide layer 132, the silicon layer 133, and the bottom layer 134, and is aligned with one of the first openings 121. Some of the first openings 121 are filled with the bottom layer 134.

[0041] Furthermore, in the first direction d1, each second opening 131 has a fifth width w5, and the fifth width w5 is greater than the fourth width w4. For example, in this embodiment, the fifth width w5 is about 41 nm, but the present disclosure is not limited thereto. In some embodiments, the fifth width w5 may range from about 39 nm to about 43 nm.

[0042] Furthermore, each of the second openings 131 is formed in a circular shape. The second opening 131 exposes a portion of the active strip 102 defined by the isolation strip 103 and the first hard mask 120.

[0043] See Figure 5A and Figure 5B The silicon substrate 100 is etched using a second hard mask 130, forming a plurality of second trenches 104. Specifically, the etching removes portions of the active stripe 102, the isolation stripe 103, and the first opening 121 of the first hard mask 120 exposed by the second hard mask 130, with the second hard mask 130 positioned above the first hard mask 120. Therefore, the second hard mask 130 further increases the etching depth, and the second trenches 104 can be thin.

[0044] In this embodiment, the second trench 104 divides the active strip 102 into a plurality of active regions 109. In other words, the active regions 109 in this embodiment are separated by the second trench 104.

[0045] Furthermore, the etching of the second trench 104 and the etching of the isolation strip 103 are performed in different steps. Therefore, the depths of the second trench 104 and the isolation strip 103 can be appropriately controlled.

[0046] See Figure 6A and Figure 6B After a plurality of oxide structures 105 are formed on the silicon substrate 100, the second hard mask 130 is removed. In this embodiment, the silicon substrate 100 has a second trench 104, and the oxide structures 105 are respectively formed in the second trench 104. The first opening 121 of the first hard mask 120 exposes the oxide structures 105 and a portion of the carrier surface 101 of the silicon substrate 100.

[0047] For example, in an embodiment, the material of oxide structure 105 may include oxide or oxide and nitride, and the top surface 106 of oxide structure 105 is coplanar with the carrier surface 101.

[0048] See Figure 7A and Figure 7B The silicon substrate 100 and its oxide structure 105 are etched using a first hard mask 120. Specifically, a first trench 107 is etched in the silicon substrate 100 through a first opening 121 of the first hard mask 120, and a third trench 108 is etched in the oxide structure 105 in the second trench 104.

[0049] See Figure 8A and Figure 8B A plurality of embedded character lines 140 are respectively disposed in the first trench 107 and the third trench 108. Specifically, the embedded character lines 140 can be disposed along the third direction d3.

[0050] Specifically, the buried word line 140 may include conductive structures 141 and 142. A nitride layer 143 may cover the conductive structure 142. The material of the conductive structure 141 may include tungsten, and the material of the conductive structure 142 may include polysilicon, and the material of the nitride layer 143 may include nitride.

[0051] The buried word lines 140 are installed after etching the first trench 107 and the third trench 108, so the inner surfaces of the first trench 107 and the third trench 108 can be cleaned before depositing the buried word lines 140. The buried word lines 140 outside the active region 109 can be properly isolated without causing current leakage.

[0052] Furthermore, in the DRAM 200 of this embodiment, buried word lines 140 intersect with active regions 109, and each buried word line 140 has a first width w1 in one of the active regions 109 and a second width w2 outside the active regions 109. The second width w2 is smaller than the first width w1, and the density of the active regions 109 can be increased.

[0053] In addition, the active region 109 includes a source region 1010, a drain region 1011, and a drain region 1012. The source region 1010 is located between the drain regions 1011 and 1012, and each drain region 1011, 1012 on the carrier surface 101 is parallelogram in shape.

[0054] In other words, see also Figure 5A and Figure 5B The etching of the second trench 104 cuts the active strip 102 in a thin and precise manner, thus increasing the density of the active region 109, and the drain regions 1011 and 1012 can be parallelogram-shaped. In addition, the size of the drain regions 1011 and 1012 can be large, which can further reduce single-cell failures when setting up capacitors.

[0055] As described above, in the DRAM of the embodiments disclosed herein, word line interference can be reduced by having buried word lines with a thinner width outside the active region, and single cell failures can be reduced by having active regions, thus increasing the density of the DRAM.

[0056] Although this disclosure has been described in considerable detail with reference to certain embodiments, other embodiments are also possible. Therefore, the spirit and scope of the claims should not be limited to the embodiments described herein.

[0057] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of this disclosure without departing from the scope or spirit of this disclosure. In summary, this disclosure is intended to cover modifications and variations thereof, provided that such modifications and variations fall within the scope of the claims of the invention application.

[0058] [Symbol Explanation]

[0059] 100: Silicon substrate

[0060] 101: Carrier surface

[0061] 102: Active stripes

[0062] 103: Isolation Strip

[0063] 104: Second trench

[0064] 105: Oxide Structure

[0065] 106: Top surface

[0066] 107: First trench

[0067] 108: Third trench

[0068] 109: Active Zone

[0069] 110: Oxide layer

[0070] 111: Nitride layer

[0071] 112: Photoresist layer

[0072] 113: Opening

[0073] 120: First Hard Mask

[0074] 121: First Opening

[0075] 130: Second Hard Mask

[0076] 131: Second opening

[0077] 132: Oxide layer

[0078] 133: Silicon layer

[0079] 134: Bottom layer

[0080] 140: Hidden Character Line

[0081] 141, 142: Conductive Structure

[0082] 143: Nitride layer

[0083] 1010: Source Region

[0084] 1011, 1012: Drain region

[0085] BB: Noodles

[0086] d1: First direction

[0087] d2: Second direction

[0088] d3:Third direction

[0089] w1-w7: Width.

Claims

1. A dynamic random access memory, characterized in that, Include: A silicon substrate having a carrier surface; A plurality of buried word lines are embedded in the silicon substrate, wherein each of the buried word lines includes a first conductive structure and a second conductive structure on the first conductive structure; and Multiple active regions are located on the surface of the carrier; The embedded character lines intersect with the active regions, and each of the embedded character lines has a first width in one of the active regions and a second width outside the active regions, wherein the first width is greater than the second width, the bottom of the first conductive structure outside the active regions is lower than the bottom of the first conductive structure in the active regions, and the top of the second conductive structure outside the active regions is flush with the top of the second conductive structure in the active regions.

2. The dynamic random access memory according to claim 1, wherein the first conductive structure comprises tungsten and the second conductive structure comprises polycrystalline silicon.

3. The dynamic random access memory of claim 1, wherein each of the active regions comprises: Multiple drain regions; and Source polar region, Furthermore, the source region is located between the drain regions, and each drain region is a parallelogram in shape on the surface of the carrier.

4. A method for manufacturing a dynamic random access memory, characterized in that, Include: A first hard mask is disposed on the carrier surface of a silicon substrate, wherein the silicon substrate has a plurality of active strips disposed on the carrier surface and a plurality of isolation strips separating the active strips. A second hard mask is set on the first hard mask; A plurality of second trenches are etched on the silicon substrate through a plurality of second openings in the second hard mask; A plurality of oxide structures are respectively provided in the second trenches; A plurality of first trenches are etched on the silicon substrate through a plurality of first openings in the first hard mask, and a plurality of third trenches are etched on the oxide structures in the second trenches; and A plurality of buried character lines are respectively set in the first trench and the third trench. The second groove divides the active strips into a plurality of active regions.

5. The manufacturing method according to claim 4, wherein each embedded character line comprises: At least one conductive structure; Furthermore, the material of this conductive structure includes polycrystalline silicon or tungsten.

6. The manufacturing method according to claim 4, wherein after the oxide structure is provided in the second trenches, the top surface of the oxide structure in the second trenches is coplanar with the surface of the carrier.

7. The manufacturing method of claim 4, wherein the active strips extend along a first direction, and each of the active strips has a consistent third width in a second direction, and the second direction is perpendicular to the first direction.

8. The manufacturing method of claim 4, wherein after the second hard mask is disposed on the first hard mask, the second hard mask fills some of the first openings of the first hard mask.

9. The manufacturing method of claim 4, wherein the active strips extend along a first direction, and in the first direction, each first opening has a fourth width, and each of the second openings has a fifth width, and the fifth width is greater than the fourth width.

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