Semiconductor integrated circuit, device provided with same, and bus system

Abstract

The invention provides a semiconductor integrated circuit, a device provided with the semiconductor integrated circuit, and a bus system, which can improve power efficiency between input and output. The semiconductor integrated circuit includes: a first power supply input terminal; a second power input terminal; a first power output terminal; a first power line connecting the first power input terminal and the first power output terminal; a first AC filter provided on the first power supply line; a first countercurrent prevention circuit provided in the first power supply line between the first AC filter and the first power supply output terminal; a bypass line that bypasses the first backflow prevention circuit; the charge pump circuit is arranged on the bypass line; and a control circuit that operates the charge pump circuit so that a current flows through the bypass line and the first power supply output terminal when an input voltage between the first power supply input terminal and the second power supply input terminal is lower than a first voltage.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor integrated circuit, a device including the semiconductor integrated circuit, and a bus system. Background Art

[0002] Conventionally, there is known a bus system that transmits a differential signal via a pair of wires (for example, see Patent Document 1).

[0003] In bus systems that transmit differential signals over a pair of wires, applying a DC voltage to the wires allows them to function not only as communication lines but also as power lines. In recent years, the development of semiconductor integrated circuits that extract a DC voltage from a pair of wires and supply a DC current to a downstream load has progressed.

[0004] However, the voltage input to the semiconductor integrated circuit from a pair of wirings fluctuates depending on the differential signal transmitted over the pair of wirings, and therefore may sometimes be lower than the voltage output from the semiconductor integrated circuit to the load. When the voltage input to the semiconductor integrated circuit from a pair of wirings falls below the voltage output from the semiconductor integrated circuit to the load, current is temporarily unable to be supplied from the semiconductor integrated circuit to the load. As a result, power efficiency between the input and output of the semiconductor integrated circuit may decrease.

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2014-107660 Summary of the Invention

[0006] The present disclosure provides a semiconductor integrated circuit capable of improving power efficiency between input and output, a device including the semiconductor integrated circuit, and a bus system.

[0007] A semiconductor integrated circuit of the first type has: a first power input terminal; a second power input terminal; a first power output terminal; a first power line connecting the first power input terminal and the first power output terminal; a first AC filter, which is arranged on the first power line; a first backflow prevention circuit, which is arranged on the first power line between the first AC filter and the first power output terminal; a bypass line, which bypasses the first backflow prevention circuit; a charge pump circuit, which is arranged on the bypass line; and a control circuit, which operates the charge pump circuit when the input voltage between the first power input terminal and the second power input terminal is lower than a first voltage, so that current flows through the bypass line and the first power output terminal.

[0008] The device of the second mode comprises: a semiconductor integrated circuit; and a load, which is powered by the semiconductor integrated circuit, wherein the semiconductor integrated circuit has: a first power input terminal; a second power input terminal; a first power output terminal, which is electrically connected to the load; a first power line, which connects the first power input terminal and the first power output terminal; a first AC filter, which is arranged on the first power line; a first backflow prevention circuit, which is arranged on the first power line between the first AC filter and the first power output terminal; a bypass line, which bypasses the first backflow prevention circuit; a charge pump circuit, which is arranged on the bypass line; and a control circuit, which operates the charge pump circuit when the input voltage between the first power input terminal and the second power input terminal is lower than a first voltage, so that current flows through the bypass line and the first power output terminal.

[0009] A bus system according to a third aspect includes the semiconductor integrated circuit according to the first aspect and a pair of wirings including a first wiring electrically connected to the first power input terminal and a second wiring electrically connected to the second power input terminal.

[0010] According to the present disclosure, it is possible to improve power efficiency between input and output of a semiconductor integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 FIG. 1 is a diagram illustrating a bus system of a semiconductor integrated circuit to which the present disclosure is applicable.

[0012] Figure 2 This is a timing chart illustrating waveforms of various components of the bus system.

[0013] Figure 3 This is a diagram illustrating a bus system of a semiconductor integrated circuit including a first comparative example.

[0014] Figure 4 1 is a diagram illustrating waveforms of various components of a bus system of a semiconductor integrated circuit including a first comparative example.

[0015] Figure 5 This is a diagram illustrating a bus system including the semiconductor integrated circuit according to the first embodiment.

[0016] Figure 6 This is a diagram illustrating waveforms of various components of the bus system included in the semiconductor integrated circuit according to the first embodiment.

[0017] Figure 7 This is a diagram showing a first configuration example of the semiconductor integrated circuit according to the first embodiment.

[0018] Figure 8 This is a diagram showing a second configuration example of the semiconductor integrated circuit according to the first embodiment.

[0019] Figure 9 This is a diagram showing a third configuration example of the semiconductor integrated circuit according to the first embodiment.

[0020] Figure 10 This is a diagram showing a third configuration example of the semiconductor integrated circuit according to the first embodiment.

[0021] Figure 11 This is a diagram illustrating a portion of a control circuit included in a semiconductor integrated circuit.

[0022] Figure 12 This is a diagram showing a first configuration example of an AC filter included in a semiconductor integrated circuit.

[0023] Figure 13 This is a diagram showing a second configuration example of an AC filter included in a semiconductor integrated circuit.

[0024] Figure 14 is a diagram illustrating a circuit for implementing thermal shutdown. DETAILED DESCRIPTION

[0025] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0026] Figure 1 FIG. 1 is a diagram illustrating a bus system of a semiconductor integrated circuit to which the present disclosure is applicable. Figure 1 The illustrated bus system 1000 is a communication system comprising a plurality of drivers (in this example, five drivers 211, 212, 213, 214, and 215 (hereinafter also referred to as "drivers 211, etc.")) connected to each other in a balanced manner via a pair of wiring lines 81 and 82. Drivers 211, etc. have identical communication interface circuits and communicate with each other via differential signals transmitted over the pair of wiring lines 81 and 82.

[0027] Figure 1 The bus system 1000 is applied to communication between air-conditioning devices. The bus system 1000 includes a plurality of air-conditioning devices connected to each other in a balanced manner via a pair of wirings 81 and 82. Figure 1 In FIG. 1 , an indoor unit 201 , a remote control terminal 202 , an indoor unit 203 , a remote control terminal 204 , and an outdoor unit 205 are exemplified as a plurality of air-conditioning devices.

[0028] Indoor unit 201 has a driver 211 and a load 221, and performs air conditioning in room A. Remote control terminal 202 has a driver 212 and a load 222, and is an operation terminal for remotely controlling indoor unit 201. Indoor unit 203 has a driver 213 and a load 223, and performs air conditioning in room B. Remote control terminal 204 has a driver 214 and a load 224, and is an operation terminal for remotely controlling indoor unit 203. Outdoor unit 205 has a driver 215 and a load 225, and discharges air to the outside that has undergone heat exchange with the refrigerant circulating between outdoor unit 205 and indoor units 201 and 203.

[0029] Specific examples of the loads 221 and 223 include processors such as MPUs (Micro Processing Units) and power controllers that control the air conditioning operations of the indoor units 201 and 203. Specific examples of the loads 222 and 224 include MPUs, display devices such as LCDs (Liquid Crystal Displays), and switches. Specific examples of the load 225 include MPUs and power controllers that control the compression operation of the refrigerant in the outdoor unit 205.

[0030] Driver 211 and the like are based on the home bus system (HBS), but may be based on a bus system other than HBS. Driver 211 and the like include a terminal OUTA connected to wiring 81 via a capacitor (not shown) and a terminal OUTB connected to wiring 82 via a capacitor (not shown).

[0031] Figure 2 This is a timing diagram illustrating waveforms of various components of a bus system. Bus system 1000, for example, employs the AMI (Alternate Mark In version) method for waveforms of signals transmitted between multiple devices. Driver 211 and the like include a transmission circuit that converts a rectangular wave signal DIN received from a microcomputer such as an MPU into a differential pair of AMI signals and transmits the signals from terminals OUTA and OUTB. Driver 211 and the like may also include a receiving circuit that converts a differential pair of AMI signals received from terminals OUTA and OUTB into a rectangular wave signal DOUT and transmits the signals to a microcomputer such as an MPU. The AMI signal transmitted or received via terminal OUTA and the AMI signal transmitted or received via terminal OUTB have opposite phases.

[0032] By applying a DC voltage to the pair of wirings 81 and 82 that transmit such differential signals, the pair of wirings 81 and 82 can be used not only as communication lines but also as power lines. Next, a semiconductor integrated circuit that extracts a DC voltage from the pair of wirings 81 and 82 and supplies a DC current to a subsequent load will be described.

[0033] Figure 3 This is a diagram illustrating a bus system of a semiconductor integrated circuit including a first comparative embodiment. Figure 3 The bus system 300 shown includes a pair of wirings 81 and 82 to which a DC voltage is applied by a DC power supply 88, a choke coil 87 inserted into the pair of wirings 81 and 82, and a semiconductor integrated circuit 100 that extracts the DC voltage from the pair of wirings 81 and 82. Based on the DC voltage extracted from the pair of wirings 81 and 82, the semiconductor integrated circuit 100 supplies a DC output current Io to a subsequent load 85.

[0034] The semiconductor integrated circuit 100 is provided with a plurality of devices (in Figure 1 In the case of an indoor unit 201, the indoor unit 201, the remote control terminal 202, the indoor unit 203, the remote control terminal 204, and the outdoor unit 205. The semiconductor integrated circuit 100 supplies a DC output current Io to, for example, a load 85 within the device included in the semiconductor integrated circuit 100 (for example, in the case of a semiconductor integrated circuit 100 included in the indoor unit 201, the load 221 within the indoor unit 201 or the driver 211). The semiconductor integrated circuit 100 is provided inside or outside a driver within the device included in the semiconductor integrated circuit 100 (for example, in the case of a semiconductor integrated circuit 100 included in the indoor unit 201, the driver 211 within the indoor unit 201).

[0035] exist Figure 3 In addition to the semiconductor integrated circuit 100, the bus system 300 further includes a driver IC (Integrated Circuit) 120 connected to a pair of wirings 81 and 82 via capacitors 121 and 122, and a diode bridge 80 inserted into the pair of wirings 81 and 82. Figure 3 In the figure, one driver IC 120 is shown, but a plurality of driver ICs 120 are electrically connected to a pair of wirings 81 and 82 via capacitive coupling. The driver IC 120 is, for example, Figure 1 The semiconductor integrated circuits such as the driver 211 shown in the figure are provided to transmit or receive Figure 2 A differential pair of AMI signals is shown.

[0036] exist Figure 3In the embodiment, the semiconductor integrated circuit 100 includes a first power input terminal (terminal INP), a second power input terminal (terminal INN), a first power output terminal (terminal OUTP), a second power output terminal (terminal OUTN), filter circuits 101 and 102, and a discharge circuit 103.

[0037] Semiconductor integrated circuit 100 extracts a DC voltage from the voltage input to a pair of terminals INP and INN (input voltage VIN) via filter circuits 101 and 102, and outputs this DC voltage as output voltage VO from a pair of terminals OUTP and OUTN to load 85. Output voltage VO is smoothed by capacitor 84 externally connected between OUTP and OUTN. Load 85 operates using output voltage VO as a power supply voltage. Output voltage VO causes a DC output current Io (load current) to flow through load 85.

[0038] Figure 4 The example contains Figure 3 The waveforms of various components of bus system 300 of semiconductor integrated circuit 100 in the first comparative embodiment are shown. An AMI signal with a phase opposite to that of the AMI signal input to terminal INP is input to terminal INN. Semiconductor integrated circuit 100 extracts a DC voltage from input voltage VIN, the potential difference between terminals INP and INN, via filter circuits 101 and 102. The DC output voltage VO, the potential difference between a pair of terminals OUTP and OUTN, is then output to load 85.

[0039] As the characteristics of AMI signal, such as Figure 4 As shown, a period during which the input voltage VIN is lower than the output voltage VO may occur in a quarter cycle. During this period, because the potential at terminal INP is lower than the potential at terminal OUTP, no current flows from terminal INP to terminal OUTP. Similarly, during this period, the potential at terminal INN rises relative to the potential at terminal OUTN, so no current flows from terminal OUTN to terminal INN. In other words, the output current Io temporarily stops flowing during this period.

[0040] Such a temporary stop in current flow may cause discrete changes in the DC current Idc flowing through the pair of wirings 81 and 82. When the DC current Idc undergoes discrete changes, the AMI signal transmitted through the pair of wirings 81 and 82 is attenuated. Therefore, a continuous current supply is required to flow a constant DC current Idc. During the period when the input voltage VIN is lower than the output voltage VO, the semiconductor integrated circuit 100 discharges the DC current from the terminal INP via the discharge circuit 103 (see FIG. 1 ). Figure 3 ) returns to the terminal INN. Figure 4 As shown, continuous current supply is achieved with respect to the direct current Idc.

[0041] However, since the discharge current Idis not supplied to the load 85 flows in a quarter cycle, the semiconductor integrated circuit 100 is temporarily unable to supply current (output current Io) to the load 85. This temporary output stoppage of the semiconductor integrated circuit 100 may increase the capacitance of the capacitor 84 connected between the pair of terminals OUTP and OUTN, leading to an increase in circuit size. Furthermore, since the discharge current Idis not supplied to the load 85 flows in a quarter cycle, the efficiency of the output power of the semiconductor integrated circuit 100 relative to the input power is less than 75% at most. Furthermore, the resistance components within the discharge circuit 103 generate heat due to the discharge current Idis, requiring design considerations for component damage caused by heat generation. Consequently, the structure of the semiconductor integrated circuit 100 sometimes makes it difficult to apply it to high current applications at high input voltages.

[0042] In contrast, Figure 5 The semiconductor integrated circuit 110 of the first embodiment shown includes a charge pump circuit 50 capable of supplying current (output current Io) to the load 85 even when the input voltage VIN is lower than the output voltage VO. This achieves continuous current supply to the load 85 and improved power efficiency between the input and output of the semiconductor integrated circuit 110. Furthermore, by including the charge pump circuit 50 capable of flowing current between the input and output of the semiconductor integrated circuit 110 even when the input voltage VIN is lower than the output voltage VO, the semiconductor integrated circuit 110 achieves continuous current supply with respect to the DC current Idc.

[0043] Figure 5 1 is a diagram illustrating a bus system including a semiconductor integrated circuit according to the first embodiment. Figure 5 In the first embodiment shown, the above description is cited, and the description of the same structure, function, and effect as those of the first comparative embodiment is omitted or simplified.

[0044] Figure 5 The bus system 301 shown includes a pair of wirings 81 and 82 to which a DC voltage is applied by a DC power supply 88, a choke coil 87 inserted into the pair of wirings 81 and 82, and a semiconductor integrated circuit 110 that extracts the DC voltage from the pair of wirings 81 and 82. Based on the DC voltage extracted from the pair of wirings 81 and 82, the semiconductor integrated circuit 110 supplies a DC output current Io to a subsequent load 85.

[0045] Wiring 81 is an example of a first wiring electrically connected to the first power input terminal (terminal INP). In this example, terminal INP is electrically connected to the first output terminal of diode bridge 80, which is inserted into the pair of wirings 81 and 82. Wiring 82 is an example of a second wiring electrically connected to the second power input terminal (terminal INN). In this example, terminal INN is electrically connected to the second output terminal of diode bridge 80, which is inserted into the pair of wirings 81 and 82.

[0046] exist Figure 5 In the figure, the semiconductor integrated circuit 110 has a first power input terminal (terminal INP), a second power input terminal (terminal INN), a first power output terminal (terminal OUTP), a second power output terminal (terminal OUTN), power lines 71, 72, AC filters 10, 20, a backflow prevention circuit 30, a bypass line 73, a charge pump circuit 50, a bypass switch 70 and a control circuit 60.

[0047] The semiconductor integrated circuit 110 extracts a DC voltage from the voltage (input voltage VIN) input to the pair of terminals INP and INN via the AC filters 10 and 20 , and outputs the extracted DC voltage as an output voltage VO from the pair of terminals OUTP and OUTN to the load 85 .

[0048] The power supply line 71 is an example of a first power supply line that connects a first power supply input terminal (terminal INP) and a first power supply output terminal (terminal OUTP). A current flows through the power supply line 71 from the terminal INP to the terminal OUTP.

[0049] The power supply line 72 is an example of a second power supply line that connects the second power supply input terminal (terminal INN) and the second power supply output terminal (terminal OUTN). A current flows through the power supply line 72 from the terminal OUTN to the terminal INN.

[0050] AC filter 10 is an example of a first AC filter installed on the first power line (power line 71). AC filter 10 is a circuit that operates like an inductor, attenuating signals with frequencies higher than a predetermined frequency. AC filter 10 attenuates high-frequency components of signals input and output from terminal INP. AC filter 10 is an integrated circuit that functions like a discrete choke coil.

[0051] AC filter 20 is an example of a second AC filter provided on the second power line (power line 72). AC filter 20 is a circuit that operates like an inductor, attenuating signals with frequencies higher than a predetermined frequency. AC filter 20 attenuates high-frequency components of signals input and output from terminal INN. AC filter 20 is an integrated circuit that functions like a discrete choke coil.

[0052] Backflow prevention circuit 30 is an example of a first backflow prevention circuit provided on a first power line (power line 71) between a first AC filter (AC filter 10) and a first power output terminal (terminal OUTP). Backflow prevention circuit 30 is an integrated circuit that blocks reverse current flowing from terminal OUTP to terminal INP.

[0053] Bypass line 73 is an example of a bypass line that bypasses the first backflow prevention circuit (backflow prevention circuit 30). Bypass line 73 has one end connected to the power line portion between the AC filter 10 and the backflow prevention circuit 30, and the other end connected to the power line portion between the terminal OUTP and the backflow prevention circuit 30. Bypass line 73 is a current path that bypasses the backflow prevention circuit 30.

[0054] The charge pump circuit 50 is provided on the bypass line 73. The charge pump circuit 50 is a voltage conversion circuit that can step up, step down, or invert the input voltage to the charge pump circuit 50 using capacitors 55 and 84 external to the semiconductor integrated circuit 110. For example, the charge pump circuit 50 outputs a voltage higher than the input voltage VCH by stepping up the input voltage VCH to the charge pump circuit 50.

[0055] The bypass switch 70 is provided on a bypass line 73 between the AC filter 10 and the charge pump circuit 50. The bypass switch 70 is a semiconductor switch such as a MOSFET that is turned on and off by the control circuit 60. Alternatively, the bypass switch 70 may be provided on the bypass line 73 between the terminal OUTP and the charge pump circuit 50.

[0056] The control circuit 60 monitors the decrease in the input voltage VIN and, based on the monitoring result, controls the timing of activating the charge pump circuit 50. In this example, the control circuit 60 controls the timing of activating the charge pump circuit 50 by turning the bypass switch 70 on or off.

[0057] Figure 6 This example includes Figure 5 The waveform diagram of each component of the bus system 301 of the semiconductor integrated circuit 110 according to the first embodiment is shown. An AMI signal with a phase opposite to that of the AMI signal input to the terminal INP is input to the terminal INN. The semiconductor integrated circuit 110 extracts a DC voltage from the input voltage VIN, which is the potential difference between the terminals INP and INN, through the AC filters 10 and 20. The DC output voltage VO, which is the potential difference between the pair of terminals OUTP and OUTN, is output to the load 85.

[0058] As in the case of the first comparison method, Figure 6As shown, a period in which the input voltage VIN is lower than the output voltage VO may occur in a quarter cycle. When the potential of terminal INP is lower than the potential of terminal OUTP, no current flows from terminal INP to terminal OUTP. Similarly, when the potential of terminal INN is higher than the potential of terminal OUTP, no current flows from terminal OUTN to terminal INN.

[0059] The control circuit 60 of the first embodiment compares the input voltage VIN with a first voltage (hereinafter also referred to as "voltage V1"). When the input voltage VIN is lower than voltage V1, the control circuit 60 determines that the input voltage VIN is lower than the output voltage VO. Voltage V1 is, for example, a threshold voltage generated within the control circuit 60. When the input voltage VIN is lower than voltage V1, the control circuit 60 turns on the bypass switch 70. By turning on the bypass switch 70, the control circuit 60 activates the charge pump circuit 50, causing the supplemental current Ib from the charge pump circuit 50 to flow through the bypass line 73 and the terminal OUTP.

[0060] By operating the charge pump circuit 50 in this manner, during the period when the input voltage VIN is lower than the output voltage VO, the output current Io is supplemented by the supplementary current Ib, thereby achieving continuous current supply to the load 85. Thus, for example, the circuit scale can be reduced by reducing the capacitance of the capacitor 84 connected between the pair of terminals OUTP and OUTN. Furthermore, during the period when the input voltage VIN is lower than the output voltage VO, the supplementary current Ib is output from the semiconductor integrated circuit 110 to the load 85, thereby improving the efficiency of the output power of the semiconductor integrated circuit 110 relative to the input power compared to the first comparison method. Furthermore, since the discharge circuit 103 as in the first comparison method is not required, heat generation is suppressed. Thus, it is easy to apply to applications with high input voltage and high current. Furthermore, the range (types) of packages that can be selected to accommodate the semiconductor integrated circuit 110 is expanded.

[0061] Furthermore, due to the charge pump circuit 50 operating in this manner, during the period when the input voltage VIN is lower than the output voltage VO, the input current Ia to the charge pump circuit 50 and the supplementary current Ib output from the charge pump circuit 50 flow through the bypass line 73. Consequently, even during the period when the input voltage VIN is lower than the output voltage VO, current can flow between the input and output of the semiconductor integrated circuit 110, bypassing the backflow prevention circuit 30. This enables continuous current supply of the DC current Idc. The input current Ia is the current input from the terminal INP to the charge pump circuit 50 via the bypass switch 70. The supplementary current Ib is the current supplied from the charge pump circuit 50 to the terminal OUTP.

[0062] When input voltage VIN exceeds voltage V1, control circuit 60 turns bypass switch 70 off, thereby disconnecting bypass line 73. By turning bypass switch 70 off, control circuit 60 halts the charge pump circuit 50's operation to flow supplemental current Ib from charge pump circuit 50 through bypass line 73 and terminal OUTP. Consequently, while input voltage VIN exceeds output voltage VO, current does not flow through bypass line 73, allowing current to flow between the input and output of semiconductor integrated circuit 110 via backflow prevention circuit 30. This ensures a continuous supply of DC current Idc.

[0063] Figure 7 This is a diagram showing a first configuration example of the semiconductor integrated circuit according to the first embodiment. Figure 7 The semiconductor integrated circuit 110A shown is an embodiment of the semiconductor integrated circuit 110 described above. The semiconductor integrated circuit 110A further includes a first capacitor connection terminal (terminal CFP), a second capacitor connection terminal (terminal CFN), a backflow prevention circuit 40 , a regulator 75 , and an overcurrent protection circuit 74 .

[0064] Capacitor 11 is an external capacitive element located between terminals CFP and INP. The filtering characteristics of AC filter 10 can be adjusted based on the capacitance value of capacitor 11. Capacitor 21 is an external capacitive element located between terminals CFN and INN. The filtering characteristics of AC filter 20 can be adjusted based on the capacitance value of capacitor 21. Zener diode 83 is an external element located between terminals INP and INN. The surge withstand capability between terminals INP and INN can be adjusted based on the Zener voltage of Zener diode 83.

[0065] The regulator 75 is a circuit that generates a constant voltage REG based on the input voltage VIN. Each circuit unit in the semiconductor integrated circuit 110A operates based on the constant voltage REG.

[0066] Backflow prevention circuit 40 is an example of a second backflow prevention circuit provided on a second power line (power line 72) between the second AC filter (AC filter 20) and the second power output terminal (terminal OUTN). Backflow prevention circuit 40 is an integrated circuit that blocks reverse current flowing from terminal INN to terminal OUTN.

[0067] The backflow prevention circuit 30 includes a synchronous switch 31 inserted into the power line 71 and a backflow monitoring circuit 32 that monitors the backflow current flowing through the synchronous switch 31. The synchronous switch 31 (P_SW) is, for example, a P-channel MOSFET. The backflow monitoring circuit 32 monitors the voltage across the synchronous switch 31 and, upon detecting a polarity reversal, turns off the synchronous switch 31. This prevents backflow current from flowing into the power line 71. The control circuit 60 can turn off the synchronous switch 31 when the input voltage VIN is lower than the voltage V1, and can turn on the synchronous switch 31 when the input voltage VIN is higher than the voltage V1.

[0068] The backflow prevention circuit 40 includes a synchronous switch 41 inserted into the power line 72 and a backflow monitoring circuit 42 that monitors the backflow current flowing through the synchronous switch 41. The synchronous switch 41 (N_SW) is, for example, an N-channel MOSFET. The backflow monitoring circuit 42 monitors the voltage across the synchronous switch 41 and, upon detecting a polarity reversal in the voltage across the synchronous switch 41, opens the synchronous switch 41. This prevents backflow current from flowing into the power line 72. The control circuit 60 does not necessarily need to open the synchronous switch 41 based on the magnitude of the input voltage VIN.

[0069] The overcurrent protection circuit 74 monitors the current flowing through the power supply line 72 and, when detecting a current exceeding a predetermined value, shuts off the power supply line 72. Thus, the overcurrent protection circuit 74 protects the semiconductor integrated circuit 110A from the overcurrent flowing through the power supply line 72.

[0070] The charge pump circuit 50 includes an oscillator 54 (OSC), a switch control circuit 53, and switches 51 and 52. The switch control circuit 53 controls the on / off switching of switches 51 and 52 according to a pulse signal from the oscillator 54, thereby controlling the charging and discharging of the capacitor 55. Consequently, even when the input voltage VIN is lower than the output voltage VO, current flows through the terminal INP, the AC filter 10, the bypass switch 70, the charge pump circuit 50, the terminal OUTP, and the load 85 in this order.

[0071] Based on the output voltage HACT of the AC filter 10, the bypass switch 70 controls the input voltage VCH, which serves as the power supply voltage for the charge pump circuit 50. The illustrated charge pump circuit 50 is a double-step-up circuit, and therefore controls the input voltage VCH to half of VIN. This allows the semiconductor integrated circuit 110A to make the output voltage VO track the input voltage VIN, so that the output voltage VO is equal to the input voltage VIN.

[0072] The control circuit 60 includes a detection circuit 61 connected to a pair of terminals INP and INN, and drive circuits 62, 63, and 64 that receive detection signals representing detection results from the detection circuit 61. The detection circuit 61 detects a decrease in the input voltage VIN. The detection circuit 61 can detect a decrease in the input voltage VIN by detecting a decrease in the internal current flowing between the pair of terminals INP and INN via the detection circuit 61.

[0073] The drive circuit 63 controls the on / off switching of the bypass switch 70. The drive circuit 62 controls the on / off switching of the synchronization switch 31. The drive circuit 64 controls the on / off switching of the synchronization switch 41.

[0074] Figure 8 This is a diagram showing a second configuration example of the semiconductor integrated circuit according to the first embodiment. Figure 8 The semiconductor integrated circuit 110B shown is a modified example of the semiconductor integrated circuit 110A described above. The semiconductor integrated circuit 110B differs from the semiconductor integrated circuit 110A described above in that a bypass terminal (terminal BYP) and a capacitor 86 are added.

[0075] Terminal BYP is a terminal for connecting a capacitive element internally connected between bypass switch 70 and the input portion of charge pump circuit 50. Capacitor 86 is an external capacitive element connected between terminal BYP and terminal INN. Externally connecting capacitor 86 improves the stability of input voltage VCH, which serves as the power supply voltage for charge pump circuit 50.

[0076] Figure 9 This is a diagram showing a third configuration example of the semiconductor integrated circuit according to the first embodiment. Figure 9 The semiconductor integrated circuit 110C shown is a modification of the semiconductor integrated circuit 110B described above. The semiconductor integrated circuit 110C differs from the semiconductor integrated circuit 110B described above in that it does not have the terminal OUTN, the power supply line 72, the AC filter 20, or the backflow prevention circuit 40. The terminal BYP and the capacitor 86 may also be omitted.

[0077] The semiconductor integrated circuits 110A and 110B described above have a filter configuration of two channels, INP-OUTP and INN-OUTN. In contrast, the semiconductor integrated circuit 110C has a filter configuration of one channel, INP-OUTP.

[0078] Figure 10 This is a diagram showing a fourth configuration example of the semiconductor integrated circuit according to the first embodiment. Figure 10The semiconductor integrated circuit 110D shown is a modification of the semiconductor integrated circuit 110B described above. The semiconductor integrated circuit 110D differs from the semiconductor integrated circuit 110B described above in that it does not have the terminal OUTP, the power supply line 71, the AC filter 10, or the backflow prevention circuit 40. The terminal BYP and the capacitor 86 may also be omitted.

[0079] In contrast to the semiconductor integrated circuit 110C, the semiconductor integrated circuit 110D has a filter structure of one channel, INN-OUTN.

[0080] exist Figure 10 In this case, unlike the above-mentioned semiconductor integrated circuit 110A, the terminal INN is an example of a first power input terminal, the terminal INP is an example of a second power input terminal, the terminal OUTN is an example of a first power output terminal, the power line 72 is an example of a first power line, the AC filter 20 is an example of a first AC filter, and the backflow prevention circuit 40 is an example of a first backflow prevention circuit.

[0081] Figure 10 The charge pump circuit 50 generates a negative voltage. When the input voltage VIN is lower than the voltage V1, the control circuit 60 turns on the bypass switch 70, thereby activating the charge pump circuit 50 and causing the supplementary current Ib from the charge pump circuit 50 to flow through the bypass line 73 and the terminal OUTN. Consequently, even when the input voltage VIN is lower than the output voltage VO, current flows in the order of the load 85, the terminal OUTN, the charge pump circuit 50, the bypass switch 70, the AC filter 20, and the terminal INN.

[0082] Figure 11 This diagram illustrates a portion of a control circuit included in a semiconductor integrated circuit. A detection circuit 61 within the control circuit 60 operates based on a constant voltage REG generated by a regulator 75. The detection circuit 61 includes a current detection circuit 65 that detects an internal current i flowing between terminals INP and INN, and a comparison circuit 66 that compares the internal current i detected by the current detection circuit 65 with a first current (hereinafter also referred to as "current I1"). The internal current i is proportional to the input voltage VIN. As the input voltage VIN decreases, the internal current i decreases.

[0083] When the internal current i detected by the current detection circuit 65 becomes lower than the current I1 due to a decrease in the input voltage VIN, the comparator circuit 66 determines that the input voltage VIN is lower than the aforementioned voltage V1. When the internal current i is lower than the current I1, the comparator circuit 66 outputs a signal to activate the charge pump circuit 50 as described above. Thus, even when the input voltage VIN is lower than the output voltage VO, current is supplied to the load 85. On the other hand, when the internal current i is higher than the current I1, the comparator circuit 66 outputs a signal to stop the charge pump circuit 50. This stops the current flowing through the bypass line 73.

[0084] Figure 12 1 is a diagram showing a first configuration example of an AC filter included in a semiconductor integrated circuit. The AC filter 10A is an example of the AC filter 10 described above. The AC filter 20A is an example of the AC filter 20 described above.

[0085] AC filter 10A is an active inductor comprising a P-channel MOS transistor 12 connected in series with power line 71, and a resistor 13 connected between the gate and drain of MOS transistor 12. The source of MOS transistor 12 is connected to terminal INP, and the gate is connected to terminal CFP. The voltage Vds between the drain and source of MOS transistor 12 is determined by the voltage Vgs between the gate and source of MOS transistor 12. The impedance of AC filter 10A can be adjusted by the capacitance of capacitor 11.

[0086] AC filter 20A is an active inductor comprising an N-channel MOS transistor 22 connected in series with power line 72, and a resistor 23 connected between the gate and drain of MOS transistor 22. The source of MOS transistor 22 is connected to terminal INN, and the gate is connected to terminal CFN. The voltage Vds between the drain and source of MOS transistor 12 is determined by the voltage Vgs between the gate and source of MOS transistor 12. The impedance of AC filter 20A can be adjusted by the capacitance of capacitor 21.

[0087] Figure 13 10B is an example of the AC filter 10 described above. 20B is an example of the AC filter 20 described above.

[0088] AC filter 10B is a filter amplifier comprising a MOS transistor 12, resistors 15 and 16, a voltage source 17, and an operational amplifier 18. Resistor 15 is connected between terminal INP and terminal CFP1. Resistor 16 and voltage source 17 are connected between terminal CFP1 and the inverting input terminal of operational amplifier 18. The output of operational amplifier 18 is connected to the gate of MOS transistor 12. The non-inverting input terminal of operational amplifier 18 is connected to terminal CFP2 and the drain of MOS transistor 12. An external capacitor 14 is provided between a pair of terminals CFP1 and CFP2 provided on a semiconductor integrated circuit. This structure reduces the drop in voltage Vds between the drain and source of MOS transistor 12, thereby reducing losses and improving efficiency between input and output. The impedance of AC filter 10B can be adjusted by adjusting the capacitance value of capacitor 14.

[0089] AC filter 20B is a filter amplifier comprising a MOS transistor 22, resistors 25 and 26, a voltage source 27, and an operational amplifier 28. Resistor 25 is connected between terminal INN and terminal CFN1. Resistor 26 and voltage source 27 are connected between terminal CFN1 and the inverting input terminal of operational amplifier 28. The output of operational amplifier 28 is connected to the gate of MOS transistor 22. The non-inverting input terminal of operational amplifier 28 is connected to terminal CFN2 and the drain of MOS transistor 22. An external capacitor 24 is provided between a pair of terminals CFN1 and CFN2 provided on the semiconductor integrated circuit. This structure reduces the drop in voltage Vds between the drain and source of MOS transistor 22, thereby reducing losses and improving efficiency between input and output. The impedance of AC filter 20B can be adjusted by adjusting the capacitance value of capacitor 24.

[0090] Figure 14 This diagram illustrates a circuit for implementing thermal shutdown. A semiconductor integrated circuit may also include a thermal shutdown circuit 90 that detects overheating and shuts off current flowing between the input and output of the semiconductor integrated circuit. This provides thermal protection for the semiconductor integrated circuit. For example, when thermal shutdown circuit 90 detects overheating, it opens at least one of switch 91 connected between the gate and source of MOS transistor 12 and switch 92 connected between the gate and source of MOS transistor 22. This shuts off current flowing through power lines 71 and 72, thereby suppressing overheating.

[0091] As described above, the embodiments have been described, but the embodiments are presented as examples, and the present invention is not limited to the embodiments. The embodiments can be implemented in various other ways, and various combinations, omissions, substitutions, and modifications can be made without departing from the scope of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included in the invention described in the scope of patent protection and its equivalents.

[0092] For example, the signals transmitted and received by the semiconductor integrated circuit are not limited to differential signals, but may also be single-ended signals. The communication method may also be different from the AMI method.

[0093] Devices equipped with semiconductor integrated circuits are not limited to air conditioners; they may also include other devices such as telephones, security equipment, audio equipment, video equipment, and communications equipment. A semiconductor integrated circuit may be an IC that simply supplies a DC voltage from wiring and supplies current to a load, or it may be an IC that not only supplies this power but also has other functions, such as the ability to transmit and receive signals with other communication partners via wiring.

[0094] Description of Reference Signs

[0095] 10, 10A, 10B, 20, 20A, 20B AC filters

[0096] 11, 14, 21, 24, 55, 84, 86, 121, 121 capacitors

[0097] 12, 22MOS transistor

[0098] 13, 15, 16, 23, 25, 26 resistors

[0099] 17, 27 voltage source

[0100] 18, 28 operational amplifiers

[0101] 30, 40 backflow prevention circuit

[0102] 31, 41 synchronous switch

[0103] 32, 42 reverse current monitoring circuit

[0104] 50 charge pump circuit

[0105] 51, 52, 91, 92 switches

[0106] 53 switch control circuit

[0107] 54 Oscillator

[0108] 60 control circuit

[0109] 61 detection circuit

[0110] 62, 63, 64 drive circuit

[0111] 65 current detection circuit

[0112] 66 comparison circuit

[0113] 70 bypass switch

[0114] 71, 72 power cord

[0115] Route 73 Bypass

[0116] 74 Overcurrent protection circuit

[0117] 75 regulator

[0118] 80 diode bridge

[0119] 81, 82 wiring

[0120] 83 Zener diode

[0121] 85, 221, 222, 223, 224, 225 load

[0122] 87 choke coil

[0123] 88 DC power supply

[0124] 90° thermal shutdown circuit

[0125] 100, 110, 110A, 110B, 110C, 110D semiconductor integrated circuits

[0126] 101, 102 filter circuit

[0127] 103 discharge circuit

[0128] 120 driver IC

[0129] 201, 203 indoor units

[0130] 202, 204 remote control terminals

[0131] 205 outdoor unit

[0132] 211, 212, 213, 214, 215 drivers

[0133] 300, 301, 1000 bus systems.

Claims

1. A semiconductor integrated circuit, characterized in that: have: a first power input terminal; a second power input terminal; a first power output terminal; a first power line connecting the first power input terminal and the first power output terminal; a first AC filter, which is provided on the first power line; a first backflow prevention circuit provided on the first power line between the first AC filter and the first power output terminal; a bypass line that bypasses the first backflow prevention circuit; a charge pump circuit, which is arranged on the bypass line; as well as The control circuit operates the charge pump circuit to allow current to flow through the bypass line and the first power output terminal when an input voltage between the first power input terminal and the second power input terminal is lower than a first voltage.

2. The semiconductor integrated circuit according to claim 1, wherein: When the input voltage is higher than the first voltage, the control circuit stops the operation of the charge pump circuit for causing current to flow through the bypass line and the first power output terminal.

3. The semiconductor integrated circuit according to claim 2, wherein: When the input voltage is higher than the first voltage, the control circuit cuts off the bypass line.

4. The semiconductor integrated circuit according to claim 1, wherein The control circuit detects an internal current flowing between the first power input terminal and the second power input terminal. When the internal current becomes lower than a first current due to a decrease in the input voltage, the control circuit activates the charge pump circuit to allow current to flow through the bypass line and the first power output terminal.

5. The semiconductor integrated circuit according to claim 4, wherein: When the internal current is higher than the first current, the control circuit stops the operation of the charge pump circuit for causing the current to flow through the bypass line and the first power supply output terminal.

6. The semiconductor integrated circuit according to claim 5, wherein: When the internal current is higher than the first current, the control circuit cuts off the bypass line.

7. The semiconductor integrated circuit according to any one of claims 1 to 6, wherein: The semiconductor integrated circuit further includes a bypass switch provided on the bypass line between the first AC filter and the charge pump circuit. When the input voltage is lower than the first voltage, the control circuit turns on the bypass switch.

8. The semiconductor integrated circuit according to claim 7, wherein: The semiconductor integrated circuit further includes a terminal for connecting a capacitor element connected between the bypass switch and an input portion of the charge pump circuit.

9. The semiconductor integrated circuit according to any one of claims 1 to 6, wherein: The semiconductor integrated circuit further comprises: a second power output terminal; a second power line connecting the second power input terminal and the second power output terminal; and A second AC filter is provided on the second power line.

10. The semiconductor integrated circuit according to claim 9, wherein: The semiconductor integrated circuit further includes a second backflow prevention circuit provided on the second power line between the second AC filter and the second power output terminal.

11. A device, characterized in that: have: semiconductor integrated circuits; and load, which is powered from the semiconductor integrated circuit, The semiconductor integrated circuit comprises: a first power input terminal; a second power input terminal; a first power output terminal electrically connected to the load; a first power line connecting the first power input terminal and the first power output terminal; a first AC filter, which is provided on the first power line; a first backflow prevention circuit provided on the first power line between the first AC filter and the first power output terminal; a bypass line that bypasses the first backflow prevention circuit; a charge pump circuit disposed on the bypass line; as well as The control circuit operates the charge pump circuit to allow current to flow through the bypass line and the first power output terminal when an input voltage between the first power input terminal and the second power input terminal is lower than a first voltage.

12. A bus system, characterized in that: have: The semiconductor integrated circuit according to claim 1; and A pair of wiring, The pair of wirings includes a first wiring electrically connected to the first power input terminal and a second wiring electrically connected to the second power input terminal.

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